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Электронный компонент: EDD2508AETA-5C-E

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Document No. E0861E20 (Ver. 2.0)
Date Published April 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2006
PRELIMINARY DATA SHEET
256M bits DDR SDRAM
EDD2508AETA (32M words
8 bits)
Specifications
Density: 256M bits
Organization
8M words
8 bits
4 banks
Package: 66-pin plastic TSOP (II)
Lead-free (RoHS compliant)
Power supply:
DDR400: VDD,
VDDQ
=
2.6V
0.1V
DDR333, 266: VDD, VDDQ
=
2.5V
0.2V
Data rate: 400Mbps/333Mbps/266Mbps (max.)
Four internal banks for concurrent operation
Interface: SSTL_2
Burst lengths (BL): 2, 4, 8
Burst type (BT):
Sequential (2, 4, 8)
Interleave (2, 4, 8)
/CAS Latency (CL): 2, 2.5, 3
Precharge: auto precharge option for each burst
access
Driver strength: normal/weak
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period: 7.8
s
Operating ambient temperature range
TA = 0
C to +70
C
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
Data inputs, outputs, and DM are synchronized with
DQS
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
EDD2508AETA
Preliminary Data Sheet E0861E20 (Ver. 2.0)
2
Ordering Information

Part number
Mask
version
Organization
(words
bits)
Internal
banks
Data rate
Mbps (max.)
JEDEC speed bin
(CL-tRCD-tRP)

Package
EDD2508AETA-5B-E
EDD2508AETA-5C-E
E 32M
8
4
400
DDR400B (3-3-3)
DDR400C (3-4-4)
66-pin Plastic
TSOP (II)
EDD2508AETA-6B-E
333
DDR333B
(2.5-3-3)
EDD2508AETA-7A-E
EDD2508AETA-7B-E
266
DDR266A (2-3-3)
DDR266B (2.5-3-3)
Part Number
Elpida Memory
Density / Bank
25: 256M / 4-bank
Organization
8: x8
Power Supply, Interface
A: 2.5V, SSTL_2
Die Rev.
Package
TA: TSOP (II)
Speed
5B: DDR400B (3-3-3)
5C: DDR400C (3-4-4)
6B: DDR333B (2.5-3-3)
7A: DDR266A (2-3-3)
7B: DDR266B (2.5-3-3)
Environment Code
E: Lead Free
Product Family
D: DDR SDRAM
Type
D: Monolithic Device
E D D 25 08 A E TA - 5B - E
Speed Grade Compatibility
Operating
Frequencies
Speed bin
CL2
CL2.5
CL3
DDR400B
133MHz 166MHz 200MHz
DDR400C
133MHz 166MHz 200MHz
DDR333B
133MHz 166MHz 166MHz
DDR266A
133MHz 133MHz 133MHz
DDR266B
100MHz 133MHz 133MHz
EDD2508AETA
Preliminary Data Sheet E0861E20 (Ver. 2.0)
3
Pin Configurations
/xxx indicates active low signal.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
(Top view)
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
66-pin Plastic TSOP(II)
Pin name
Function
Pin name
Function
A0 to A12
Address inputs
CK
Clock input
BA0, BA1
Bank select address
/CK
Differential Clock input
DQ0 to DQ7
Data-input/output
CKE
Clock enable
DQS
Input and output data strobe
VREF
Input reference voltage
/CS
Chip select
VDD
Power for internal circuit
/RAS
Row address strobe command
VSS
Ground for internal circuit
/CAS
Column address strobe command
VDDQ
Power for DQ circuit
/WE
Write enable
VSSQ
Ground for DQ circuit
DM
Input mask
NC
No connection
EDD2508AETA
Preliminary Data Sheet E0861E20 (Ver. 2.0)
4
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Speed Grade Compatibility............................................................................................................................2
Pin Configurations .........................................................................................................................................3
Electrical Specifications.................................................................................................................................5
Block Diagram .............................................................................................................................................13
Pin Function.................................................................................................................................................14
Command Operation ...................................................................................................................................16
Simplified State Diagram .............................................................................................................................23
Operation of the DDR SDRAM ....................................................................................................................24
Timing Waveforms.......................................................................................................................................43
Package Drawing ........................................................................................................................................49
Recommended Soldering Conditions..........................................................................................................50
EDD2508AETA
Preliminary Data Sheet E0861E20 (Ver. 2.0)
5
Electrical Specifications
All voltages are referenced to VSS (GND).
After power up, wait more than 200 s and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter Symbol
Rating Unit
Note
Voltage on any pin relative to VSS
VT
1.0 to +3.6
V
Supply voltage relative to VSS
VDD
1.0 to +3.6
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
1.0
W
Operating ambient temperature
TA
0 to +70
C
Storage temperature
Tstg
55 to +125
C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0
C to +70
C)
Parameter Symbol
Speed
min.
typ.
max.
Unit
Notes
Supply voltage
VDD,VDDQ
DDR400
2.5
2.6
2.7
V
1
VDD,
VDDQ
DDR333,
266
2.3
2.5
2.7
V
1
VSS,
VSSQ
0 0 0 V
Input reference voltage
VREF
0.49
VDDQ 0.50
VDDQ 0.51
VDDQ
V
Termination voltage
VTT
VREF 0.04
VREF
VREF + 0.04
V
Input high voltage
VIH (DC)
VREF + 0.15
--
VDDQ + 0.3
V
2
Input low voltage
VIL (DC)
0.3
--
VREF 0.15
V
3
Input voltage level,
CK and /CK inputs
VIN (DC)
0.3
--
VDDQ + 0.3
V
4
Input differential cross point
voltage, CK and /CK inputs
VIX (DC)
0.5
VDDQ
-
0.2V
0.5
VDDQ
0.5
VDDQ +
0.2V
V
Input differential voltage,
CK and /CK inputs
VID (DC)
0.36
--
VDDQ + 0.6
V
5, 6
Notes: 1. VDDQ must be lower than or equal to VDD.
2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
3. VIL is allowed to outreach below VSS down to 1.0V for the period shorter than or equal to 5ns.
4. VIN (DC) specifies the allowable DC execution of each differential input.
5. VID (DC) specifies the input differential voltage required for switching.
6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF 0.18V
if measurement.