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Электронный компонент: EDD2508AKTA-5

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Document No. E0349E60 (Ver. 6.0)
Date Published February 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003-2005
PRELIMINARY DATA SHEET
256M bits DDR SDRAM
EDD2508AKTA-5 (32M words
8 bits, DDR400)
Description
The EDD2508AKTA-5 is a 256M bits DDR SDRAM
organized as 8,388,608 words
8 bits
4 banks.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 2 bits prefetch-pipelined
architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
It is packaged in 66-pin plastic TSOP (II).
Features
Power supply: VDDQ = 2.6V
0.1V
: VDD = 2.6V
0.1V
Data rate: 400Mbps (max.)
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs, outputs, and DM are synchronized with
DQS
4 internal banks for concurrent operation
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
SSTL_2 compatible I/O
Programmable burst length (BL): 2, 4, 8
Programmable /CAS latency (CL): 3
Programmable output driver strength: normal/weak
Refresh cycles: 8192 refresh cycles/64ms
7.8
s maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
Pin Configurations
/xxx indicates active low signal.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
(Top view)
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
A0 to A12
BA0, BA1
DQ0 to DQ7
DQS
/CS
/RAS
/CAS
/WE
DM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
66-pin Plastic TSOP(II)
EDD2508AKTA-5
Preliminary Data Sheet E0349E60 (Ver. 6.0)
2
Ordering Information

Part number
Mask
version
Organization
(words
bits)
Internal
banks
Data rate
Mbps (max.)
JEDEC speed bin
(CL-tRCD-tRP)

Package
EDD2508AKTA-5B
EDD2508AKTA-5C
K 32M
8
4
400
DDR400B (3-3-3)
DDR400C (3-4-4)
66-pin Plastic
TSOP (II)
Part Number
Elpida Memory
Density / Bank
25: 256M / 4-bank
Organization
8: x8
Power Supply, Interface
A: 2.5V, SSTL_2
Die Rev.
Package
TA: TSOP (II)
Speed
5B: DDR400B (3-3-3)
5C: DDR400C (3-4-4)
Product Family
D: DDR SDRAM
Type
D: Monolithic Device
E D D 25 08 A K TA - 5B
EDD2508AKTA-5
Preliminary Data Sheet E0349E60 (Ver. 6.0)
3
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram .............................................................................................................................................10
Pin Function.................................................................................................................................................11
Command Operation ...................................................................................................................................13
Simplified State Diagram .............................................................................................................................20
Operation of the DDR SDRAM ....................................................................................................................21
Timing Waveforms.......................................................................................................................................39
Package Drawing ........................................................................................................................................45
Recommended Soldering Conditions..........................................................................................................46
EDD2508AKTA-5
Preliminary Data Sheet E0349E60 (Ver. 6.0)
4
Electrical Specifications
All voltages are referenced to VSS (GND).
After power up, wait more than 200 s and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter Symbol
Rating Unit
Note
Voltage on any pin relative to VSS
VT
1.0 to +3.6
V
Supply voltage relative to VSS
VDD
1.0 to +3.6
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
1.0
W
Operating ambient temperature
TA
0 to +70
C
Storage temperature
Tstg
55 to +125
C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70
C)
Parameter Symbol
min.
typ.
max.
Unit
Notes
Supply voltage
VDD,
VDDQ
2.5 2.6
2.7 V
1
VSS,
VSSQ
0 0
0 V
Input reference voltage
VREF
0.49
VDDQ
0.50
VDDQ 0.51
VDDQ
V
Termination voltage
VTT
VREF 0.04
VREF
VREF + 0.04
V
Input high voltage
VIH (DC)
VREF + 0.15
--
VDDQ + 0.3
V
2
Input low voltage
VIL (DC)
0.3
--
VREF 0.15
V
3
Input voltage level,
CK and /CK inputs
VIN (DC)
0.3
--
VDDQ + 0.3
V
4
Input differential cross point
voltage, CK and /CK inputs
VIX (DC)
0.5
VDDQ
-
0.2V 0.5
VDDQ
0.5
VDDQ + 0.2V V
Input differential voltage,
CK and /CK inputs
VID (DC)
0.36
--
VDDQ + 0.6
V
5, 6
Notes: 1. VDDQ must be lower than or equal to VDD.
2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
3. VIL is allowed to outreach below VSS down to 1.0V for the period shorter than or equal to 5ns.
4. VIN (DC) specifies the allowable DC execution of each differential input.
5. VID (DC) specifies the input differential voltage required for switching.
6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF 0.18V
if measurement.
EDD2508AKTA-5
Preliminary Data Sheet E0349E60 (Ver. 6.0)
5
DC Characteristics 1 (TA = 0 to +70
C, VDD, VDDQ = 2.6V 0.1V, VSS, VSSQ = 0V)
max.
Parameter Symbol
Grade
8
Unit
Test condition
Notes
Operating current (ACT-PRE)
IDD0
-5B
-5C
110
100
mA
CKE VIH,
tRC = tRC (min.)
1, 2, 9
Operating current
(ACT-READ-PRE)
IDD1
-5B
-5C
140
130
mA
CKE VIH, BL = 4,CL = 3,
tRC = tRC (min.)
1, 2, 5
Idle power down standby current
IDD2P
3
mA
CKE VIL
4
Floating idle standby current
IDD2F
30
mA
CKE VIH, /CS VIH
DQ, DQS, DM = VREF
4, 5
Quiet idle standby current
IDD2Q
25
mA
CKE VIH, /CS VIH
DQ, DQS, DM = VREF
4, 10
Active power down standby current
IDD3P
20
mA
CKE VIL
3
Active standby current
IDD3N
60
mA
CKE VIH, /CS VIH
tRAS = tRAS (max.)
3, 5, 6
Operating current
(Burst read operation)
IDD4R
200
mA CKE
VIH, BL = 2, CL = 3
1, 2, 5, 6
Operating current
(Burst write operation)
IDD4W
210
mA CKE
VIH, BL = 2,CL = 3
1, 2, 5, 6
Auto Refresh current
IDD5
170
mA
tRFC = tRFC (min.),
Input VIL or VIH
Self refresh current
IDD6
3
mA
Input VDD 0.2 V
Input 0.2 V
Operating current
(4 banks interleaving)
IDD7A
320
mA
BL = 4
1, 5, 6, 7
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2.
One
bank
operation.
3.
One
bank
active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycle.
10. Command/Address stable at VIH or VIL.
DC Characteristics 2 (TA = 0 to +70
C, VDD, VDDQ = 2.6V 0.1V, VSS, VSSQ = 0V)
Parameter Symbol
min.
max.
Unit
Test
condition
Note
Input leakage current
ILI
2
2
A
VDD VIN VSS
Output leakage current
ILO
5
5
A
VDDQ VOUT VSS
Output high current
IOH
15.2
--
mA
VOUT = 1.95V
Output low current
IOL
15.2
--
mA
VOUT = 0.35V