EM39LV010
1M Bits (128Kx8) Flash Memory
SPECIFICATION
This specification is subject to change without further notice. (04.09.2004 V1.0)
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General Description
The EM39LV010 is a 1M bits Flash memory organized as 128K x 8 bits. The EM39LV010
uses 2.7-3.6V power supply for Program and Erase. Featuring high performance Flash
memory technology, the EM39LV010 provides a typical Byte-Program time of 11 sec and a
typical Sector-Erase time of 40 ms. The device uses Toggle Bit or Data# Polling to detect the
completion of the Program or Erase operation. To protect against inadvertent write, the
device has on-chip hardware and software data protection schemes. The device offers
typical 100,000 cycles endurance and a greater than 10 years data retention. The
EM39LV010 conforms to JEDEC standard pin outs for x8 memories. The EM39LV010 is
offered in package types of 32-lead PLCC, 32-pin TSOP, 48-ball FBGA, and known good dice
(KGD). For KGD, please contact ELAN Microelectronics or its representatives for detailed
information (see Appendix at the bottom of this specification for Ordering Information).
The EM39LV010 devices are developed for applications that require memories with
convenient and economical updating of program, data or configuration, e.g., Networking cards,
Card Readers, Graphic cards, Digital TV, MP3, Wireless Phones, etc.
Features
Single Power Supply
Full voltage range from 2.7 to 3.6 volts
for both read and write operations
Sector-Erase Capability
Uniform 4Kbyte sectors
Read Access Time
Access
time: 45, 70 and 90 ns
Power Consumption
Active
current: 15 mA (Typical)
Standby
current: 1
A (Typical)
Erase/Program Features
Sector-Erase
Time: 40 ms (Typical)
Chip-Erase
Time: 40 ms (Typical)
Byte-Program
Time: 11
s (Typical)
Chip
Rewrite
Time: 1.5 seconds (Typical)
Automatic Write Timing
Internal
V
PP
Generation
End-of-Program or End-of-Erase
Detection
Data#
Polling
Toggle
Bit
CMOS I/O Compatibility
JEDEC Standard
Pin-out and software command sets
compatible with single-power supply Flash
memory
High Reliability
Endurance cycles: 100K (Typical)
Data retention: 10 years
Package Option
32-lead PLCC
32-pin
TSOP
48-pin
FBGA
EM39LV010
1M Bits (128Kx8) Flash Memory
SPECIFICATION
This specification is subject to change without further notice. (04.09.2004 V1.0)
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Functional Block Diagram
X-Decoder
Flash
Memory Array
Y-Decoder
I/O Buffers and Data Latches
Address Buffer &
Latches
Control Logic
Mem ory Address
CE#
OE#
W E#
DQ7-DQ0
Figure 0a: Functional Block Diagram
Pin Assignments
PLCC
14 15 16 17 18 19 20
30
31
32
1
2
3
4
DQ1 DQ2 V
SS
DQ3DQ4 DQ5 DQ6
A12 A15 A16 NC V
DD
W E#
NC
5
6
7
8
9
10
11
12
13
DQ0
A7
A6
A5
A4
A3
A2
A1
A0
21
22
23
24
25
26
27
28
29
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
32-Lead PLCC
Top View
Figure 0b: 32-lead PLCC Pin Assignments
EM39LV010
1M Bits (128Kx8) Flash Memory
SPECIFICATION
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page
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TSOP
Standard TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
OE#
V
SS
A0
A4
A5
A6
A7
W E#
A8
A9
A11
A12
A13
NC
NC
A14
A15
V
DD
A16
A1
A2
A3
25
26
27
28
29
30
31
32
24
23
22
21
20
19
18
17
A10
CE#
Figure 0c: TSOP Pin Assignments
FBGA
A13
A9
W E#
A7
A3
FBG A
Top View , Balls Facing D ow n
A14
A15
A16
V
SS
A8
A10
A11
DQ 6
NC
NC
DQ 5
V
DD
DQ 4
N C
NC
DQ 2
A17
A4
A6
A2
A5
A1
DQ 0
A0
CE#
O E#
DQ 1
V
SS
NC
N C
NC
A12
A19
DQ 7
NC
NC
DQ 3
V
DD
N C
NC
A18
NC
NC
Figure 0d: FBGA Pin Assignments
EM39LV010
1M Bits (128Kx8) Flash Memory
SPECIFICATION
This specification is subject to change without further notice. (04.09.2004 V1.0)
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Pin Description
Pin Name
Function
A0A19 17
addresses
DQ7DQ0 Data
inputs/outputs
CE# Chip
enable
OE# Output
enable
WE# Write
enable
V
DD
2.7-3.6 volt single power supply
V
SS
Device
ground
NC
Pin not connected internally
Table 1: Pin Description
Device Operation
The EM39LV010 uses Commands to initiate the memory operation functions. The
Commands are written to the device by asserting WE# Low while keeping CE# Low. The
address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data
bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the EM39LV010 is controlled by CE# and OE#. Both have to be Low
for the system to obtain data from the outputs. CE# is used for device selection. When CE#
is high, the chip is deselected and only standby power is consumed. OE# is the output
control and is used to gate data from the output pins. The data bus is in high impedance state
when either CE# or OE# is high. Refer to the Read Cycle Timing Diagram in Figure 1 for
further details.
Byte Program
The EM39LV010 is programmed on a byte-by-byte basis. Before programming, the sector
where the byte is located; must be erased completely. The Program operation is
accomplished in three steps:
The first step is a three-byte load sequence for Software Data Protection.
The second step is to load byte address and byte data. During the Byte Program
operation, the addresses are latched on the falling edge of either CE# or WE#, whichever
occurs last; and the data is latched on the rising edge of either CE# or WE#, whichever
occurs first.
The third step is the internal Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated,
will be completed within 16 s. See Figures 2 and 3 for WE# and CE# controlled
Program operation timing diagrams respectively and Figure 12 for flowchart.
EM39LV010
1M Bits (128Kx8) Flash Memory
SPECIFICATION
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page
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During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During
internal Program operation, the host is free to perform additional tasks. Any command
issued during the internal Program operation is ignored.
EM39LV010 Device Operation
Operation
CE# OE# WE#
DQ
Address
Read V
IL
V
IL
V
IH
D
OUT
A
IN
Program V
IL
V
IH
V
IL
D
IN
A
IN
Erase V
IL
V
IH
V
IL
X
*
Sector address, XXH for Chip-Erase
Standby V
IH
X X
High
Z X
Write Inhibit
X
V
IL
X High
Z/D
OUT
X
Write Inhibit
X
X
V
IH
High
Z/D
OUT
X
Software Mode
V
IL
V
IL
V
IH
See
Table
3
Product
Identification
*
X can be V
IL
or V
IH
, but no other value.
Table 2: EM39LV010 Device Operation
Write Command/Command Sequence
The EM39LV010 provides two software methods to detect the completion of a Program or
Erase cycle in order to optimize the system write cycle time. The software detection includes
two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode
is enabled after the rising edge of WE#, which initiates the internal Program or Erase
operation. The actual completion of the write operation is asynchronous with the system;
therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid
data may appear to conflict with either DQ7 or DQ6. In order to prevent such spurious
rejection, when an erroneous result occurs, the software routine should include an additional
two times loop to read the accessed location. If both reads are valid, then the device has
completed the write cycle, otherwise the rejection is valid.
Chip Erase
The EM39LV010 provides Chip-Erase feature, which allows the entire memory array to be
erased to logic "1" state. The Chip-Erase operation is initiated by executing a six-byte
command sequence with Chip-Erase command (10H) at address 5555H in the last byte
sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#,
whichever occurs first. During the Erase operation, the only valid reads are Toggle Bit and
Data# Polling. See Table 3 for the command sequence, Figure 6 for timing diagram, and
Figure 15 for the flowchart. Any commands issued during the Chip-Erase operation are
ignored.
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