EM65240
240 COM/SEG Dot Matrix LCD Driver
* This specification are subject to be changed without notice.
4.8.2002
1
GENERAL DESCRIPTION
The EM65240 is a 240-channel LCD driver LSI used to drive large scale dot matrix LCD
panels, like PDA, personal computers and workstations. Which is made by power CMOS
high voltage process technology. Through the use of TCP technology, it is deal for
substantially decreasing the size of LCD module frame. This product can function as a
common and a segment driver, which is used for liquid crystal dot matrix display.
In common driver mode, it can be selected in single mode and dual mode by a mode pin (MD),
data input/output pins are bi-directional, four data shift direction are pin selectable.
In segment driver mode, it can be selected 4-bit parallel input mode or 8-bit parallel input mode
by a mode pin (MD).
FEATURES
Both common mode and segment mode
- Display duty application: up to 1/480 duty
-
Supply voltage for the logic system: +2.5 to +5.5V
-
Supply voltage for LCD driver: +15 to +42V
-
Number of LCD driver outputs: 240
-
Low output impedance
-
Low power consumption
-
CMOS silicon process (P-type Silicon substrate)
-
268 pin TCP (tape carrier package) package: EM65240U
Common mode
-
Shift clock frequency: 4.0MHz (Max.) (V
DD
=+2.5 to +5.5)
-
Built-in 240 bits bi-directional shift register (divisible into 120bits*2)
-
Available in a single mode or in a dual mode
-
Data input/output pins are bi-directional, four data shift direction are pin selectable.
-
Shift register circuit reset function when /DSPOF active
EM65240
240 COM/SEG Dot Matrix LCD Driver
* This specification are subject to be changed without notice.
4.8.2002
2
Segment mode
-
Shift clock frequency: 20MHz(Max.) (V
DD
=+ 5V
10%)
15MHz(Max.) (V
DD
=+ 3.5V to + 4.5V )
12MHz(Max.) (V
DD
=+ 2.5V to + 3.0V )
-
Adopts a data bus system
-
4-bits/8-bits parallel input mode are selected by MD pin
-
Automatic transfer function of an enable signal
-
Automatic counting function which, in the chip select, causes the internal clock to be
stopped by automatically counting 240 of input data
-
Line latch circuit reset function when /DSPOF active
PIN CONFIGURATION
V
0L
V
12L
V
43L
V
5L
VDD
S/C
EIO2
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
XCK
/DSPOF
LP
EIO1
FR
DIR
MD
TEST1
VSS
V
5R
V
43R
V
12R
V
0R
Y
24
0
Y
23
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Y
2
Y
1
Chip Surface
241 ------------------------------------------------------------------------------------------------------268
240---------------------------------------------------------------------------------------------------------------------1
Figure1 pin configuration
EM65240
240 COM/SEG Dot Matrix LCD Driver
* This specification are subject to be changed without notice.
4.8.2002
3
Table 1 pin designation
Pin NO. Symbol
I/O
Description
1 to240
Y
1
Y
240
O LCD driver output
241,268 V
OL
,V
OR
-
Power supply for LCD driver
242,267 V
12L
,V
12R
-
Power supply for LCD driver
243,266 V
43L
,V
43R
-
Power supply for LCD driver
244,265 V
5L
,V
5R
-
Power supply for LCD driver
245 V
DD
-
Power supply for logic system
246
S/C
I
Segment/common mode selection
247
259
EIO
2
EIO
1
I/O Input /output for chip select or data of shift
register
248 to 254
255
DI
0
DI
6
DI
7
I
Display data input for segment mode
Dual mode data input for common mode
256
XCK
I
Display data shift clock input for segment
mode
257
/DSPOF
I
Control input for non-select output level
258
LP
I
Latch pulse input/shift clock input for shift
register
260
FR
I
AC-converting signal input for LCD driver
waveform
261
DIR
I
Display data shift direction selection
262
MD
I
Mode selection input
263 TEST
1
I
Test mode selection input
264 V
SS
-
Ground (0 V)
EM65240
240 COM/SEG Dot Matrix LCD Driver
* This specification are subject to be changed without notice.
4.8.2002
4
PIN DESCRIPTIONS
Segment mode
Table2 pin description of segment mode
Symbol I/O
Connected
to
Functions
V
DD
I Power Supply Power supply for internal logic connects to
+2.5 to +5.5V
V
SS
I
GND
Connect to Ground
V
0R
V
0L
V
12R
V
12L
V
34R
V
34L
V
5R
V
5L
I Power Supply Power supply for LCD driver level
Normally
the bias voltage used is set by
resistor divider
Ensure that the voltage are set such that
V
SS
V
5
<V
34
<V
12
<V
0
To further reduce the difference between
the output waveforms of LCD driver output
pin Y
1
and Y
240
externally connect V
iR
and
V
iL
(i=0
12
34
5)
DI
0
DI
7
I
Controller Input for display data
In 4-bit parallel input mode
input data
into 4 pins DI
0
DI
3
In 8-bit parallel input mode
input data
into8 pins DI
0
DI
7
XCK
I
Controller Clock signal for taking display data
Data is read on the falling of the clock
pulse
LP
I
Controller Latch signal for display data
Data is latched on the falling edge of the
clock pulse
Selection of segment mode/common mode
S/C Mode
selection
H segment
mode
L common
mode
S/C I
Controller
EM65240
240 COM/SEG Dot Matrix LCD Driver
* This specification are subject to be changed without notice.
4.8.2002
5
Segment mode (continuous)
Directional selection for reading display
data
DIR
Data read direction
L Y
240
to Y
1
H Y
1
to Y
240
DIR I
Controller
/DSPOF
I
Controller Control signal for output deselect level
The input signal is level-shifted from logic
voltage level to LCD driver voltage level
and controls LCD drive circuit
When the signal is low
the output (Y
1
Y
240
) of LCD drive be set to level V
5
the
contents of line latch are reset
but read the
display data in the data latch regardless of
condition of /DSPOF
When this signal return to high, the
operation returns to the normal status.
FR
I
Controller AC signal for LCD driver
Input a frame inversion signal
The LCD driver output voltage level can
be set by line latch output signal and FR
signal
Mode selection
MD Mode
selection
H
4-bit parallel input
L
8-bit parallel input
MD I
Controller
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