High Efficiency Linear Power Supply with Accurate
Power Surveillance and Software Monitoring
Features
n
Highly accurate 5 V, 250 mA guaranteed output
n
Low dropout voltage, typically 260 mV at 250 mA
n
Low quiescent current, typically 175 A
n
Standby mode, maximum current 340 A (with
100 A load on OUTPUT)
n
Unregulated DC input can withstand -20 V reverse
battery and +60 V power transients
n
Fully operational for unregulated DC input voltage up
to 40 V and regulated output voltage down to 3.0 V
n
Reset output guaranteed for regulated output voltage
down to 1.2 V
n
No reverse output current
n
Very low temperature coefficient for the regulated
output
n
Current limiting
n
Comparator for voltage monitoring, voltage reference
1.52 V
n
Programmable reset voltage monitoring
n
Programmable power on reset (POR) delay
n
Watchdog with programmable time windows
guarantees a minimum time and a maximum time
between software clearing of the watchdog
n
Time base accuracy 10%
n
System enable output offers added security
n
TTL/CMOS compatible
n
-40 to +125C temperature range
n
PSOP2-16 package
Description
The A6250 of fers a high level of in te gra tion by com bin ing
volt age reg u la tion, volt age mon i tor ing and soft ware mon i -
tor ing in a 16 lead pack age. The volt age reg u la tor has a
low drop out volt age (typ. 260 mV at 250 mA) and a low
qui es cent cur rent (175 A). The qui es cent cur rent in -
creases only slightly in drop out pro long ing bat tery life.
Built-in pro tec tion in cludes a pos i tive tran sient ab sorber
for up to 60 V (load dump) and the abil ity to sur vive an un -
reg u lated in put volt age of -20 V (re verse bat tery). The in -
put may be con nected to ground or a re verse volt age
with out re verse cur rent flow from the out put to the in put. A
com para tor mon i tors the volt age ap plied at the V
IN
in put
com par ing it with an in ter nal 1.52 V ref er ence. The
power-on re set func tion is in i tial ized af ter V
IN
reaches 1.52
V and takes the re set out put in ac tive af ter T
POR
de pend ing
of ex ter nal re sis tance. The re set out put goes ac tive low
when the V
IN
volt age is less than 1.52 V. The RES and EN
out puts are guar an teed to be in a cor rect state for a reg u -
lated out put volt age as low as 1.2 V. The watch dog func -
tion mon i tors soft ware cy cle time and ex e cu tion. If
soft ware clears the watch dog too quickly (in cor rect cy cle
time) or too slowly (in cor rect ex e cu tion) it will cause the
sys tem to be re set. The sys tem en able out put pre vents
crit i cal con trol func tions be ing ac ti vated un til soft ware has
suc cess fully cleared the watch dog three times. Such a se -
cu rity could be used to pre vent mo tor con trols be ing en er -
gized on re peated re sets of a faulty sys tem.
Applications
n
Industrial electronics
n
Cellular telephones
n
Security systems
n
Battery powered products
n
High efficiency linear power supplies
n
Automotive electronics
1
A6250
EM MICROELECTRONIC-MARIN SA
Typical Operating Configuration
Pin Assignment
Fig. 1
Fig. 2
A6250
A6250
Absolute Maximum Ratings
Parameter
Symbol Conditions
Continuous voltage at INPUT to
V
SS
V
INPUT
-0.3 to +45 V
Transients on INPUT for
t< 100 ms and duty cycle 1%
V
TRANS
up to +60 V
Reverse supply voltage on INPUT V
REV
-20 V
Max. voltage at any signal pin
V
MAX
OUTPUT+0.3V
Min. voltage at any signal pin
V
MIN
V
SS
-0.3V
Storage temperature
T
STO
-65 to +150C
Operating junction temperature
T
J
max. 150 C
Electrostatic discharge max. To
MIL-STD-883C method 3015
V
Smax
1000V
Max. soldering conditions
T
Smax
250C x 10 s
Max. Output current
I
OUTPUTmax
300 mA
Ta ble 1
Stresses above these listed max i mum rat ings may cause
per ma nent dam age to the de vice. Ex po sure be yond
spec i fied op er at ing con di tions may af fect de vice re li abil ity
or cause mal func tion.
Decoupling Methods
The in put ca pac i tor is nec es sary to com pen sate the line
in flu ences. A re sis tor of approx. 1
con nected in se ries
with the in put ca pac i tor may be used to damp the os cil la -
tion of the in put ca pac i tor and in put in duc tivi ty. The ESR
value of the ca pac i tor plays a ma jor role re gard ing the ef fi -
ciency of the de coup ling. It is rec om mended also to con -
nect a ce ramic ca pac i tor (100 nF) di rectly at the IC's pins.
In gen eral the user must as sure that pulses on the in put
line have slew rates lower than 1 V/s. On the out put side,
the ca pac i tor is nec es sary for the sta bil ity of the reg u la tion
cir cuit. The sta bil ity is guar an teed for val ues of 22 F or
big ger. It is spe cially im por tant to choose a ca pac i tor with
a low ESR value. Tantal ca pac i tors are rec om mended.
See the notes re lated to Ta ble 2. Spe cial care must be
taken in dis turbed en vi ron ments (au to mo tive, prox im ity of
mo tors and re lays, etc.).
Handling Procedures
This de vice has built-in pro tec tion against high static volt -
ages or elec tric fields; how ever, anti-static pre cau tions
must be taken as for any other CMOS com po nent. Un less
oth er wise spec i fied, proper op er a tion can only oc cur
when all ter mi nal volt ages are kept within the sup ply volt -
age range. Un used in puts must al ways be tied to a de -
fined logic volt age level.
Operating Conditions
Parameter
Symbol Min. Max. Units
Operating junction
temperature
1)
T
J
-40
+125
C
INPUT voltage
2)
VI
NPUT
2.3
40
V
OUTPUT voltage
2)
3)
V
OUTPUT
1.2
V
RES & EN guaranteed
4)
V
OUTPUT
1.2
V
OUTPUT current
5)
I
OUTPUT
250
mA
Comparator input voltage
V
IN
0
V
OUTPUT
V
RC-oscillator programming
6)
R
10
1000
k
Thermal resistance from
junction to ambient
7)
- PSOP2-16
R
th(j-a)
30
90
C/W
Ta ble 2
1)
The max i mum op er at ing tem per a ture is con firmed by
sam pling at ini tial de vice qual i fi ca tion. In pro duc tion, all
de vices are tested at +125C.
2)
Full op er a tion guar an teed. To achieve the load reg u la tion
spec i fied in Ta ble 3 a 22 F ca pac i tor or greater is re quired
on the INPUT, see Fig. 8. The 22 F must have an ef fec tive
re sis tance
5
and a res o nant fre quency above 500 kHz.
3)
A 10 F load ca pac i tor and a 100 nF de coup ling ca pac i tor
are re quired on the reg u la tor OUTPUT for sta bil ity. The 10 F
must have an ef fec tive se ries re sis tance of
5
and a
res o nant fre quency above 500 kHz.
4)
RES must be pulled up ex ter nally to V
OUTPUT
even if it is
un used. (Note: RES and EN are used as in puts by EM test.)
5)
The OUTPUT cur rent will not ap ply for all pos si ble
com bi na tions of in put volt age and out put cur rent.
Com bi na tions that would re quire the A6250 to work above
the max i mum junc tion tem per a ture (+125 C) must be
avoided.
6)
Re sis tor val ues close to 1000 k
are not rec om mended for
ap pli ca tions work ing at 125 C.
7)
The ther mal re sis tance spec i fied as sumes the pack age is
sol dered to a PCB. The termal re sis tance's value de pends on
the PCB's struc ture. A typical value of 51 C/W has been
ob tained with a dual layer board, with the slug soldered to
the heat-sink area of the PCB (see Fig. 22).
2
A6250
3
A6250
Electrical Characteristics
V
INPUT
= 6.0 V, C
L
= 10 F + 100 nF, C
INPUT
= 22 F, T
J
= -40 to +125C, un less oth er wise spec i fied
Parameter
Symbol Test Conditions
Min.
Typ.
Max.
Unit
Supply current in standby mode
I
SS
R
EXT
= don't care, TCL = V
OUTPUT
,
V
IN
= 0 V, I
L
= 100 A
140
340
A
Supply current
1)
I
SS
R
EXT
= 100 k
, I/Ps at V
OUTPUT
,
O/Ps 1 M
to V
OUTPUT
, I
L
= 100 A
175
400
A
Supply current
1)
I
SS
R
EXT
= 100 k
,
I/Ps at V
OUTPUT
,
V
INPUT
= 8.0 V, O/Ps 1M
to V
OUTPUT
,
I
L
= 100 mA
1.7
4.2
mA
I
L
= 250 mA
7
15
mA
Output voltage
V
OUTPUT
I
L
= 100 A
4.85
5.15
V
Output voltage
V
OUTPUT
100 A
I
L
250 mA,
4.85
5.15
V
Output voltage temperature
coefficient
2)
V
th(coeff)
100
ppm/C
Line regulation
3)
V
LINE
6 V
V
INPUT
35 V
,
L
= 1 mA,
T
J
= +125C
0.2
0.8
%
Load regulation
3)
V
L
100 A
I
L
100 mA
0.2
0.7
%
Load regulation
3)
V
L
5 mA
I
L
250 mA
0.9
1.45
%
Dropout voltage
4)
V
DROPOUT
I
L
= 100 A
40
170
mV
Dropout voltage
4)
V
DROPOUT
I
L
= 100 mA
160
380
5)
mV
Dropout voltage
4)
V
DROPOUT
I
L
= 250 mA
260
650
mV
Dropout supply current
I
SS
V
INPUT
= 4.5 V, I
L
= 100 A,
R
EXT
= 100 k
, O/Ps 1 M
to
V
OUTPUT
, I/Ps at V
OUTPUT
1.2
1.8
mA
Current limit
I
Lmax
OUTPUT tied to V
SS
450
mA
OUTPUT noise, 10 Hz to 100 kHz
V
NOISE
200
V rms
4.5
V
OUTPUT
5.5 V, I
L
= 100 A. C
L
= 10 F + 100 nF, C
INPUT
= 22 F, T
J
= -40 to +125C, un less oth er wise spec i fied
RES and EN
Output Low Voltage
V
OL
V
OUTPUT
= 4.5 V, I
OL
= 20 mA
0.4
V
V
OL
V
OUTPUT
= 4.5 V, I
OL
= 8 mA
0.2
0.4
V
V
OL
V
OUTPUT
= 2.0 V, I
OL
= 4 mA
0.2
0.4
V
V
OL
V
OUTPUT
= 1.2 V, I
OL
= 0.5 mA
0.06
0.2
V
EN
Output High Voltage
V
OH
V
OUTPUT
= 4.5 V, I
OH
= -1 mA
3.5
4.1
V
V
OH
V
OUTPUT
= 2.0 V, I
OH
= -100 A
1.8
1.9
V
V
OH
V
OUTPUT
= 1.2 V, I
OH
= -30 A
1.0
1.1
V
TCL and V
IN
TCL Input Low Level
V
IL
V
SS
0.8
V
TCL Input High Level
V
IH
2.0
V
OUTPUT
V
Leakage current TCL input
I
LI
V
SS
V
TCL
V
OUTPUT
0.05
1
A
V
IN
input resistance
R
VIN
100
M
Comparator reference
6) 7)
V
REF
T
J
= +25C
1.474
1.52
1.566
V
V
REF
1.436
1.620
V
V
REF
-40C
T
J
+125C
1.420
1.620
V
Comparator hysteresis
7)
V
HY
2
mV
Ta ble 3
1)
If INPUT is con nected to V
SS
, no re verse cur rent will flow from the OUTPUT to the INPUT, how ever the sup ply cur rent spec i fied
will be sank by the OUTPUT to supply the A6250.
2)
The OUTPUT volt age tem per a ture co ef fi cient is defined as the worst case voltage change divided by the total temperature range.
3)
Reg u la tion is mea sured at con stant junc tion tem per a ture using pulse testing with a low duty cycle. Changes in OUTPUT volt age
due to heating effects are covered in the specification for thermal regulation.
4 )
The drop out volt age is de fined as the INPUT to OUTPUT differential, measured with the input voltage equal to 5.0 V.
5 )
Not tested.
6)
The com para tor and the volt age reg u la tor have sep a rate voltage references (see Block Di a gram Fig. 7).
7)
The com para tor ref er ence is the power-down re set thresh old. The power-on reset threshold equals the com para tor ref er ence
volt age plus the comparator hysteresis (see Fig. 4).
3
4
A6250
Timing Characteristics
V
INPUT
= 6.0 V, I
L
= 100 A, C
L
= 10 F + 100 nF, C
INPUT
= 22 F, T
J
= -40 to +125C, un less oth er wise spec i fied
Parameter
Symbol Test Conditions
Min.
Typ.
Max.
Units
Propagation delays:
TCL to Output Pins
T
DIDO
250
500
ns
V
IN
sensitivity
T
SEN
1
5
20
s
Logic Transition Times on all
Output Pins
T
TR
Load 10 k
, 50 pF
30
100
ns
Power-on Reset delay
T
POR
R
EXT
= 123 k
, 1%
90
100
110
ms
Watchdog Time
T
WD
R
EXT
= 123 k
, 1%
90
100
110
ms
Open Window Percentage
OWP
0.2 T
WD
Closed Window Time
T
CW
0.8 T
WD
T
CW
R
EXT
= 123 k
, 1%
72
80
88
ms
Open Window Time
T
OW
0.4 T
WD
T
OW
R
EXT
= 123 k
, 1%
36
40
44
ms
Watchdog Reset Pulse
T
WDR
T
WD
/ 40
T
WDR
R
EXT
= 123 k
, 1%
2.5
ms
T
CL
Input Pulse Width
T
TCL
150
ns
Ta ble 4
Timing Waveforms
Watchdog Timeout Period
Voltage Monitoring
Fig. 3
Fig. 4
Con di tion:
R
EXT
= 123 k
5
A6250
Timer Reaction
Combined Voltage and Timer Reaction
Block Diagram
Fig. 5
Fig. 6
Fig. 7
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