EM4056
Copyright
2005, EM Microelectronic-Marin SA
1
www.emmicroelectronic.com
2KBIT Read/Write with ANTICOLLISION
Contactless Identification Device
Description
The EM4056 is a CMOS integrated circuit intended for
use in contactless Read/Write transponders.
The user's configurable 2 kbits EEPROM memory
contained in the chip is organised in 125 words of 16 bits,
each word can be irreversibly protected against reading
or/and writing attempts.
The user can define a password and protect part or all of
the memory.
Serial and identification numbers are laser programmed
during IC manufacturing. A reserved application
numbering may be made available and customer specific
on request.
The EM4056 transmits its data towards the reader by
amplitude modulation of the magnetic field and receives
the commands from the reader in a similar way.
Simple set of commands allow the dialogue between the
EM4056 and the reader. Read and write commands
access directly to an address of memory.
The EM4056 has a built-in anticollision protocol which
allows an unlimited number of transponders in the reader
field to dialogue simultaneously.
The transmission antenna is the only external element
required, all the other elements are integrated on chip.
Features
2 kBits EEPROM organized in 125 words of 16 bits
3 words of 16 Bits Laser ROM for application number
and serial number
Programmable (OTP) Read and/or Write Protection
on every word
Programmable PIN coverage of the memory (0, 25,
50, 75 or 100 %)
Power check for EEPROM Write operation
Reader Talk First communication protocol
Data transmission performed by Amplitude
Modulation (ASK) and Biphase (CDP) coding
Data rate 2 KBauds (Bit Period = 64 periods of carrier
frequency)
100 to 150kHz carrier frequency
Long range Read/Write operations
Block check of data transmission (CRC)
Anticollision protocol based on unique ID
number(unlimited number of tags)
PIN Code identification linked with counter of false
attempts
On chip arithmetic operation (addition, comparison of
secret and non secret data, etc.)
340pF
3% on chip Resonant Capacitor
No external supply buffer capacitance
On chip Rectifier and Voltage Limiter
Applications
Ticketing
Hands free Access control
Prothesis
identification
Prepayment
devices
Manufacturing automation with portable database
Industrial
logistics
Typical Operating Configuration
C2
EM4056
L
Typical value for inductance L is 4.78mH at f
O
= 125 KHz
C1
Fig. 1
EM MICROELECTRONIC -
MARIN SA
EM4056
Copyright
2005, EM Microelectronic-Marin SA
2
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Block Diagram
Analog
Circuit
Safety
(incl. PIN Code)
Adder
Anticollision
Logic Circuit
Modulator
Demodulator
Serial Input
Serial Output
CLK
Antenna
(Coil)
EEPROM
Power Supply
Addressing
Laser ROM
3x16 bit
Memory
Write/Read
Protection (OTP)
125 x 16 bit
EEPROM
125kHz EM
coupling
Fig. 2
System Principle
Reader
125kHz EM coupling
Demodulator
Oscillator
Decoder
Command Mode
Reader Coil
Transponder Coil
Answer Mode
Transponder Coil
Reader Coil
Reader
Coil
Reader
Modulator
Serial
Interface
RS232
EM4056
Fig. 3
EM4056
Copyright
2005, EM Microelectronic-Marin SA
3
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Absolute Maximum Ratings
Parameter Symbol
Min.
Max.
Units
Voltage on Power
Supply pads
VDD -0.3 6.0 V
Voltage on other pads
VPAD
VSS - 0.3 VDD+ 0.3
V
Max. AC peak current
induced on COIL1 and
COIL2
ICOIL
- 30
+ 30
mAp
Storage temperature
TSTORE -55 +125 oC
Operating temperature
TOP -40 +85
oC
Electrostatic discharge
max. to MIL-STS-883C
method 3015
VESD 1000
V
Stresses above these listed maximum ratings may cause
permanent damages to the device. Exposure beyond
specified operating conditions may affect device reliability
or cause malfunction.
Handling Procedures
This device has built-in protection against high static
voltages or electric fields; however, anti-static precautions
must be taken as for any other CMOS component. Unless
otherwise specified, proper operation can only occur when
all terminal voltages are kept within the voltage range.
Unused inputs must always be tied to a defined logic
voltage level.
Operating Conditions
Parameter Symbol
Min
Max
Units
Max. AC Voltage on COIL
VCOIL
(Note
1)
Vpp
Max. AC coil current
ICOIL
-10 +10 mAp
Carrier frequency
fCOIL
100 150 kHz
Operating temperature
TOP
-40 +85 C
Note 1: Defined by forcing 10mA on Coil1-Coil2
Electrical Characteristics
Unless otherwise specified : VDD = 4.0 V, VSS = 0 V, TOP = 25C, VCOIL = 4.5 Vpp, fCOIL = 125 KHz Sine wave
Parameter Symbol
Conditions
Min
Typ
Max
Unit
Supply voltage (not regulated)
VPOS-REG
(Note1)
V
Supply voltage (regulated)
V
DD
VPOS-REG
= max
(note 1)
3.4 4.3 V
Min. EEPROM Read voltage
V
RD
Read mode
(note 2)
2.5
V
Min. EEPROM Write voltage
V
WR
Write mode
2.5
V
EEPROM Read current
I
RD
Read mode
19
25
A
EEPROM Write current
I
WR
Write mode
60
80
A
Power check EEPROM write
current
I
PWCHK
VDD = 4.0 V
70
95
A
EEPROM pwr check threshold
voltage
V
PWCHK
2.52
2.75
3.10
V
EEPROM data endurance
N
CY
Erase all / Write all
105
cycle
EEPROM retention
(note 3)
T
RET
T
OP
= 55
oC after 105 cycles
10 year
Voltage drop V
COIL
- V
SS
on
modulator
V
ON
I
COIL
= 100
A
I
COIL
= 5 mA
0.50
2.50
V
V
Resonance capacitor
C
COIL
330
340
350
pF
POR voltage (high)
V
PRH
V
DD
rising
2.0 2.6 V
MONOFLOP delay
T
MONO
25
50
85
s
Min. voltage of clock extractor 1
(note 4)
V
CLK1min
V
coil1-coil2 (min for extraction)
4.5
Vpp
Min. voltage of clock extractor 2
(note 5)
V
CLK2min
V
coil1-coil2 (min for extraction)
1.0
Vpp
Note 1: Max. supply voltage (not regulated) is defined by forcing a DC current 10 mAp in pins COIL1-COIL2
Note 2: The circuit is not functional under low level POR voltage
Note 4: Uplink
Note 3: Based on 1000 hours measurement at 150oC
Note 5: downlink
EM4056
Copyright
2005, EM Microelectronic-Marin SA
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Timing Characteristics
Parameter Symbol
Conditions
Typ
Units
Modulation duration
ON OFF ON
Tb0
Bit 0
26 8
Emission Bit Period
Tb1
Bit 1
36 8
RF periods
Tab
Start bit
8 16 8
Reception Bit Period
Tbit
64
RF periods
Reception Bit Period Arbitration
Tbitarb
32
RF periods
Select processing time
Tsp
190
RF periods
Read processing time
Trp
126
RF periods
Write processing time
Twp
3134
RF periods
Arb1 processing time
Ta1p
62
RF periods
Arb2 processing time
Ta2p
10
RF periods
Arbitration format duration
Tarb
115
Read Rom format duration
Tro
24.5
Select format duration
Ts
19.1
Prot format duration
Tp
32.2
Read format duration
Tr
20.3
Write format duration
Tw
36.6
Comp format duration
Tc
16.6
Login format duration
Tl
35.1
ms
EEPROM Write duration
T
ee
V
DD
= 3V
20.0
Functional Description
General
The EM4056 has a read enable bit (RdEn) realised with a flip-flop cell. If the RdEn bit is set to 0 , the transponder is
always allowed to answer otherwise it answers only on special commands.
At power on, the default value of the RdEn bit is 0. Therefore, after switching the field on, the RdEn bit of all known tags may
be set by the reader in order to separate them in two groups.
The block check sequence uses a 8 bits CRC which is the same polynom for all CRC blocks.
In addition, the CRC block from the EM4056 to the reader is sent in the format of the BitVal frame (see arbitration mode) to
increase the error detection rate in the reader.
Memory organisation
Address Bit
Bit 0 is defined as the first bit output
Bit
17
1
0
0000000
LASER ROM (3 * 18)
0000010
EEPROM (123 * 18)
W
r
ite Prot
Read Prot
1111110
Configuration
Word
1111111
PIN
Word
Config Word definition + Laser Rom area definition
Fig.4
The Read Protected and the Write Protected bit are OTP bit. Once written to one,
it is definitively locked. No possibility to erase them to zero.
EM4056
Copyright
2005, EM Microelectronic-Marin SA
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ROM organisation
Address
Datas
Wp
Rp
bit17
bit2
bit1
bit0
0000000
B15
B0
1
0
0000001
B31
B16
1
0
0000010
L7
L0 C7
C0
1
0
B31-B0 unique code number.
L7-L0
8-bit customer ID, standard version = 65hex, 101dec.
C7 C0
CRC calculated on bits B31 to B0 and L7 to L0.
(CRC block diagram see figure 4).
Note : EM4056 with different customer ID will also have a different unique code number.
Commands structure
Command
Code
ReadRom
MSB 0010 LSB
SelToggle 0100
SelTag 0101
DeselTag 0110
Prot 1000
Read 1010
Write 1100
Add 1101
Comp 1110
Start Arbitration
0001
Continue if "0"
00
Continue if "1"
11
Abort Arbitration
01 or 10
CRC Block Diagram
7
6 5
4
3 2 1
0
Data Input
LSB
X0=1
X1
X4
X5
X7
MSB
X
Exclusive OR
Shift Register
CRC Generating polynomial = X7+X5+X4+X+1
Fig. 5
In uplink the CRC is calculated on all bits of the command (startbit excluded), MSB first.
In dowlink the CRC is calculated on all bits of the answer, first bit sent by the chip first.
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