EM6125
Copyright
2001, EM Microelectronic-Marin SA
1
www.emmicroelectronic.com
Digitally programmable 65 and 81 multiplex rate LCD
Controller and Driver
Features
Slim IC for COG, COF and COB technologies
I
2
C & Serial bus interface
Internal display data RAM
2 digitally programmable multiplex rates :
-
81 rows x 102 columns
-
65 rows x 118 columns
LCD supply voltage internally generated and digitally
programmable from 3V to 11V
Low operating current consumption: 120
A (typ)
No external components needed except one V
LCD
capacitor
On chip
-
4 intermediate bias voltages generation
-
Oscillator for LCD refresh (no external components
required)
High noise immunity on inputs
Row and column drivers mirroring for COG or COF
connections flexibility
Partial display mode with 17 active rows for current
consumption reduction
Sleep mode for a nearly null current consumption
Wide V
DD
supply voltage from 1.8V to 5V.
Wide temperature range: -40C to +85C
Description
The EM6125 is a bit map controller and driver for full dot
matrix monochrome STN LCD displays. The driving
capability is 81 rows x 102 columns (10 rows of
characters + one row of icons) or 65 rows x 118 columns
(8 rows of characters + one row of icons). There is a one
to one relation between LCD pixels and bits of the
Display Data RAM.
The EM6125 is extremely low power consumption LCD
controller and driver product. The typical current
consumption is about 120
A with no external component
except the capacitor connected to V
LCD
. One important
feature on EM6125 is the partial display mode, which
enables important current consumption reduction. With
this function selected, only 17 rows remain active,
needed V
LCD
decreases and the commutation
frequencies of row and column drivers are also
decreased. These three effects of partial display mode
reduce drastically current consumption.
Typical Applications
Mobile phones
Smart cards
Automotive displays
Portable, battery operated products
Balances and scales, utility meters
Typical Operating Configuration
V
LCD
SCL SDA RES Vss1 Vss2 V
DD1
V
DD2
V
HV
EM6125
102 columns outputs
41 row drivers
40 row drivers
Figure 1
Pin Configuration
Figure 2
EM MICROELECTRONIC
- MARIN SA
EM6125
Copyright
2001, EM Microelectronic-Marin SA
2
www.emmicroelectronic.com
Features
1
Description
1
Typical Applications
1
Typical Operating Configuration
1
Pin Configuration
1
1 Absolute Maximum Ratings
4
2 Handling Procedures
4
3 Operating Conditions
4
4 Electrical Characteristics
4
5 Timing Characteristics
5
5.1 Timing Waveforms
7
6 Block diagram
9
7 Pin description
10
8 Functional description
11
8.1 Selection of interface type
11
8.2 Serial interface
11
8.3 I
2
C interface
13
8.3.1 Start and stop conditions
13
8.3.2 Bit transfer
13
8.3.3 Acknowledge
13
8.4 I
2
C protocol
13
8.4.1 Write mode
13
8.4.2 Read Mode (RW = 1)
14
8.5 Display Data RAM
14
8.5.1 DDRAM description
14
8.5.2 DDRAM addressing
18
8.6 Initialization of EM6125
23
8.7 Description of instructions
24
8.7.1 Initialization 0
24
8.7.1.1 Mux Mode
24
8.7.1.2 TC[1:0]
24
8.7.1.3 Inv. Row
25
8.7.1.4 MX
26
8.7.1.5 Blank
26
8.7.1.6 Checker
26
8.7.1.7 Inv. Video
26
8.7.2 Initialization 1
28
8.7.2.1 X[6:0]
28
8.7.2.2 V
28
8.7.3 Initialization 2
28
8.7.3.1 Y[3:0]
28
8.7.3.2 Vlcd Dischg.
28
8.7.3.3 DEC
28
8.7.3.4 LSB
28
8.7.4 Initialization 3
28
8.7.4.1 Vlcd Level[7:0]
28
8.7.5 Initialization 4
29
8.7.5.1 Mult[1:0]
29
8.7.5.2 Partial Display
29
8.7.5.3 First Row PD[3:0]
29
EM6125
Copyright
2001, EM Microelectronic-Marin SA
3
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8.7.5.4 Sleep
29
8.7.6 Test 0 to 3
29
8.8 LCD outputs
30
8.9 LCD refresh frequency
31
8.10 V
LCD
depending on V
HV
31
8.11 LCD driver waveforms
32
8.11.1 Partial Display
34
9 Typical Application
35
10 Pad location
39
11 Ordering Information
42
12 Updates
43
EM6125
Copyright
2001, EM Microelectronic-Marin SA
4
www.emmicroelectronic.com
1 Absolute Maximum Rating s
Parameter
Symbol
Conditions
Supply voltage range
V
DD1,2
-0.3V to +6V
Supply voltage range
V
HV
-0.3V to +6V
Supply voltage range
V
LCD
V
HV
-0.3V to +12V
All input voltages
V
LOGIC
-0.3V to V
DD1,2
+0.3V
Voltages at S
0
to S
184
V
DISPLAY
-0.3V to V
LCD
+ 0.3V
Storage temperature
range
T
STO
-65C to +150 C
Electrostatic discharge
max. to MIL-STD-883C
method 3015
V
ESD
1000V
Maximum soldering
conditions
T
SMAX
250C
10 s
Stresses above these listed maximum ratings may cause
permanent damage to the device. Exposure beyond
specified electrical characteristics may affect device
reliability or cause malfunction.
2 Handling Procedures
This device has built-in protection against high static
voltages or electric fields; however, anti-static
precautions should be taken as for any other CMOS
components. Unless otherwise specified, proper
operation can only occur when all terminal voltages are
kept within the supply voltage range.
3 Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Operating
temperature
T
A
-40
+85
C
Logic supply
voltage
V
DD1,2
1.8
2.5
5.5
V
High voltage
generator
supply voltage
V
HV
2.4 *
2.5
5.5
V
LCD supply
voltage
V
LCD
3
8
11
V
* Lower V
HV
voltage is possible until the required V
LCD
voltage is reached.
4 Electrical Characteristics
V
SS1,2
= 0V, V
DD1
= V
DD2
= 1.8V, V
HV
= 2.4V, unless otherwise specified. T
A
= -40C to +85 C unless otherwise specified.
Minimum required capacitor: 1
F on V
LCD
, 100nF on V
DD1,2
and V
HV
.
Parameter
Symbol
Test conditions
Min.
Typ.
Max.
Units
Supply Current
Sleep mode
I
DD
Sleep = 1
10
nA
Sleep mode
I
HV
Sleep = 1
0.5
A
Normal LCD refresh mode
I
DD
(note 1)
15
21
A
Normal LCD refresh mode
I
HV
(note 2)
124
180
A
Partial LCD refresh mode
I
HV
(note 3)
50
87
A
Control Input Signals
Input leakage
I
IN
V
i
= V
ss1
or V
DD1
-1
1
A
Input capacitance
C
IN
8
pF
Low level input voltage
V
IL
0.3xV
DD1
V
High level input voltage
V
IH
0.7xV
DD1
V
LCD Outputs
Internally generated LCD
supply voltage
V
LCD
00000000b
3.02
V
V
LCD
10001110b
8.02
V
V
LCD
step between 2
consecutive programmed
V
LCD
Level
V
LCD
step
35.2
mV
V bias tolerance
V bias tol.
(note 5)
-80
80
mV
Note 1: Measured on V
DD1
+ V
DD2
, all outputs open, SDA and SCL at V
SS
, RES at V
DD1
, multiplex rate 81, x5 voltage
multiplier, V
LCD
= 10001110b, DDRAM loaded with checker pattern
Note 2: Measured on V
HV
, same conditions as (note 1).
Note 3: Measured on V
HV
, all outputs open, SDA and SCL at V
SS
, RES at V
DD1
, partial display mode,
2 voltage multiplier,
V
LCD
= 00101011b, DDRAM loaded with checker pattern.
Note 4: With internal voltage multiplier, the maximum V
LCD
voltage depends on V
HV
, programmed voltage multiplier and
display load.
Note 5: V
1
, V
2
, V
3
and V
4
bias levels measured with V
LCD
= 7V, on 1 LCD row driver output and 1 LCD column driver
output, multiplex rate 81, T
A
= 25 C, load =
10
A.
EM6125
Copyright
2001, EM Microelectronic-Marin SA
5
www.emmicroelectronic.com
5 Timing Characteristics
V
SS1,2
= 0V, V
DD1
= V
DD2
= 1.8V, V
HV
= 2.4V, T
A
= -40C to +85 C unless otherwise specified.
Parameter
Symbol
Test conditions
Min.
Typ.
Max.
Units
Internal frame frequency
for LCD refresh
f
FR
(note 1)
75 x
mux
Hz
Minimum reset pulse width
t
RW
70
ns
I2C timing characteristics
SCL frequency
f
I2C
1600
kHz
SCL low period
t
LOW
350
ns
SCL high period
t
HIGH
100
ns
SDA setup time
t
SUDAT
10
ns
SDA hold time
t
HDDAT
20
ns
SCL and SDA rise time
t
R
200
ns
SCL and SDA fall time
t
F
200
ns
Setup time for a repeated
start condition
t
SUSTA
20
ns
Hold time for a
start condition
t
HDSTA
20
ns
Setup time for a
stop condition
t
SUSTO
20
ns
Spike width on SCL and SDA
t
SW
20
ns
Time before a new transmission can start
t
BUF
100
ns
Capacitive bus line load
C
b
400
pF
Serial bus timing characteristics
SCL frequency
f
SER
4
MHz
SCL low period
t
CL
70
ns
SCL high period
t
CH
130
ns
SDA setup time
t
DS
20
ns
SDA hold time
t
DH
50
ns
SCL rise time
t
CR
200
ns
SCL fall time
t
CF
200
ns
CS setup time
t
SUCS
10
ns
CS hold time
t
HDCS
130
ns
Time before a new transmission can
start, CS minimum high time.
t
BUFCS
70
ns
Note 1:
Measured on pad FR.
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