R
EM6625
Copyright
2005, EM Microelectronic-Marin SA
1
www.emmicroelectronic.com
Ultra Low Power Microcontroller with 4x20 LCD Driver
Features
True Low Power
1.6 A active mode, LCD On
0.4 A standby mode, LCD Off
0.2 A sleep mode
@ 3 V, 32 KHz, 25 C
Low Supply Voltage 1.2 V to 3.6 V
Melody, 7 tones + silence inclusive 4-bit timer
Universal 10-bit counter, PWM, event counter
LCD 20 segments, 3 or 4 times multiplexed
Temperature compensated LCD voltage levels
Built-in LCD voltage multipliers
LCD frequency 32 Hz/42.7 Hz/64 Hz
32 KHz or 128 kHz crystal oscillator
72 basic instructions
2 clocks per instruction cycle
Mask ROM 4k x 16 bits
RAM 128 x 4 bits
Max. 12 inputs ; port A, port B, port SP
Max. 8 outputs ; port B, port SP
Voltage Level Detector (VLD), 8 levels software
selectable from 1.2 V up to 4.0 V
Prescaler down to 1 second ( crystal = 32 KHz )
1/1000 sec 12 bit binary coded decimal counter with
hard or software start/stop function
3 wire serial port , 8 bit, master and slave mode
5 external interrupts (port A, serial interface)
8 internal interrupts (3x prescaler, BCD counter
2x10-bit counter, melody timer, serial interface)
timer watchdog and oscillation supervisor
Description
The EM6625 is an ultra-low power, low voltage
microcontroller with an integrated 3/4 MUX x 20
segments LCD driver and the equivalent of 8kB mask
ROM. It features temperature compensated LCD voltage
levels, free LCD segment allocation and built-in voltage
multipliers. It also has a melody generator, a millisecond
counter (BCD) and PWM function. Tools include
windows-based simulator and emulator. A flexible MFP
version is also available for development stage.
Due to its very low current consumption, the EM6625 is
ideal for use in battery-operated and field-powered
applications.
Typical Applications
Household appliance
Timer / sports timing devices
Medical devices
Interactive system with display
Automotive controls with display
Measurement equipment
Bicycle computers
Safety and security devices
Figure 1. Architecture
Core
EM6600
32/128 KHz
Crystal Osc
ROM
4k X 16Bit
RAM
128*4Bit
Power
Supply
VLD 8 Levels
Prescaler
Millisecond
Counter
10-Bit Univ
Count/Timer
Interrupt
Controller
LCD Controller
3, 4 X 20
Serial
Interface
Port B
Port A
Power on
Reset
Watchdog
Melody
Generator
Voltage
Multiplier
0
2
1
3
0
2
1
3
V
DD
PWM
PWM
Figure 2. Pin Configuration, TQFP52
EM6625
TQFP52
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
39
38
37
36
35
34
33
32
31
30
29
28
27
52
51
50
49
48
47
46
45
44
43
42
41
40
VL1
VL2
VL3
COM[1]
COM[2]
COM[3]
COM[4]
SEG[20]
SEG[19]
SEG[18]
SEG[17]
SEG[16]
SEG[15]
PA[1]
PA[0]
PB[3]
PB[2]
PB[1]
PB[0]
PS[3]
PS[2]
PS[1]
PS[0]
TEST
RESET
SEG[1]
SEG
[
1
4
]
SEG
[
1
3
]
SEG
[
1
2
]
SEG
[
1
1
]
SEG
[
1
0
]
SEG
[
9
]
SEG
[
8
]
SEG
[
7
]
SEG
[
6
]
SEG
[
5
]
SEG
[
4
]
SEG
[
3
]
SEG
[
2
]
C1
A
C1
B
C2
A
C2
B
VS
S
QO
UT
QI
N
VR
EG
VB
AT
ST
R
O
BE
BUZ
Z
ER
PA
[
3
]
PA
[
2
]
EM MICROELECTRONIC -
MARIN SA
R
EM6625
Copyright
2005, EM Microelectronic-Marin SA
2
www.emmicroelectronic.com
EM6625 at a glance
Power Supply
- Low voltage low power architecture including internal
voltage regulator
- 1.2 V to 3.6 V battery voltage
- 1.6 A in active mode (Xtal, LCD on, 25
C)
- 0.4 A in standby mode (Xtal, LCD off, 25
C)
- 0.2 A in sleep mode (25
C)
- 32 KHz/128 kHz Oscillator (metal option)
RAM
- 64 x 4 bit, direct addressable
-
64 x 4 bit, indexed addressable
ROM
- 4k x 16 bit (~8k Byte), metal mask programmable
CPU
- 4-bit RISC architecture
- 2 clock cycles per instruction
- 72 basic instructions
Main Operating Modes and Resets
- Active mode (CPU is running)
- Standby mode (CPU in halt)
- Sleep mode (no clock, reset state)
- Initial reset on power on (POR)
- Watchdog reset (logic and oscillation watchdogs)
- Reset terminal
- Reset with input combination on port A (register
selectable)
Prescaler
- 15 stage system clock divider down to 1Hz
- 3 Interrupt requests; 1Hz, 32Hz or 8Hz, Blink
- Prescaler reset (4kHz to 1Hz)
Liquid Crystal Display Driver (LCD)
- 20 Segments 3 or 4 times multiplexed
- Internal or external voltage multiplier
- Free Segment allocation architecture (metal option)
- LCD switch off for power save
- LCD frequency 32 Hz/42.7 Hz/64 Hz
8-Bit Serial Interface
- 3 wire (Clock, DataIn , DataOut) master/slave mode
- READY output during data transfer
- Maximum shift clock is equal to the main system clock
- Interrupt request to the CPU after 8 bits data transfer
- Supports different serial formats
- Can be configured as a parallel 4 bit input/output port
- Direct input read on the port terminals
- All outputs can be put tristate (default)
- Selectable pull-downs in input mode
- CMOS or
Nch.
open drain outputs
- Weak pull-up selectable in Nch.
open drain mode
4-Bit Input Port A
- Direct input read on the port terminals
- Debouncer function available on all inputs
- Interrupt request on positive or negative edge
- Pull-up or pull-down or none selectable by register
- Test variables (software) for conditional jumps
- PA[0] and PA[3] are inputs for the event counter
- PA[3] is Start/Stop input for the millisecond counter
- Reset with input combination (register selectable)
4-Bit Bi-directional Port B
- All different functions bit-wise selectable
- Direct input read on the port terminals
- Data output latches
- CMOS or Nch. open drain outputs
- Pull-down or pull-up selectable
- Weak pull-up in Nch. open drain mode
- Selectable PWM, 32kHz, 1kHz and 1Hz output
Melody Generator
- Dedicated Buzzer terminal
- 7 tones plus silence output
- The output can be put tristate (default)
- Internal 4-bit timer, usable also in standalone mode
- 4 different timer input clocks
- Timer with automatic reload or single run
- Timer interrupt request when reaching 0
Voltage Level Detector (SVLD)
- 8 different levels from 1.2 V to 4.0 V.
- Busy flag during measure
10-Bit Universal Counter
- 10, 8, 6 or 4 bit up/down counting
- Parallel load
- Event counting (PA[0] or PA[3])
- 8 different input clocks-
- Full 10 bit or limited (8, 6, 4 bit)
compare function
- 2 interrupt requests (on compare and on 0)
- Hi-frequency input on PA[3] and PA[0]
- Pulse width modulation (PWM) output
Millisecond Counter
- 3 digits binary coded decimal counter (12 bits)
- PA[3] input signal pulse width and period measurement
- Internal 1000 Hz clock generation
- Hardware or software controlled start stop mode
- Interrupt request on either 1/10 Sec or 1Sec
Interrupt Controller
- 5 external and 8 internal interrupt request sources
- Each interrupt request can individually be masked
- Each interrupt flag can individually be reset
- Automatic reset of each interrupt request after read
- General interrupt request to CPU can be disabled
- Automatic enabling of general interrupt request flag
when going into HALT mode.
R
EM6625
Copyright
2005, EM Microelectronic-Marin SA
3
www.emmicroelectronic.com
Table of Contents
FEATURES __________________________________1
DESCRIPTION _______________________________1
TYPICAL APPLICATIONS _______________________1
EM6625 AT A GLANCE _________________________2
1. PIN DESCRIPTION FOR EM6625 _____________4
2. OPERATING
MODES ______________________6
2.1 A
CTIVE
M
ODE
__________________________6
2.2 S
TANDBY
M
ODE
________________________6
2.3 S
LEEP
M
ODE
__________________________6
3. POWER
SUPPLY__________________________7
4. RESET __________________________________8
4.1 O
SCILLATION
D
ETECTION
C
IRCUIT
___________9
4.2 R
ESET
T
ERMINAL
_______________________9
4.3 I
NPUT
P
ORT
A
R
ESET
F
UNCTION
____________9
4.4 D
IGITAL
W
ATCHDOG
T
IMER
R
ESET
__________10
4.5 CPU
S
TATE AFTER
R
ESET
________________10
5. OSCILLATOR AND PRESCALER____________11
5.1 O
SCILLATOR
__________________________11
5.2 P
RESCALER
__________________________11
6. INPUT AND OUTPUT PORTS _______________12
6.1 P
ORTS
O
VERVIEW
______________________12
6.2 P
ORT
A _____________________________13
6.2.1
IRQ on Port A ____________________13
6.2.2
Pull-up or Pull-down _______________14
6.2.3
Software Test Variables ____________14
6.2.4
Port A for 10-Bit Counter and MSC ___14
6.3 P
ORT
A
R
EGISTERS
_____________________14
6.4 P
ORT
B _____________________________16
6.4.1
Input / Output Mode _______________16
6.4.2
Pull-up or Pull-down _______________17
6.4.3
CMOS / NCH. Open Drain Output ____17
6.4.4
PWM and Frequency Output ________18
6.5 P
ORT
B
R
EGISTERS
_____________________18
6.6 P
ORT
S
ERIAL
_________________________19
6.6.1
4-bit Parallel I/O __________________19
6.6.2
Pull-up or Pull-down _______________20
6.6.3
Nch. Open Drain Outputs ___________21
6.6.4
General Functional Description ______21
6.6.5
Detailed Functional Description ______22
6.6.6 Output
Modes ____________________22
6.6.7
Reset and Sleep on Port SP_________23
6.7 S
ERIAL
I
NTERFACE
R
EGISTERS
_____________24
7. MELODY,
BUZZER _______________________26
7.1 4-B
IT
T
IMER
__________________________26
7.1.1
Single Run Mode _________________27
7.1.2
Continuos Run Mode ______________27
7.2 P
ROGRAMMING
O
RDER
__________________28
7.3 M
ELODY
R
EGISTERS
____________________28
8. 10-BIT
COUNTER ________________________30
8.1 F
ULL AND
L
IMITED
B
IT
C
OUNTING
___________30
8.2 F
REQUENCY
S
ELECT AND
U
P
/D
OWN
C
OUNTING
_31
8.3 E
VENT
C
OUNTING
______________________32
8.4 C
OMPARE
F
UNCTION
____________________32
8.5 P
ULSE
W
IDTH
M
ODULATION
(PWM) _________32
8.5.1
How the PWM Generator works. _____33
8.5.2 PWM
Characteristics ______________33
8.6 C
OUNTER
S
ETUP
_______________________34
8.7 10-
BIT
C
OUNTER
R
EGISTERS
______________ 34
9. MILLISECOND
COUNTER _________________ 36
9.1 PA[3]
I
NPUT FOR
MSC __________________ 36
9.2 IRQ
FROM
MSC _______________________ 36
9.3 MSC-M
ODES
_________________________ 37
9.4 M
ODE SELECTION
______________________ 37
9.5 M
ILLISECOND
C
OUNTER
R
EGISTERS
_________ 39
10. INTERRUPT
CONTROLLER______________ 40
10.1 I
NTERRUPT
C
ONTROL
R
EGISTERS
___________ 41
11.
SUPPLY VOLTAGE LEVEL DETECTOR ____ 42
11.1 SVLD
R
EGISTER
______________________ 42
12. STROBE
OUTPUT______________________ 43
12.1 S
TROBE
R
EGISTER
_____________________ 43
13. RAM _________________________________ 44
14. LCD
DRIVER __________________________ 45
14.1 LCD
C
ONTROL
________________________ 46
14.2 LCD
A
DDRESSING
______________________ 46
14.3 F
REE
S
EGMENT
A
LLOCATION
______________ 47
14.4 LCD
R
EGISTERS
_______________________ 47
15.
PERIPHERAL MEMORY MAP ____________ 49
16.
OPTION REGISTER MEMORY MAP _______ 53
17.
ACTIVE SUPPLY CURRENT TEST ________ 54
18. MASK
OPTIONS _______________________ 55
18.1 I
NPUT
/
O
UTPUT
P
ORTS
__________________ 55
18.1.1
Port A Metal Options ______________ 55
18.1.2
Port A Metal Options ______________ 55
18.1.3
Port B Metal Options ______________ 56
18.1.4
Port SP Metal Options _____________ 57
18.1.5
Voltage Regulator Option ___________ 58
18.1.6
Debouncer Frequency Option _______ 58
18.1.7
Frequency Selection Option _________ 58
18.1.8
LCD Frame Frequency Option _______ 58
18.1.9
User defined LCD Segment Allocation 59
19.
TEMP. AND VOLTAGE BEHAVIORS _______ 60
19.1 IDD
C
URRENT
(T
YPICAL
) _________________ 60
19.2 IDD
C
URRENT
@
128
K
HZ _______________ 60
19.3 P
ULL
-
DOWN
R
ESISTANCE
(T
YPICAL
) _________ 61
19.4 P
ULL
-
UP
R
ESISTANCE
(T
YPICAL
) ___________ 62
19.5 O
UTPUT
C
URRENTS
(T
YPICAL
) _____________ 62
20. ELECTRICAL
SPECIFICATION ___________ 63
20.1 A
BSOLUTE
M
AXIMUM
R
ATINGS
_____________ 63
20.2 H
ANDLING
P
ROCEDURES
_________________ 63
20.3 S
TANDARD
O
PERATING
C
ONDITIONS
_________ 63
20.4 DC
C
HARACTERISTICS
-
P
OWER
S
UPPLY
_____ 63
20.5 S
UPPLY
V
OLTAGE
L
EVEL
D
ETECTOR
_________ 64
20.6 O
SCILLATOR
__________________________ 64
20.7 DC
CHARACTERISTICS
-
I/O
P
INS
___________ 65
20.8 LCD
SEG[20:1]
O
UTPUTS
_______________ 66
20.9 LCD
C
OM
[4:1]
O
UTPUTS
_________________ 66
20.10 DC
O
UTPUT
C
OMPONENT
______________ 66
20.11 LCD
V
OLTAGE
M
ULTIPLIER
_____________ 66
21.
DIE, PAD LOCATION AND SIZE___________ 67
22.
PACKAGE & ORDERING INFORMATION ___ 68
22.1 O
RDERING
I
NFORMATION
_________________ 69
22.2 P
ACKAGE
M
ARKING
_____________________ 69
22.3 C
USTOMER
M
ARKING
___________________ 69
R
EM6625
Copyright
2005, EM Microelectronic-Marin SA
4
www.emmicroelectronic.com
1. Pin Description for EM6625
Chip
TQFP
52
DIL
64
Signal Name
Function
Remarks
1
1
10
VL1
Voltage multiplier level 1
LCD level 1 input, if external
supply selected
2
2
11
VL2
Voltage multiplier level 2
LCD level 2 input, if external
supply selected
3
3
12
VL3
Voltage multiplier level 3
LCD level 3 input, if external
supply selected
4
4
13
COM[1]
LCD back plane 1
5
5
14
COM[2]
LCD back plane 2
6
6
15
COM[3]
LCD back plane 3
7
7
16
COM[4]
LCD back plane 4
Not used if 3 times multiplexed
8
8
18
SEG[20]
LCD Segment 20
9
9
19
SEG[19]
LCD Segment 19
10
10
20
SEG[18]
LCD Segment 18
11
11
21
SEG[17]
LCD Segment 17
12
12
22
SEG[16]
LCD Segment 16
13
13
23
SEG[15]
LCD Segment 15
14
14
26
SEG[14]
LCD Segment 14
15
15
27
SEG[13]
LCD Segment 13
16
16
28
SEG[12]
LCD Segment 12
17
17
29
SEG[11]
LCD Segment 11
18
18
30
SEG[10]
LCD Segment 10
19
19
31
SEG[9]
LCD Segment 9
20
20
33
SEG[8]
LCD Segment 8
21
21
34
SEG[7]
LCD Segment 7
22
22
35
SEG[6]
LCD Segment 6
23
23
36
SEG[5]
LCD Segment 5
24
24
37
SEG[4]
LCD Segment 4
25
25
38
SEG[3]
LCD Segment 3
26
26
39
SEG[2]
LCD Segment 2
27
27
42
SEG[1]
LCD Segment 1
28
28
43
Reset
Input reset terminal,
internal pull-down 15 KOhm
Main reset
29
29
44
Test
Input test terminal,
internal pull-down 15 KOhm
For EM tests only, ground 0 !
Except when needed for MFP
programming
30
30
45
PSP[0]
Input/output , open drain
serial port : SIN
parallel out terminal 0
Serial interface data in
or
parallel data[0] in/out
31
31
46
PSP[1]
Output , open drain
serial port : Ready/CS
parallel out terminal 1
Serial interface Ready CS
or
parallel data[1] in/out
32
32
47
PSP[2]
Output , open drain
serial port : SOUT
parallel out terminal 2
Serial interface data out
or
parallel data[2] in/out
33
33
49
PSP[3]
Input/output , open drain
serial port : SCLK
parallel out terminal 3
Serial interface clock I/O
or
parallel data[3] in/out
34
34
50
PB[0]
Input/output, open drain
port B terminal 0
Port B data[0] I/O or
Ck[1] output
R
EM6625
Copyright
2005, EM Microelectronic-Marin SA
5
www.emmicroelectronic.com
Chip
TQFP
52
DIL
64
Signal Name
Function
Remarks
35
35
51
PB[1]
Input/output, open drain
port B terminal 1
Port B data[1] I/O or
Ck[11] output
36
36
52
PB[2]
Input/output, open drain
port B terminal 2
Port B data[2] I/O or
Ck[16] output
37
37
53
PB[3]
Input/output, open drain
port B terminal 3
Port B data[3] I/O or
PWM output
38
38
54
PA[0]
Input port A terminal 0
TestVar 1
Event counter
39
39
55
PA[1]
Input port A terminal 1
TestVar 2
40
40
58
PA[2]
Input port A terminal 2
TestVar 3
41
41
59
PA[3]
Input port A terminal 3
Event counter,
MSC start/stop control
42
42
60
Buzzer
Output Buzzer terminal
43
43
61
Strobe
Output Strobe terminal
P reset state or/and port B
write or sleep flag out
44
44
62
Vbat = V
DD
Positive power supply
MFP Connection
45
45
63
Vreg
Internal voltage regulator
Connect to minimum 100nF,
MFP connection
46
46
64
Qin/Osc1
Crystal terminal 1
32 or 128KHz crystal, MFP
connection
47
47
2
Qout /Osc2
Crystal terminal 2
32 or 128KHz crystal, MFP
connection
48 48 3
V
SS
Negative power supply
ref. terminal, MFP connection
49
49
4
C2B
Voltage multiplier
Not needed if ext. supply
50
50
5
C2A
Voltage multiplier
Not needed if ext. supply
51
51
6
C1B
Voltage multiplier
Not needed if ext. supply
52
52
7
C1A
Voltage multiplier
Not needed if ext. supply
Gray shaded areas : Terminals needed for MFP programming connections (V
DD
, Vreg, Qin, Qout, Test).
Figure 3. Typical Configuration
C rystal
L C D D isp la y
C 1
C 1
C 1
C 4
C 3
V re g
V
S S
T e st
R e set
V
D D
(V b a t)
S E G [20 :1 ]
Q in O o ut
C 2
C 2
C 1A
C 1B
C 2A
C 2B
C O M [4:1 ]
V L1
V L2
V L3
E M 6 6 2 5
A ll C apacitors 100n F
P o rt A
S tro b e
B u zze r
P ort B
P ort S P
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