EM6635
03/03 REV. B
Copyright
2002, EM Microelectronic-Marin SA
1
www.emmicroelectronic.com
Low Power Microcontroller with RC and 32kHz oscillators
and 9 high drive outputs
Features
32'768Hz crystal oscillator
500kHz RC Oscillator (no external component)
External clock (metal option)
9 High drive outputs: up to 20mA
Melody generator with 255 programmable
frequencies
True Low Power: 1.5uA active mode
0.4uA halt mode
@ 1.55V, 32kHz, 25C
Low Supply Voltage 1.2V to 3.6V
Max. 14 Inputs with selectable debouncers; Port P1,
P2, P6, P70, P71
Max. 15 outputs (9 I/O High drive outputs); Port P3,
P4, P6, P70, P71, P72
Mask ROM 4096 x 16bits
RAM 256 x 4bits
2 clocks per instruction cycle
72 basic instructions
2 outputs; Reset OUT, Buzzer OUT
2 timers 8bits
2 x 4 bits BCD counters
Event counter 3bits
Prescaler down to 1Hz (crystal =32kHz), readable by
CPU in 2 ranges
Serial Port as selectable configuration of Port 5
18 Interrupts: 12 internal, 6 external
Voltage Level Detector, 3 levels software selectab
le
Die form and MLF2, 40 pin (Micro Lead Frame)
package
Description
The EM6635 is a low voltage, low power microcontroller
containing 9 integrated high-drive outputs able to provide
up to 20mA. It is ideal for use in applications in which one
must drive devices such as motor drivers, small stepping
motors, LEDs, triacs, external EEPROM or other ICs in
the system.
EM6635 has both a 32kHz crystal oscillator and a
500kHz RC oscillator without external component, as well
as an external clock to be driven up to 4MHz.
The CPU operating clock can be switched from crystal to
RC oscillator for high-speed operation.
It has a frequency/melody generator with 255
programmable frequencies for quality buzzer.
The EM6635 contains the equivalent of 8kB mask ROM
and the RAM has a capacity of 256x4 bits.
It also has a power-on reset, watchdog timer, 2 timers
8bits, 2 BCD counters, 3bits event counter, 4 wire serial
port 8bits and several clock functions.
Figure 1. Architecture
Crystal
Oscillator
32kHz
RC Oscillator
500kHz
External
clock
R A M
256 x 4Bits
R O M
4096 x 16Bits
Power Supply
Voltage reg.
Watch Dog
timer
Frequency
Generator
B C D
Counter
Timer 1
Timer 2
Core
EM6600
VLD 3levels
Frequency
Doubler
or
Interrupt
Controller
Reset
Logic
Port 6
0 1 2 3
Port 1
0 1 2 3
Port 7
0 1 2 3
Port 5
0 1 2 3
Port 4
0 1 2 3
Port 3
0 1 2 3
Port 2
0 1 2 3
Serial or
parallel port
2 : High Drive Output
3 : Buzzer out
High Drive Output
Figure 2. Typical application
Stepping Motors
P72
P3
P4
P5
V
P1
P2
SIO
VSS
VRR
QOUT
BZ
P6
P70,P71
Reset Out
EM6635
PI E Z O
32kHz Xtal
BAT
+V
BAT
C
VRR
CENV
QIN
Reset IN
+V
BAT
Applications
Watch & clock
Timer / sports timing devices
Security / industrial
Toys
Sensor interface
EM MICROELECTRONIC
- MARIN SA
EM6635
03/03 REV.B
Copyright
2002, EM Microelectronic-Marin SA
2
www.emmicroelectronic.com
EM6635 at a glance
Power Supply
- Low voltage low power architecture
- including internal voltage regulator
- 1.2 to 3.6 V battery voltage
- 1.5A in active mode (Xtal, 25
C)
- 0.4 A in HALT mode (Xtal, 25
C)
- 32'768Hz Crystal Oscillator
- 500kHz RC oscillator (no external component)
- External clock (metal option)
RAM
- 4 pages of 64 x 4bits, page 0 is direct addressable
ROM
- 4096 x 16bits, metal mask programmable
CPU
- 4-bits RISC architecture
- 2 clock cycles per instruction (CPI=2)
- 72 basic instructions
- operating frequency selectable by SW
Main Operating Modes and Resets
- Active mode, CPU is running
- Halt mode, CPU in halt, peripheral are running
- Initial reset on power on (POR)
- Watchdog reset (logic)
- Reset terminal with Schmitt Trigger
- Reset with input combination on Port P1 & Port P2
(register selectable)
Prescaler
- 15 stage system clock divider from 32kHz down to 1Hz
- 4 Interrupt requests; 128Hz, 64Hz, 32Hz and 1Hz or
64Hz, 16Hz, 8Hz and 1Hz
- Prescaler state readable to CPU from 128Hz to 16Hz
and from 8Hz to 1Hz
- Prescaler reset (32Hz to 1Hz)
8bit Serial Interface at Port 5
- 4 wire (serial clock In/Out, serial output, serial status
In/Out (RDY), serial input)
- Master mode: 32kHz, 16kHz or 4kHz serial clock
- Slave mode: external clock from P33
- Selectable word length: 8 - 7 - 6 - 5 bit
- Selectable synchronized or direct output
- Selectable positive or negative active clock edge by
direct or inverted serial clock SCK
- Special ready output mode when port is in master mode
- RDY can be set by SW
Frequency Generator with 255 output frequencies
- 8bit programmable frequency divider
- 50% duty cycle output signal
- Clock frequency is 65536Hz (doubled 32768Hz)
- SW activated
Watchdog Timer
- Creates watchdog reset after time-out
- Can be disabled by SW and mask option
Interrupt Controller
- 12 internal, 6 external interrupt request sources
- Individually maskable, individually resettable
- Global interrupts disable,with auto-enable at HALT mode
Voltage Level Detector (SVLD)
- 3 software selectable levels
- Busy flag during measure
- Active only on request during measurement to reduce
power consumption
Timer 1
- 8bits timer with 3 modes: Zero Stop, Synchron Mode
and Auto Reload Mode
- Timer clock selectable 4kHz-2kHz-1kHz-512Hz by SW
- Zero Stop: Timer starts counting down when loaded from
CPU with data (> 0). When at zero, an interrupt is
generated.
- Synchron Mode: After loading by CPU, timer starts
synchronized by the positive edge of the prescaler 64Hz
signal. An interrupt is generated when timer reaches
zero. During timer count down, Port P3 and P4 are
outputting their data, otherwise P3 and P4 are at high
level (acc. to selected port configuration).
- Auto Reload Mode: (see text at Timer 2)
Timer 2
- 8bits timer with 2 modes: Zero Stop and Auto Reload
- Zero Stop as timer1
- Auto Reload mode: Timer starts when a non-zero data is
loaded by CPU and counts down to zero. Then the
loaded data (internally stored) is automatically reload to
the timer counter and the sequence starts again. Each
time when zero is reached, an interrupt is generated.
- Timer clock selectable 256Hz-64Hz-16Hz-4Hz by SW
CHRONO 2x4bits BCD counters
- Start, stop, reset by SW
- 1/100th second resolution
- CARRY flag can be read by SW when the counter
changes from 99 to 0
Event Counter 3bits
- Associated to input port P10, P11; readable to CPU
- Counter counts up to 7 and stays there
- Counter reset by CPU-write
Buzzer Output
- Piezo driver via external NPN transistor
- Activated together with frequency generator
Input Ports P1, P2
- Direct or debounced input read selectable by SW for
each port
- Clocked pulldown or no pulldown by mask option
- P1: Edge detector at P10, P11 (both edges) to generate
pulse for event counter
- Interrupt by P12: both edges, by P13: both edges
- Interrupt by positive edge (debounced) of any P2 input
- Reset by debounced input combination: P13, P22, P23 =
high, enabled by SW
Input / Output Ports P3, P4, P5, P6, P7
- High current drive capability at P3, P4 and P72
- P3, P4: Common direction select P30-P32, P40-P42;
P33 and P43 are individually selectable
- P5: individual direction select, debouncer when input
- As input: direct read of terminal data, as output: register
data
- P3,P4,P72: selectable 9,8,7,6,5,4 or 3 high drive output
in combination with special synchron mode of timer 1
- P5: pull down / pull up according to mask option
- P6: As input: Direct or debounced input read selectable by
SW
- Interrupt by positive edge (debounced) of any P6 input
- Common direction select P60-P61, P62-P63
- P70, P71: As input: Direct or debounced input read
selectable by SW for each port
- Interrupt by positive edge (debounced) of P70, P71 input
- Common direction select P70, P71
EM6635
03/03 REV. B
Copyright
2002, EM Microelectronic-Marin SA
3
www.emmicroelectronic.com
1. Pin
Description
Package
MLF2
Function
Symbol
Type Description
1
Ports
P23
I
Input port with selectable debouncer
2
P22
I
Input port with selectable debouncer
3
P21
I
Input port with selectable debouncer
4
P20
I
Input port with selectable debouncer
5
System
BZ
O
Buzzer output
6
RESET OUT
O
Reset output
7
Power Supply
V
SS
negative supply, substrate
8
Test
TCK
EM test access, must be without any connection
9
TESTRC
EM test access, must be without any connection
10
Oscillator
QOUT
32 kHz quartz connection, input or External clock (metal option)
11
QIN
32 kHz quartz connection, output
12
Not connected
13
Test
TEST
EM test access, must be without any connection
14
System
CENV
Capacitor connection for envelop control tw. V
SS
15
Power Supply
V
RR
Regulated supply voltage, capacitor connection tw. V
SS
16
System
RESET IN
I
active high reset input
17
Ports
P71
I/O
Input/output; low current drive
18
P70
I/O
Input/output; low current drive
19
P63
I/O
Input/output; low current drive
20
P62
I/O
Input/output; low current drive
21
P61
I/O
Input/output; low current drive
22
P60
I/O
Input/output; low current drive
23
P53
I/O
Input/output: configurable as serial clock I/O: SCK
24
P52
I/O
Input/output: configurable as serial output: SOUT
25
P51
I/O
Input/output: configurable as serial status I/O: RDY
26
P50
I/O
Input/output: configurable as serial input: SIN
27
Power Supply
VBAT (V
DD
)
Positive supply, capacitor tw. V
SS
(C depends on VBAT noise)
28
Ports
P13
I
Input port with selectable debouncer and edge detector
29
P12
I
Input port with selectable debouncer and edge detector
30
P11
I
Input port with selectable debouncer and edge detector
31
P10
I
Input port with selectable debouncer and edge detector
32
P72
I/O
Input/output; high current drive
33
P43
I/O
Input/output; high current drive
34
P42
I/O
Input/output; high current drive
35
P41
I/O
Input/output; high current drive
36
P40
I/O
Input/output; high current drive
37
P33
I/O
Input/output; high current drive, P33 configurable as Fout
38
P32
I/O
Input/output; high current drive
39
P31
I/O
Input/output; high current drive
40
P30
I/O
Input/output; high current drive
NC/P63
Not connected
EM6635
03/03 REV. B
Copyright
2002, EM Microelectronic-Marin SA
4
www.emmicroelectronic.com
2. Peripheral
Memory
Allocation
Address HEX
Peripheral Function
0 - 3F
Data RAM page 0, 1, 2, 3
40 - 46
HW Control, Configuration
47 4C
Input/output Ports
4D - 4F
Free
50 - 55
Input/output Ports
56 5E
Timer1, Timer2, BCD counter
5F
Free
60 6B
Event Counter, Freq. Generator
Interrupt Controller
6C
Supply voltage level detector
6D
RC-Oscillator
6E
6F
CPU Index Reg. Low
CPU Index Reg. Hi
70 - 74
Serial Interface
75, 76
EM Test
77
RAM Page Register
78
Reserved
79 7D
Free
7E
7F
EM Test
EM Test
Special Access Modes for HW-Control 1 and -2:
There are two HW-Control registers (HW-Ctl-1, HW-Ctl-2) with different access modes. Each of these two registers can be
accessed by two different addresses. The access by address H40 for HW-Ctl-1 (H42 for HW-Ctl-2) is the normal access
method as every other register in the EM6635: The corresponding data bus value is written into the register bit.
Using address H41 (HW-Ctl-1) or address H43 (HW-Ctl-2) allows a bitwise access to the register. The CPU has not to care
about the states of the register bits which must not be modified.
With a high level at bits 0 to 2, the corresponding bits in the register are selected, while a low level unselects the register
bits. The level of bit 3 defines the action on the selected bits: a high level will set and a low level will clear the selected
register bits. Read access is done in the normal way.
If bits 0, 1, 2 are not selected (at Low level), the register at bit 3 is set if bit 3 is high or reset if it is low.
This concerns SelTBCapHi at HW-Ctl-2, address H43.
2.1 RAM Address Modes
The EM6635 has 4 pages of 64x4bits RAM's built-in. The page number is coded on 2 bits, there are 4 pages.
The page number is stored on RAM index register at address H77.
The RAM is directly addressable on addresses decimal (0 to 63), and it is paged adressable.
To write or read the RAM page1, 2, 3 the user has first to set the offset value in the RAM Index register.
RAM index
PageSel[1]
PageSel[0]
Page
0
0
0
0
1
1
1
0
2
1
1
3
EM6635
03/03 REV. B
Copyright
2002, EM Microelectronic-Marin SA
5
www.emmicroelectronic.com
Ram Architecture
Add
Page
64x4 direct addressable
RAM
Add
Page
64x4 indirect addressable
RAM
Add
Page
64x4 indirect addressable
RAM
Add
Page
64x4 indirect addressable
RAM
RAM_0
4 bit R/W
RAM_0
4 bit R/W
RAM_0
4 bit R/W
RAM_0
4 bit R/W
RAM_1
4 bit R/W
RAM_2
4 bit R/W
RAM_3
4 bit R/W
RAM_60
4 bit R/W
RAM_61
4 bit R/W
RAM_62
4 bit R/W
0
RAM_63
4 bit R/W
1
RAM_63
4 bit R/W
2
RAM_63
4 bit R/W
3
RAM_63
4 bit R/W
CPU Access Format:
Register
Add Hex
Add Dec
bit3
bit2
bit1
bit0
RAM index
77
119
W
R
x
0
x
0
PageSel[1]
PageSel[1]
PageSel[0]
PageSel[0]
3. Operating
Modes
The EM6635 has two low power operating modes, the active and the halt mode. The oscillator is always active in both
modes, whereas the RC-Oscillator is controlled by the CPU.
3.1 Active Mode:
The CPU is running. Instructions are read from the internal ROM and executed by the CPU.
After a system reset, the EM6635 is in active mode at ROM-address H000.
The active mode is stopped by executing the HALT instruction.
3.2 HALT Mode:
After a HALT instruction, the EM6635 is in HALT mode. The CPU is stopped. The 32kHz-oscillator, the prescaler are
running, whereas the timers, the watchdog timer, the BCD counters and the frequency generator are only working, if
activated before.
The RC-oscillator is stopped.
All registers, RAM and output buffers retain their states prior to HALT mode.
The HALT mode is left by an interrupt occurence or by a system reset.
The HALT command enables the global interrupt, i.e. DisINT=0.
Note: HALT mode is activated and XTAL Oscillator is not running. Only a system reset allows to go back in Active mode.
4. Power
Supply
The EM6635 is supplied by a single external power supply between V
DD
(VBAT) and V
SS
(Ground).
A built-in voltage regulator generates V
RR
providing regulated voltage for the oscillator and the internal logic. The output
drivers are supplied directly from the external supply V
DD
. The internal power configuration is shown below in figure 3.
To supply the internal core logic it is possible to use either the internal voltage regulator (V
RR
< V
DD
) or VBAT directly (V
RR
=
V
DD
). The selection is done by mask option. By default the voltage regulator is used. Refer to chapter 17 for the mask
options.
The internal voltage regulator is chosen for high voltage systems. It saves power by reducing the internal core logic's power
supply to an optimum value. However, due to the inherent voltage drop over the regulator the minimal V
DD
is restricted to
1.4V.
A direct VBAT connection can be selected for systems running on a 1.5V battery. The internal RFIL 1kOhm resistor
together with the external capacitor on V
RR
is filtering the V
DD
supply to the internal logic (as a low pass filter to protect the
logic against parasitic over- and under-voltages, e.g. created by piezo shocks).
In this case the minimum V
DD
can be as low as 1.2V.
The output buffers are directly supplied from the external power supply.
Note:
State of I/O pads may not be defined until V
RR
reaches typ. 0.8V and Power-On-Reset supplied by V
RR
clears them
to inputs.
PDF 
ZIP