R
EM6680
Copyright 2005, EM Microelectronic-Marin SA
1
www.emmicroelectronic.com
Ultra Low Power 8-pin Microcontroller
Features
True Low Power:
4.0 A active mode
3.0 A standby mode
0.65 A sleep mode
@ 1.5V, 32kHz, 25C
Low Supply Voltage 1.2 V to 3.6 V
No external component needed
Available in TSSOP-8/14, SO-8/14 packages and die
4-bit ADC or 12 levels Supply Voltage Level
Detector (SVLD)
Max 4 (5*) outputs with 2 high drive outputs of 10mA
Max. 5 (6*) inputs
Sleep Counter Reset (automatic wake-up from sleep
mode (EM patent))
Mask ROM 1536
16 bits
RAM 80
4 bits
Internal RC oscillator 32 kHz 800 kHz
2 clocks per instruction cycle
72 basic instructions
External CPU clock source possible
Watchdog timer (2 sec)
Power-On-Reset with Power-Check on Start-Up
3 wire serial port , 8 bit, master and slave mode
Universal 10-bit counter, PWM, event counter
Prescaler down to 1 Hz (freq. = 32 kHz)
Frequency output 1Hz, 2048 Hz,
CpuClk
, PWM
6 internal interrupt sources ( 2
10-bit counter, 2
prescaler, SVLD, Serial Interface)
2 external interrupt sources (port A)
Description
The EM6680 is an ultra-low voltage, low power
microcontroller coming in a package as small as 8-pin
TSSOP and working up to 0.4 MIPS. It comes with an
integrated 4-bit ADC and 2
high current drive
outputs of
10mA and it requires no external component. It has a
sleep counter reset allowing automatic wake-up from sleep
mode. It is designed for use in battery-operated and field-
powered applications requiring an extended lifetime. A
high integration level make it an ideal choice for cost
sensitive applications.
The EM6680 contains the equivalent of 3kB mask ROM
and a RC oscillator with frequencies between 32 and
800kHz selectable by metal option. It also has a power-
on reset, watchdog timer, 10 bit up/down counter, PWM
and several clock functions.
Tools include windows-based simulator and emulator. A
ROMless version is also available for validation in
development stage (EMDK6680A).
Figure 1. Architecture
Core
EM6600
Stable
RC oscillator
32 - 128kHz
ROM
1536 x 16Bit
RAM
80 x 4Bit
Power Supply
Prescaler
10-Bit Univ
Count/Timer
Interrupt
Controller
Power on
Reset
Watchdog
V
DD
V
DD
Sleep Counter
Reset
* PA5 available only
in 14-pin package
and in die
4-bit ADC
SVLD check
PA1 & PA2:
high current
drive outputs
Serial Interface
PA0 PA1 PA2 PA3 PA4 *PA5
Port A
Reset
Figure 2. Pin Configuration
PA0
1
PA1
2
PA2
3
PA3
4
8
V
DD
7
V
REG
6
PA4
(Reset,ADC)
5
V
SS
EM6680
TSSOP-14, SO-14
NC
1
PA0
2
PA1
3
PA2
4
14
NC
13
V
DD
12
V
REG
11
PA5
10
PA4
(Reset,ADC)
EM6680
PA3
5
NC
6
NC
7
9
V
SS
8
NC
TSSOP-8, SO-8
Typical Applications
Household appliances
Safety and security devices
Automotive controls
Sensor interfaces
Watchdog
Intelligent ADC
Driver (LED, triac)
EM MICROELECTRONIC -
MARIN SA
R
EM6680
Copyright
2005, EM Microelectronic-Marin SA
2
www.emmicroelectronic.com
EM6680 at a glance
Power Supply
- Low voltage low power architecture
including internal voltage regulator
- 1.2 V to 3.6 V supply voltage
- 4.0 A in active mode
- 3.5 A in standby mode
- 0.35 A in sleep mode
@ 1.5V, 32kHz, 25C
RAM
- 80 x 4 bit, directly addressable
ROM
- 1536 x 16 bit (~3k Byte), metal mask programmable
CPU
- 4-bit RISC architecture
- 2 clock cycles per instruction (CPI=2)
- 72 basic instructions
Main Operating Modes and Resets
- Active mode (CPU is running)
- Standby mode (CPU in halt, peripherals running)
- Sleep mode (no clock, data kept)
- Initial Power-On-Reset with Power-Check
- Watchdog reset (logic)
- Reset terminal (software option on PA[3/4])
- Sleep Counter reset from Sleep mode
- Wakeup on change from Sleep mode
Prescaler
- Divider (4 stages) to best fit CPU clock (32kHz 1MHz
to 32kHz system clock to keep peripherals timing close
to specification
- 15 stage system clock divider from 32kHz down to 1Hz
- 2 Interrupt requests (3 different frequencies)
- Prescaler reset (4kHz to 1Hz)
8-Bit Serial Interface
- 3 wire (Clock, DataIn , DataOut) master/slave mode
- READY output during data transfer
- Maximum shift clock is equal to the main system clock
- Interrupt request to the CPU after 8 bit data transfer
- Supports different serial formats
- pins shared with general 4 bit PA[3:0] I/O port
Oscillator
- RC Oscillator range: 32/50kHz to 500/800kHz
(metal selectable from 32/50, 64/100, 128/200, 256/400
or 500/800 kHz typ. for CPU clock)
- No external components are necessary
- Temperature compensated
- External clock source possible from PA[1]
4(5)-Bit I/O PA[3:0] & PA[4] / PA[5]*
- Direct input read on the port terminals
- 2 Debounce function available muxed on 4 inputs
- 2 Interrupt request on positive or negative edge
- Pull-up or pull-down or none selectable by register,
except PA[4] where pullup/down is mask selection
- 2 Test variables (software) for conditional jumps
- PA[1] and PA[3/4] are inputs for the event counter
- PA[3/4] Reset input (register selectable)
- All outputs can be put tri-state (default)
- Selectable pull-downs in input mode
- CMOS or
Nch.
open drain outputs
- Weak pull-up selectable in Nch.
open drain
mode
4-bit ADC & Voltage Level Det. (SVLD)
- External voltage compare from PA[4] input possible (low
resolution 4 bit AD converter)
-12 different levels from 1.2 V to 3.0 V for SVLD
- Used for Power Check after POR (1.25V or 1.85V)
- Busy flag during measure
- Interrupt generated if SVLD measurement low
10-Bit Universal Counter
- 10, 8, 6 or 4 bit up/down counting
- Parallel load
- Event counting (PA[1] or PA[3/4])
- 8 different input clocks
- Full 10 bit or limited (8, 6, 4 bit)
compare function
- 2 interrupt requests (on compare and on 0)
- Hi-frequency input on PA[1] and PA[3/4]
or CPUclk/2
- Pulse width modulation (PWM) output
Interrupt Controller
- 2 external and 6 internal interrupt request sources
- Each interrupt request can individually be masked
- Each interrupt flag can individually be reset
- Automatic reset of each interrupt request after read
- General interrupt request to CPU can be disabled
- Automatic enabling of general interrupt request flag
when going into HALT mode
Sleep Counter Reset (SCR)
- wake up the EM6680 from sleep mode
- 4 timings selectable by register
- Inhibit SCR by register
Package form available
- TSSOP-8/14
- SO-8/14
- Die form (9 pin possible due to additional I/O pin)
NB: All frequencies written in this document are related to a typical system clock of 32 kHz !
R
EM6680
Copyright
2005, EM Microelectronic-Marin SA
3
www.emmicroelectronic.com
Table of Contents
FEATURES______________________________
1H1H
1
DESCRIPTION ___________________________
2H2H
1
EM6680 AT A GLANCE ____________________
3H3H
2
1.
PIN DESCRIPTION FOR EM6680 _______
4H4H
4
2.
OPERATING MODES ________________
5H5H
5
2.1
ACTIVE
M
ODE
_______________________
6H6H
5
2.2
STANDBY
(H
ALT
)
M
ODE
_______________
7H7H
5
2.3
SLEEP
M
ODE
_______________________
8H8H
5
3.
POWER SUPPLY____________________
9H9H
6
4.
RESET ____________________________
10H10H
7
4.1
POR
WITH
P
OWER
-C
HECK
R
ESET
_________
11H11H
8
4.2
I
NPUT
P
ORT
A
R
ESET
__________________
12H12H
9
4.3
D
IGITAL
W
ATCHDOG
T
IMER
R
ESET
________
13H13H
9
4.4
S
LEEP
C
OUNTER
R
ESET
_______________
14H14H
10
4.5
W
AKE
-U
P ON
C
HANGE
________________
15H15H
10
4.6
T
HE
CPU
S
TATE AFTER
R
ESET
__________
16H16H
10
5.
OSCILLATOR AND PRESCALER _____
17H17H
11
5.1
RC
O
SCILLATOR OR EXTERNAL
C
LOCK
_____
18H18H
11
5.2
S
PECIAL
4
STAGE
F
REQUENCY
D
IVIDER
____
19H19H
12
5.3
P
RESCALER
________________________
20H20H
12
6.
INPUT AND OUTPUT PORT A ________
21H21H
14
6.1
I
NPUT
/
O
UTPUT
P
ORT
O
VERVIEW
________
22H22H
14
6.2
P
ORT
A
AS
I
NPUT AND ITS
M
ULTIPLEXING
___
23H23H
15
6.2.1
Debouncer __________________________
24H24H
15
6.2.2
IRQ on Port A _______________________
25H25H
16
6.2.3
Pull-up/down ________________________
26H26H
16
6.2.4
Software test variables ________________
27H27H
17
6.2.5
Port A for 10-Bit Counter _______________
28H28H
17
6.2.6
Port A Wake-Up on change_____________
29H29H
17
6.2.7
Port A for Serial Interface ______________
30H30H
17
6.2.8
Port A for External Reset_______________
31H31H
17
6.2.9
Port PA[4] as Comparator Input _________
32H32H
17
6.2.10
Reset and Sleep on Port A _____________
33H33H
17
6.2.11
Port A Blocked Inputs _________________
34H34H
17
6.3
P
ORT
A
AS
O
UTPUT AND ITS
M
ULTIPLEXING
_
35H35H
18
6.3.1
CMOS / Nch. Open Drain Output ________
36H36H
18
6.4
P
ORT
A
REGISTERS
___________________
37H37H
19
7.
SERIAL PORT _____________________
38H38H
21
7.1
G
ENERAL
F
UNCTIONAL
D
ESCRIPTION
______
39H39H
22
7.2
D
ETAILED
F
UNCTIONAL
D
ESCRIPTION
______
40H40H
22
7.2.1
Output Modes _______________________
41H41H
23
7.3
S
ERIAL
I
NTERFACE
R
EGISTERS
__________
42H42H
25
8.
10-BIT COUNTER __________________
43H43H
26
8.1
F
ULL AND
L
IMITED
B
IT
C
OUNTING
________
44H44H
26
8.2
F
REQUENCY
S
ELECT AND
U
P
/D
OWN
C
OUNTING
45H45H
27
8.3
E
VENT
C
OUNTING
____________________
46H46H
28
8.4
P
ULSE
W
IDTH
M
ODULATION
(PWM) _______
47H47H
28
8.4.1
How the PWM Generator works._________
48H48H
29
8.4.2
PWM Characteristics__________________
49H49H
30
8.5
C
OUNTER
S
ETUP
_____________________
50H50H
30
8.6
10-
BIT
C
OUNTER
R
EGISTERS
____________
51H51H
31
9.
SUPPLY VOLTAGE LEVEL DETECTOR /
4-BIT ADC ______________________________
52H52H
33
10.
ADC/SVLD COMPARATOR
CHARACTERISTICS ______________________
53H53H
36
11.
RAM _____________________________
54H54H
36
12.
INTERRUPT CONTROLLER __________
55H55H
37
12.1
I
NTERRUPT CONTROL REGISTERS
_________
56H56H
38
13.
PERIPHERAL MEMORY MAP _________
57H57H
39
14.
ACTIVE SUPPLY CURRENT TEST _____
58H58H
41
15.
MASK OPTIONS____________________
59H59H
42
15.1
I
NPUT
/
O
UTPUT
P
ORTS
________________
60H60H
42
15.1.1
Port A Metal Options __________________
61H61H
42
15.1.2
RC oscillator Frequency Option _________
62H62H
43
15.1.3
Debouncer Frequency Option ___________
63H63H
43
15.1.4
Power-Check Level Option _____________
64H64H
43
15.1.5
ADC/SVLD Voltage Level #15___________
65H65H
43
15.1.6
Counter Update option ________________
66H66H
44
15.1.7
Voltage Regulator level ________________
67H67H
44
16.
TEMP. AND VOLTAGE BEHAVIORS ___
68H68H
45
16.1
I
DD
C
URRENT
(T
YPICAL
)
AND
V
REG
FOR
2
THRESHOLDS AND
1/3
OF POSSIBLE CURRENT
FOR
V
REG
.___________________________
69H69H
45
16.2
P
ULL
-
DOWN
R
ESISTANCE
(T
YPICAL
) _______
70H70H
45
16.3
P
ULL
-
UP
R
ESISTANCE
(T
YPICAL
)__________
71H71H
45
16.4
O
UTPUT
C
URRENTS
(T
YPICAL
) ___________
72H72H
46
17.
ELECTRICAL SPECIFICATION ________
73H73H
48
17.1
A
BSOLUTE
M
AXIMUM
R
ATINGS
___________
74H74H
48
17.2
H
ANDLING
P
ROCEDURES
_______________
75H75H
48
17.3
S
TANDARD
O
PERATING
C
ONDITIONS
_______
76H76H
48
17.4
DC
C
HARACTERISTICS
-
P
OWER
S
UPPLY
___
77H77H
49
17.5
S
UPPLY
V
OLTAGE
L
EVEL
D
ETECTOR
_______
78H78H
51
17.6
DC
CHARACTERISTICS
-
I/O
P
INS
_________
79H79H
53
17.7
RC
OSCILLATOR FREQUENCY
____________
80H80H
54
17.8
S
LEEP
C
OUNTER
R
ESET
-
SCR __________
81H81H
55
18.
PACKAGE DIMENSIONS_____________
82H82H
56
18.1
SO-8/14 ___________________________
83H83H
56
18.2
TSSOP-8/14 _______________________
84H84H
57
19.
ORDERING INFORMATION___________
85H85H
58
19.1
P
ACKAGE
M
ARKING
___________________
86H86H
58
19.2
C
USTOMER
M
ARKING
__________________
87H87H
58
R
EM6680
Copyright
2005, EM Microelectronic-Marin SA
4
www.emmicroelectronic.com
1. Pin Description for EM6680
Table 1 EM6680 pin descriptions
# On
Chip
SO-8
Signal
Name
Description
1
1
PA0
general I/O, serial In, Wake-Up on Change, IRQ source,...
2
2
PA1
general I/O, serial CLK, timer source, external clock
3
3
PA2
general I/O, serial Out, freq., CPU reset status output,...
4
4
PA3
general I/O, serial Rdy/Cs, Interrupt source, Reset
5 5 V
ss
ground negative supply pin
6
6
PA4
general I, Reset, timer source, Interrupt source, Wake-Up, Compare I
7*
NC
PA5
general I/O, freq, Wake-Up on Change, IRQ source
8 7 V
reg
regulated voltage supported by 100nF tw. V
ss
9 8 V
dd
positive supply pin capacitance tw. V
dd
(C depends on V
dd
noise)
Figure 3. Typical configuration for V
dd
> 1.5V
uPUS 4bits core
Digital peripherals
RAM 64 x 4 bits
ROM 1536 x 16 bits
Analog peripherals
RC oscillator
Power-on-Reset
Sleep Reset Cnt
SVLD
4-bit ADC
Voltage
regulator
Level Shifter
Vreg
Capacitor
100nF
C
Vreg
Vdd
I/O pad
Vss
Vbat
C
Vdd
For Vdd > 1.5V
Typ_config_vdd+15.vsd
Figure 4. Typical configuration for V
dd
< 1.5V
uPUS 4bits core
Digital peripherals
RAM 64 x 4 bits
ROM 1536 x 16 bits
Analog peripherals
RC oscillator
Power-on-Reset
Sleep Reset Cnt
SVLD
4-bit ADC
Voltage
regulator
Level Shifter
Vreg
Capacitor
100nF
C
Vreg
Vdd
I/O pad
Vss
Vbat
C
Vdd
For Vdd > 1.5V
Typ_config_vdd+15.vsd
Regulated Voltage
NOTE: State of I/O pads may not be defined until V
reg
reaches typ. 0.8V and Power-On-Reset logic
supplied by V
reg
clears them to Inputs.
On I/O pins there are protective diodes towards V
dd
and V
ss
.
R
EM6680
Copyright
2005, EM Microelectronic-Marin SA
5
www.emmicroelectronic.com
2. Operating modes
The EM6680 can operate in three different modes of which 2 are low-power dissipation modes (Stand-By and
Sleep). The modes and transitions between them are shown in Figure 5.
1.) Active mode
2.) Stand-By mode
3.) Sleep mode
Figure 5. EM6680 operating mode transitions
2.1 ACTIVE Mode
The active mode is the actual CPU running mode. Instructions are read from the internal ROM and executed by
the CPU. Leaving the active mode: via the halt instruction to go into standby mode, writing the SLEEP bit to go
into Sleep mode or detecting the reset to go into reset mode.
2.2 STANDBY (Halt) Mode
Executing a HALT instruction puts the EM6680 into standby mode. The voltage regulator, oscillator, watchdog
timer, interrupts, timers and counters are operating. However, the CPU stops since the clock related to
instruction execution stops. Registers, RAM and I/O pins retain their states prior to STANDBY mode.
STANDBY is cancelled by a RESET or an Interrupt request if enabled.
2.3 SLEEP Mode
Writing to the Sleep bit in the RegSysCntl1 register puts the EM6680 in sleep mode. The oscillator stops and
most functions of the EM6680 are inactive. To be able to write to the Sleep bit, the SleepEn bit in
RegSysCntl2 must first be set to "1". In SLEEP mode only the voltage regulator is active to maintain the RAM
data integrity, the peripheral functions are stopped and the CPU is reset. SLEEP mode may be cancelled by
Wake/Up on change, external reset or by Sleep Reset Counter if any of them is enabled
.
Waking up from sleep mode may takes some time to guarantee stable oscillation. Coming back from sleep
mode puts the EM6681 in reset state and as such reinitializes all registers to their reset value. Waking up from
sleep mode clears the Sleep flag but not the SleepEn bit. Inspecting the SleepEn allows to determine if the
EM6680 was powered up (SleepEn = "0") or woken from sleep mode (SleepEn = "1").
START-UP
RESET
ACTIVE
or running
mode
STAND-BY
or HALT
mode
Clocks active
SLEEP
POWER-ON
Power-On-Reset & Power Check Level
POR static level
Power-Check Active
RC oscilator
running
8 oscillator
periods
reset synchronizer
and
Power-Check
8 CPU clock
periods
Reset-pad
WDreset
PORwPC
PORwPC
PORwPC
PORwPC
Everything stopped
Registers and
RAM keep their value
HALT instruction
interrupt/event
Sleep bit set
SleepResCnt
WakeUp on
Change
resetPortA
WDreset
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