R
EM6812
Copyright 2004, EM Microelectronic-Marin SA
2
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1 EM6812 at a glance
Power supply
"
Low power architecture
"
Voltage regulator for internal logic supply
"
External regulator capacitor
CPU
"
8 bit CoolRisc 816L Core
"
16 internal registers
"
4 hardware subroutine stacks
"
8 bit hardware multiplier
"
refer also to the CR816L reference manual
ROM / Flash
"
ROM 4096 Instructions = 11.26 Kbytes
"
Flash 8192 Instructions = 22.5 Kbytes
RAM
"
512 x 8 bit static SRAM (for 8k Instructions)
"
256 x 8 bit static SRAM (for < 4k Instructions)
"
low voltage ram data retention
Low power RAM, 12 Byte
"
for lowest power calculations
Dual Port RAM, 4 Byte
"
Data IO on port B, Control on port A
Operating modes
"
Active mode: CPU and peripherals are running
"
Standby mode: CPU halted, peripherals on
"
Sleep mode: no clocks, reset state
"
Wake Up from port A inputs
Resets
"
Power On Reset
"
Reset from watchdog timer
"
External Reset Input
"
Brown
Out
"
Reset with Port A reset combination
"
Reset Flags to identify the reset source
Oscillator XTAL 32kHZ
"
Oscillation clock pre-divider (1 sec)
"
External clock low frequency input
Oscillator RC
"
internal RC oscillator
"
External clock high frequency input
"
Freq. Trimming register
"
1MHz or 10MHz Clocks
"
stable over temperature and voltage
Prescaler's
"
2 Prescaler for RC and Xtal Oscillators
"
input clock software selectable
"
fix interval IRQ's (RTC and others)
"
clock source to other peripherals
"
Divider capture, 8 MSB's
Parallel In/Output Port A
"
8 bit wide direct input read
"
all functions bit-wise configurable
"
Input , output
"
debouncer
"
IRQ on pos. or neg. edge
"
Pull-up, pull-down or no pull selectable
"
Freq. Input for timer
"
Input combination reset
"
CMOS or NCH. Open Drain outputs
Parallel In/Output Port B
"
8 multipurpose I/O's
"
8 bit wide direct input read
"
all functions bit-wise configurable
"
4 high current outputs
"
Input , output
"
Pull-up, pull-down or no pull selectable
"
CMOS or NCH. Open Drain outputs
"
special function: Serial Interface I/O's, DP RAM
Serial Interface SPI
"
3 wire serial Interface, Sclk, Din, Dout
Timer (4 x 8 bit, or 2 x 16 bit)
"
8 (16) bit wide, Zero-Stop and Auto-Reload mode
"
External signal pulse width measurement
"
PWM
generation
"
Event
Counter
"
IRQ
requests
Watchdog timer
"
generation of watchdog reset after time out
Interrupt
"
external IRQ's from Port A, Comparator
"
internal IRQ's from Timer, Prescaler
SVLD
"
8 levels supply voltage level check
Brown Out
"
On-chip Brown-Out detection, reset state
"
Power check at Startup
R
EM6812
Copyright
2004, EM Microelectronic-Marin SA
3
www.emmicroelectronic.com
Table of contents
1
EM6812 at a glance
2
2 Circuit
Connectivity
5
2.1 Terminal
usage
6
2.2 Programming
connections
7
3 Operating
modes
8
3.1 Active
mode
8
3.2 Standby
Mode
8
3.3 Sleep
Mode
8
3.4 System
registers
9
4 Program
Memory
10
4.1 Memory
miss
10
5 Data
Memory
12
5.1 SRAM
12
5.2
General Purpose Registers, 16 Bytes
13
5.3
Dual Port RAM
13
5.3.1
CPU R/W access to DPR
13
5.3.2
External Write Access to DPR
14
5.3.3
Read Access from DPR
14
5.3.4 Conflict
handling
15
5.3.5 Register
overview
15
6 CPU
16
7 Reset
Controller
17
7.1 Basic
features
17
7.1.1
Reset functions registers
18
7.2
POR and PowerCheck
19
7.3 Reset
Pad
20
7.4
PortA Input Reset
20
7.5 BrownOut
reset
21
7.5.1 BO
Timings
21
7.6 Watchdog
22
7.6.1 Watchdog
counter
22
7.6.2 Lock/Unlock
22
8 Clock
management
23
8.1 Basic
features
23
8.1.1 Overview
23
8.2
High frequency clock source
24
8.2.1 RC
oscillator
24
8.2.2
High frequency external clock
25
8.3
Low frequency clock source:
26
8.3.1 Crystal
oscillator
26
8.3.2
Low frequency external clock
27
8.3.3
Data input on OscOut
27
8.4 Clock
synchronization
27
8.5
CPU clock selection
28
8.6
Peripheral clocks generation
28
8.6.1 Prescaler2
(10
stages)
29
8.6.2 Prescaler1
(15
stages)
30
8.7
RC clock trimming with Xtal oscillator
31
8.8 Registers
overview
32
9
Supply Voltage Level Detector (SVLD)
33
10 Port
A
34
10.1 Basic
features
34
10.1.1 Overview
35
10.1.2
Register map, PA IO functions
36
10.1.3 IO
Operation
37
10.2
Port A Interrupt requests
38
10.2.1 Debouncer
38
10.3
Reset and Wake-up
39
10.3.1
Register map
40
10.3.2 Input
splitting
40
10.3.3 Actions
40
10.3.4 Condition
match
40
10.3.5
Don't care bits
41
10.3.6 Debouncer
41
10.4 Oscillation
Loop
41
10.4.1 Inverter
function
41
10.5
Dual Port RAM interface
41
11 Port
B
42
11.1 Basic
features
42
11.1.1
Special function priority handling
42
11.1.2 Overview
43
11.2
Register map, PB IO functions
44
11.3
Normal IO operation
45
11.4
Special IO operation
45
11.4.1 Frequency
Output
45
11.4.2 SPI
outputs
46
11.4.3 SPI
inputs
46
11.4.4
Dual Port RAM terminals
46
12 Serial Port Interface
47
12.1 Basic
features:
47
12.1.1 Overview:
47
12.1.2
SPI terminal configuration
48
12.2 Functionality
48
12.2.1
Master and Slave modes
48
12.2.2
Fix data stream Output (Auto-Start)
48
12.2.3 SPI
Interruptions
48
12.2.4
SPI edge and synchronization selection 49
12.2.5 SPI
start-up
49
12.2.6
MSB or LSB first selection
49
12.3 Registers
overview:
50
13 Timers
51
13.1 Basic
features:
51
13.2 Functionality
52
13.2.1 Auto-Reload
mode
52
13.2.2 Zero-Stop
mode
53
13.2.3
Start control system
54
13.2.4
Stopping the timer
57
13.2.5 Clock
selection
57
13.2.6
PWM and Frequency generation
57
13.2.7 16-bits
configuration
58
13.2.8 Interrupts
59
13.3 Recommended
programming
order
60
13.4 Registers
overview:
60
13.4.1 General
configuration registers
60
13.4.2 Timer1
configuration
61
13.4.3 Timer2
configuration
62
13.4.4 Timer3
configuration
63
13.4.5 Timer4
configuration
64
14 Interruptions
65
14.1 Basic
features
65
14.2 Interrupt
acquisition
66
14.2.1
Interrupt acquisition masking.
67
14.2.2
Interrupt acquisition Clearing
67
14.2.3
Register map, Interrupt acquisition
67
14.3
CPU Interrupt and Event handling
68
14.3.1 Interrupt
priority
68
14.3.2
CPU Status register
69
14.3.3
CPU Status register pipeline exception 69
14.3.4
Processor vector table
70
14.3.5 Context
Saving
70
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EM6812
Copyright
2004, EM Microelectronic-Marin SA
4
www.emmicroelectronic.com
Memory mapping
71
16 Typical V and T dependencies
74
16.1 IVDD
Currents
74
16.2
SVLD, BO Detection levels
75
16.3
IOL and IOH drives
75
16.4
Pullup and Pulldown
75
17 Electrical
Specification
76
17.1
Absolute Maximum Ratings
76
17.2 Handling
Procedures
76
17.3
Standard Operating Conditions
76
17.4
Typical Crystal specification
76
17.5
DC Characteristics - Power Supply Currents 76
17.6
DC Characteristics Voltage detection levels77
17.7
DC Characteristics Oscillators
77
17.8
DC Characteristics - I/O Pins
78
17.9 Package
drawings
79
18 Ordering information Flash device
80
19 Datasheet
History
Error! Bookmark not defined.
R
EM6812
Copyright
2004, EM Microelectronic-Marin SA
5
www.emmicroelectronic.com
2 Circuit
Connectivity
The EM6812 has the same pin-out in both the SO24 and TSSOP24 pin package.
Minimum connectivity includes the power supply on V
SS
and V
DD
, a capacitor on on Vreg, and de-coupling capacitance on
V
DD
. Circuit reference terminal (substrate) is on V
SS
.
The 32kHz XTAL is only needed for systems requiring low frequency Crystal operation.
The integrated supply voltage regulator filters supply noise and allows lowest power peripheral operations. For proper
operation, a capacitor (470nF minimum) must be connected to the regulator's VREG terminal. This terminal must not be
used for any other outside connection.
Figure 1: Sample minimum connectivity
Note:
ALL circuit IO's (except OscIn) are on V
DD
level. OscIn terminal is only used in conjunction with an active Crystal
oscillator. Its input voltage must never exceed the Vreg voltage.
The crystal oscillator should be shielded with V
SS
to keep noise away.
When using the Crystal oscillator PA[7] and PA[6] should preferably used as static inputs only to avoid noise coupling
on the OscIn and OscOut high impedance inputs.
E
M
6
8
1
2
PB3
PB2
PB1
PB0
i.c.
VSS
Test
Reset
PA0
PA1
PA2
PA3
PA7
PA6
PA5
PA4
Vreg
VDD
OscOut
OscIn
PB5
PB6
PB7
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
VDD
32khz
VDD
VSS
470nF
PB4
Reset
Button
Shield
with
VSS
VSS
10k
R
EM6812
Copyright
2004, EM Microelectronic-Marin SA
6
www.emmicroelectronic.com
2.1 Terminal
usage
Table 1. Circuit terminals
Pin Name
Description
SPI & PWM
Dual
Port
RAM
Programming
connections
1 PB4
IO Standard
IO
DPRData[4]
2 PB5
IO Standard
IO
SCLK
DPRData[5] SCLK
3 PB6
IO Standard
IO
SOUT
DPRData[6]
4 PB7
IO Standard
IO
SIN
DPRData[7] SDIO
5
Vreg
Sup Connect min 470nF
6 V
DD
Sup Main power supply
V
DD
7 OscOut In Crystal,
External LF Clock input,
Data input
8
OscIn
In
Crystal only connection
9
PA7
IO,
Standard IO, IRQ, timer start & clock,
10
PA6
IO,
Standard IO, IRQ, timer start & clock
11
PA5
IO,
Standard IO, IRQ, timer start & clock
12
PA4
IO
Standard IO, IRQ, timer start & clock
13
PA3
IO
Standard IO, IRQ, timer start & clock
ExtAdr[1]
14
PA2
IO
Standard IO, IRQ, timer start & clock
ExtAdr[0]
15
PA1
IO
Standard IO, IRQ, timer start & clock
ExtWEn
16
PA0
IO
Standard IO, IRQ, timer start & clock
ExtCen
17
Reset
In
Reset input, active high with internal pull-down
resistor
18
Test
In
EM test and Program high Voltage
See note.
VPP
19 V
SS
Sup
Reference
terminal
V
SS
20
i.c.
Used for EM test purposes, internally connected. Must not be connected externally
21
PB0
IO
Standard IO, drive 2
PWM
DPRData[0]
22
PB1
IO
Standard IO, drive 2
PWM
DPRData[1]
23
PB2
IO
Standard IO, drive 2
PWM
DPRData[2]
24
PB3
IO
Standard IO, drive 2
PWM
DPRData[3]
Notes:
Connection on Test pin:
On Flash device, either connect to V
SS
via a 10kOhm resistor (as close as possible to V
SS
pad) or foresee a jumper
for programming (V
SS
or VPP connection)
Connection on pin i.c. (i.c stands for internally connected).
This pin is used in EM test modes. No external connection must be made on this pin.
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