R
EM6821
Copyright
2005, EM Microelectronic-Marin SA
1
www.emmicroelectronic.com
Ultra Low Power Controller with 4x20 LCD Driver
Features
Low Power
- 1.3 A active mode, LCD On
- 0.4 A standby mode, LCD Off
- 0.1 A sleep mode
@ 3 V, 32 KHz, 25 C
Low Voltage - 1.2 to 3.6 V
2 clocks per instruction cycle
72 basic instructions
ROM 4k x 16 bits
RAM 128 x 4 bits
Max. 12 inputs ; port A, port B, port SP
Max. 8 outputs ; port B, port SP
Voltage Level Detector, 8 levels software
selectable from 1.2 V up to 4.0 V
Melody, 7 tones + silence inclusive 4-bit timer
Universal 10-bit counter, PWM, event counter
Prescaler down to 1 second ( crystal = 32 KHz )
1/1000 sec 12 bit binary coded decimal counter
with hard or software start/stop function
LCD 20 Segments, 3 or 4 times multiplexed
3 wire serial port , 8 bit, master and slave mode
5 external interrupts (port A, serial interface)
8 internal interrupts (3x prescaler, BCD counter
2x10-bit counter, melody timer, serial interface)
timer watchdog and oscillation supervisor
Description
The EM6821 is an advanced single chip low cost
CMOS microcontroller. It contains ROM, RAM,
LCD driver, power on reset, watchdog timer,
oscillation detection circuit, 10-bit up/down and
event counter, 1ms BCD counter, prescaler,
voltage level detector (Vld), serial interface and
several clock functions. The low voltage feature
and low power consumption make it the most
suitable controller for battery, stand alone and
mobile equipment. The EM6821 is manufactured
using EM Microelectronic'a advanced low power
(ALP) CMOS process.
Typical Applications
Timing
device
Timer / sports timing devices
Bicycle
computers
Measurement
equipment
Domestic
appliance
Interactive system with display
Automotive controls with display
Safety and security devices
Figure 1. Architecture
Figure 2. Pin Configuration, TQFP52 10x10x1 mm
EM MICROELECTRONIC -
MARIN SA
R
EM6821
Copyright
2005, EM Microelectronic-Marin SA
2
www.emmicroelectronic.com
EM6821 at a glance
Power Supply
- Low voltage low power architecture
including internal voltage regulator
- 1.2 ... 3.6 V battery voltage
- 1.3 A in active mode (Xtal, LCD on, 25
C)
- 0.4 A in standby mode (Xtal, LCD off, 25
C)
- 0.1 A in sleep mode (25
C)
- 32 KHz Oscillator
RAM
- 64 x 4 bit, direct addressable
-
64 x 4 bit, indexed addressable
ROM
- 4k x 16 bit, metal mask programmable
CPU
- 4-bit RISC architecture
- 2 clock cycles per instruction
- 72 basic instructions
Main Operating Modes and Resets
- Active mode (CPU is running)
- Standby mode (CPU in halt)
- Sleep mode (no clock, reset state)
- Initial reset on power on (POR)
- Watchdog reset (logic and oscillation watchdogs)
- Reset terminal
- Reset with input combination on port A (register
selectable)
Prescaler
- 15 stage system clock divider down to 1Hz
- 3 Interrupt requests; 1Hz, 32Hz or 8Hz, Blink
- Prescaler reset (4kHz to 1Hz)
Liquid Crystal Display Driver (LCD)
- 20 Segments 3 or 4 times multiplexed
- Internal or external voltage multiplier
- Free Segment allocation architecture (metal 2 mask)
- LCD switch off for power save
8-Bit Serial Interface
- 3 wire (Clock, DataIn , DataOut) master/slave mode
- READY output during data transfer
- Maximum shift clock is equal to the main system clock
- Interrupt request to the CPU after 8 bits data transfer
- Supports different serial formats
- Can be configured as a parallel 4 bit input/output port
- Direct input read on the port terminals
- All outputs can be put tristate (default)
- Selectable pull-downs in input mode
- CMOS or
Nch.
open drain outputs
- Weak pull-up selectable in Nch.
open drain
mode
4-Bit Input Port A
- Direct input read on the port terminals
- Debouncer function available on all inputs
- Interrupt request on positive or negative edge
- Pull-up or pull-down or none selectable by register
- Test variables (software) for conditional jumps
- PA[0] and PA[3] are inputs for the event counter
- PA[3] is Start/Stop input for the millisecond counter
- Reset with input combination (register selectable)
4-Bit Bi-directional Port B
- All different functions bit-wise selectable
- Direct input read on the port terminals
- Data output latches
- CMOS or Nch. open drain outputs
- Pull-down or pull-up selectable
- Weak pull-up in Nch. open drain mode
- Selectable PWM, 32kHz, 1kHz and 1Hz output
Melody Generator
- Dedicated Buzzer terminal
- 7 tones plus silence output
- The output can be put tristate (default)
- Internal 4-bit timer, usable also in standalone mode
- 4 different timer input clocks
- Timer with automatic reload or single run
- Timer interrupt request when reaching 0
Voltage Level Detector (SVLD)
- 8 different levels from 1.2 V to 4.0 V.
- Busy flag during measure
10-Bit Universal Counter
- 10, 8, 6 or 4 bit up/down counting
- Parallel load
- Event counting (PA[0] or PA[3])
- 8 different input clocks-
- Full 10 bit or limited (8, 6, 4 bit)
compare function
- 2 interrupt requests (on compare and on 0)
- Hi-frequency input on PA[3] and PA[0]
- Pulse width modulation (PWM) output
Millisecond Counter
- 3 digits binary coded decimal counter (12 bits)
- PA[3] input signal pulse width and period measurement
- Internal 1000 Hz clock generation
- Hardware or software controlled start stop mode
- Interrupt request on either 1/10 Sec or 1Sec
Interrupt Controller
- 5 external and 8 internal interrupt request sources
- Each interrupt request can individually be masked
- Each interrupt flag can individually be reset
- Automatic reset of each interrupt request after read
- General interrupt request to CPU can be disabled
- Automatic enabling of general interrupt request flag
when going into HALT mode.
R
EM6821
Copyright
2005, EM Microelectronic-Marin SA
3
www.emmicroelectronic.com
Table of Contents
FEATURES __________________________________1
DESCRIPTION _______________________________1
TYPICAL APPLICATIONS _______________________1
EM6821 AT A GLANCE _________________________2
1.
PIN DESCRIPTION FOR EM6821 _____________4
2.
OPERATING MODES ______________________6
2.1
A
CTIVE
M
ODE
____________________________6
2.2
S
TANDBY
M
ODE
__________________________6
2.3
S
LEEP
M
ODE
____________________________6
3.
POWER SUPPLY__________________________7
4.
RESET __________________________________8
4.1
O
SCILLATION
D
ETECTION
C
IRCUIT
_____________9
4.2
R
ESET
T
ERMINAL
_________________________9
4.3
I
NPUT
P
ORT
A
R
ESET
F
UNCTION
______________9
4.4
D
IGITAL
W
ATCHDOG
T
IMER
R
ESET
____________10
4.5
CPU
S
TATE AFTER
R
ESET
__________________10
5.
OSCILLATOR AND PRESCALER____________11
5.1
O
SCILLATOR
____________________________11
5.2
P
RESCALER
____________________________11
6.
INPUT AND OUTPUT PORTS _______________13
6.1
P
ORTS
O
VERVIEW
________________________13
6.2
P
ORT
A _______________________________14
6.2.1
IRQ on Port A ______________________14
6.2.2
Pull-up or Pull-down _________________15
6.2.3
Software Test Variables ______________15
6.2.4
Port A for 10-Bit Counter and MSC _____15
6.3
P
ORT
A
R
EGISTERS
_______________________15
6.4
P
ORT
B _______________________________17
6.4.1
Input / Output Mode _________________17
6.4.2
Pull-up or Pull-down _________________18
6.4.3
CMOS / NCH. Open Drain Output ______18
6.4.4
PWM and Frequency Output __________19
6.5
P
ORT
B
R
EGISTERS
_______________________19
6.6
P
ORT
S
ERIAL
___________________________20
6.6.1
4-bit Parallel I/O ____________________20
6.6.2
Pull-up or Pull-down _________________21
6.6.3
Nch. Open Drain Outputs _____________22
6.6.4
General Functional Description ________22
6.6.5
Detailed Functional Description ________23
6.6.6
Output Modes ______________________23
6.6.7
Reset and Sleep on Port SP___________24
6.7
S
ERIAL
I
NTERFACE
R
EGISTERS
_______________25
7.
MELODY, BUZZER _______________________27
7.1
4-B
IT
T
IMER
____________________________27
7.1.1
Single Run Mode ___________________28
7.1.2
Continuos Run Mode ________________28
7.2
P
ROGRAMMING
O
RDER
____________________29
7.3
M
ELODY
R
EGISTERS
______________________29
8.
10-BIT COUNTER ________________________31
8.1
F
ULL AND
L
IMITED
B
IT
C
OUNTING
_____________31
8.2
F
REQUENCY
S
ELECT AND
U
P
/D
OWN
C
OUNTING
___32
8.3
E
VENT
C
OUNTING
________________________33
8.4
C
OMPARE
F
UNCTION
______________________33
8.5
P
ULSE
W
IDTH
M
ODULATION
(PWM) ___________33
8.5.1
How the PWM Generator works. _______34
8.5.2
PWM Characteristics ________________ 34
8.6
C
OUNTER
S
ETUP
_________________________ 35
8.7
10-
BIT
C
OUNTER
R
EGISTERS
________________ 35
9.
MILLISECOND COUNTER _________________ 37
9.1
PA[3]
I
NPUT FOR
MSC ____________________ 37
9.2
IRQ
FROM
MSC _________________________ 37
9.3
MSC-M
ODES
___________________________ 38
9.4
M
ODE SELECTION
________________________ 38
9.5
M
ILLISECOND
C
OUNTER
R
EGISTERS
___________ 40
10.
INTERRUPT CONTROLLER______________ 41
10.1
I
NTERRUPT
C
ONTROL
R
EGISTERS
_____________ 42
11.
SUPPLY VOLTAGE LEVEL DETECTOR ____ 43
11.1
SVLD
R
EGISTER
_________________________ 43
12.
STROBE OUTPUT______________________ 44
12.1
S
TROBE
R
EGISTER
_______________________ 44
13.
RAM _________________________________ 45
14.
LCD DRIVER __________________________ 46
14.1
LCD
C
ONTROL
__________________________ 47
14.2
LCD
A
DDRESSING
________________________ 47
14.3
F
REE
S
EGMENT
A
LLOCATION
________________ 48
14.4
LCD
R
EGISTERS
_________________________ 48
15.
PERIPHERAL MEMORY MAP ____________ 50
16.
OPTION REGISTER MEMORY MAP _______ 54
17.
ACTIVE SUPPLY CURRENT TEST ________ 55
18.
MASK OPTIONS _______________________ 56
18.1
I
NPUT
/
O
UTPUT
P
ORTS
____________________ 56
18.1.1
Port A Metal Options ________________ 56
18.1.2
Port A Metal Options ________________ 56
18.1.3
Port B Metal Options ________________ 57
18.1.4
Port SP Metal Options _______________ 58
18.1.5
Voltage Regulator Option _____________ 59
18.1.6
Debouncer Frequency Option _________ 59
18.1.7
User defined LCD Segment Allocation __ 59
19.
TEMP. AND VOLTAGE BEHAVIORS _______ 60
19.1
IDD
C
URRENT
(T
YPICAL
) ___________________ 60
19.2
P
ULL
-
DOWN
R
ESISTANCE
(T
YPICAL
) ___________ 60
19.3
O
UTPUT
C
URRENTS
(T
YPICAL
) _______________ 61
20.
ELECTRICAL SPECIFICATION ___________ 62
20.1
A
BSOLUTE
M
AXIMUM
R
ATINGS
_______________ 62
20.2
H
ANDLING
P
ROCEDURES
___________________ 62
20.3
S
TANDARD
O
PERATING
C
ONDITIONS
___________ 62
20.4
DC
C
HARACTERISTICS
-
P
OWER
S
UPPLY
_______ 62
20.5
S
UPPLY
V
OLTAGE
L
EVEL
D
ETECTOR
___________ 63
20.6
O
SCILLATOR
____________________________ 63
20.7
DC
CHARACTERISTICS
-
I/O
P
INS
_____________ 64
20.8
LCD
SEG[20:1]
O
UTPUTS
_________________ 65
20.9
LCD
C
OM
[4:1]
O
UTPUTS
___________________ 65
20.10
DC
O
UTPUT
C
OMPONENT
________________ 65
20.11
LCD
V
OLTAGE
M
ULTIPLIER
_______________ 65
21.
DIE, PAD LOCATION AND SIZE___________ 66
22.
TQF52 PACKAGE DIMENSIONS __________ 67
23.
ORDERING INFORMATION ______________ 68
23.1
P
ACKAGED DEVICES
______________________ 68
23.2
DIE
F
ORM
_____________________________ 68
24.
SPEC UPDATEERROR! BOOKMARK NOT DEFINED.
R
EM6821
Copyright
2005, EM Microelectronic-Marin SA
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1. Pin Description for EM6821
Chip TQFP
52
DIL
64
Signal Name
Function
Remarks
1
1
10
VL1
Voltage multiplier level 1
LCD level 1 input, if external
supply selected
2
2
11
VL2
Voltage multiplier level 2
LCD level 2 input, if external
supply selected
3
3
12
VL3
Voltage multiplier level 3
LCD level 3 input, if external
supply selected
4
4
13
COM[1]
LCD back plane 1
5
5
14
COM[2]
LCD back plane 2
6
6
15
COM[3]
LCD back plane 3
7
7
16
COM[4]
LCD back plane 4
Not used if 3 times multiplexed
8
8
18
SEG[20]
LCD Segment 20
9
9
19
SEG[19]
LCD Segment 19
10
10
20
SEG[18]
LCD Segment 18
11
11
21
SEG[17]
LCD Segment 17
12
12
22
SEG[16]
LCD Segment 16
13
13
23
SEG[15]
LCD Segment 15
14
14
26
SEG[14]
LCD Segment 14
15
15
27
SEG[13]
LCD Segment 13
16
16
28
SEG[12]
LCD Segment 12
17
17
29
SEG[11]
LCD Segment 11
18
18
30
SEG[10]
LCD Segment 10
19
19
31
SEG[9]
LCD Segment 9
20
20
33
SEG[8]
LCD Segment 8
21
21
34
SEG[7]
LCD Segment 7
22
22
35
SEG[6]
LCD Segment 6
23
23
36
SEG[5]
LCD Segment 5
24
24
37
SEG[4]
LCD Segment 4
25
25
38
SEG[3]
LCD Segment 3
26
26
39
SEG[2]
LCD Segment 2
27
27
42
SEG[1]
LCD Segment 1
28
28
43
Reset
Input reset terminal,
internal pull-down 15 KOhm
Main reset
29
29
44
Test
Input test terminal,
internal pull-down 15 KOhm
For EM tests only, ground 0 !
Except when needed for MFP
programming
30
30
45
PSP[0]
Input/output , open drain
serial port : SIN
parallel out terminal 0
Serial interface data in
or
parallel data[0] in/out
31
31
46
PSP[1]
Output , open drain
serial port : Ready/CS
parallel out terminal 1
Serial interface Ready CS
or
parallel data[1] in/out
32
32
47
PSP[2]
Output , open drain
serial port : SOUT
parallel out terminal 2
Serial interface data out
or
parallel data[2] in/out
33
33
49
PSP[3]
Input/output , open drain
serial port : SCLK
parallel out terminal 3
Serial interface clock I/O
or
parallel data[3] in/out
34
34
50
PB[0]
Input/output, open drain
port B terminal 0
Port B data[0] I/O or
Ck[1] output
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EM6821
Copyright
2005, EM Microelectronic-Marin SA
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Chip TQFP
52
DIL
64
Signal Name
Function
Remarks
35
35
51
PB[1]
Input/output, open drain
port B terminal 1
Port B data[1] I/O or
Ck[11] output
36
36
52
PB[2]
Input/output, open drain
port B terminal 2
Port B data[2] I/O or
Ck[16] output
37
37
53
PB[3]
Input/output, open drain
port B terminal 3
Port B data[3] I/O or
PWM output
38
38
54
PA[0]
Input port A terminal 0
TestVar 1
Event counter
39
39
55
PA[1]
Input port A terminal 1
TestVar 2
40
40
58
PA[2]
Input port A terminal 2
TestVar 3
41
41
59
PA[3]
Input port A terminal 3
Event counter,
MSC start/stop control
42
42
60
Buzzer
Output Buzzer terminal
43
43
61
Strobe
Output Strobe terminal
P reset state or/and port B
write or sleep flag out
44
44
62
Vbat = V
DD
Positive power supply
MFP Connection
45
45
63
Vreg
Internal voltage regulator
Connect to minimum 100nF,
MFP connection
46
46
64
Qin/Osc1
Crystal terminal 1
32 KHz crystal, MFP connection
47
47
2
Qout /Osc2
Crystal terminal 2
32 KHz crystal, MFP connection
48 48 3
V
SS
Negative power supply
ref. terminal, MFP connection
49
49
4
C2B
Voltage multiplier
Not needed if ext. supply
50
50
5
C2A
Voltage multiplier
Not needed if ext. supply
51
51
6
C1B
Voltage multiplier
Not needed if ext. supply
52
52
7
C1A
Voltage multiplier
Not needed if ext. supply
Gray shaded areas : Terminals needed for MFP programming connections (V
DD
, Vreg, Qin, Qout, Test).
Figure 3. Typical Configuration
C rystal
L C D D is play
C 1
C 1
C 1
C 4
C 3
V re g
V
S S
T e st
R e set
V
D D
(V b a t)
S E G [20 :1 ]
Q in O o u t
C 2
C 2
C 1A
C 1B
C 2A
C 2B
C O M [4 :1 ]
V L1
V L2
V L3
E M 6 8 2 1
A ll C apacitors 100 nF
P o rt A
S tro b e
B u zze r
P ort B
P ort S P
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