R
V6116
Copyright
2005, EM Microelectronic-Marin SA
1
www.emmicroelectronic.com
Digitally Programmable 2, 4 and 8 Mux LCD Driver
Description
The V6116 is a universal low multiplex LCD driver. The 2,
4 and 8 way multiplex is digitally programmable by the
command byte. The display refresh is handled on chip via
2 selectable 8 x 40 RAMs which holds the LCD content
driven by the driver. LCD pixels (or segments) are
addressed on a one to one basis with the 8 x 40 bit RAM
(a set bit corresponds to an activated LCD pixel). Due to
the very low driver impedance, the V6116 is designed to
be proved in large pixel size applications. Using the TAB
tools, the V6116 can be easily cascaded and it can be
provided in very large display applications by using the
column only driver command COL . The very low current
consumption, the extremely large voltage range and the
extremely wide temperature range give the V6116 a real
advantage for a wide range of applications.
Versions
V6116 060 with internal bias resistor
V6116 020 without internal bias resistor
When using the version 020 (without internal bias
resistor) in mux mode 4, V3 has to be connected to
V
SS
Features
V6116 mux mode 2 with 2 rows and 38 columns
V6116 mux mode 4 with 4 rows and 36 columns
V6116 mux mode 8 with 8 rows and 32 columns
Low dynamic current, 250 A max.
Low standby current, 1 A max. at +25C
Voltage bias and mux signal generation on chip
2 display RAMs addressable as 8 x 40 words
Display refresh on chip, dual RAM for display storage:
2 x (2x38; 4x36; 8x32)
Column driver only mode to have 40 column outputs
Dual RAM for display storage: 2x (2; 4; 8x40)
Crossfree cascadable for large LCD applications
Separate logic and LCD supply voltage pins
Wide power supply range: V
DD
: 2 to 6V, V
LCD
: 2 to 9V
Blank function for LCD blanking by data, BLANK bit
and STR signal (STR only if internal bias)
All segments ON by data and SET bit
Bit mapped
Serial interface
No busy state
LCD updating synchronized to the LCD refresh signal
TAB and bumped die form delivery. Other form
delivery on request
-40 to + 85 C temperature range
Typical Operating Configuration
Fig. 1
Pad Assignment
QFP52
See Fig. 16 for TAB pinout
Fig. 2
EM MICROELECTRONIC -
MARIN SA
R
V6116
Copyright
2005, EM Microelectronic-Marin SA
2
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Absolute Maximum Ratings
Parameter Symbol
Conditions
Supply voltage range
V
DD
-0.3V to 9V
LCD supply voltage range
V
LCD
-0.3V to 9.5V
Voltage at DI, DO, CLK, STR,
FR, COL
V
LOGIC
-0.3V to
V
DD
+0.3V
Voltage at V1 to V3, S1 to S40
V
DISP
-0.3V to V
LCD
+
0.3V
Storage temperature range
T
STO
-65 to +150C
Electrostatic discharge max. to
MIL-STD-883C method 3015.7
with ref. to V
SS
V
Smax
1000V
Maximum soldering conditions
T
Smax
290C x 10s
Table 1
Stresses above these listed maximum ratings may cause
permanent damages to the device. Exposure beyond
specified operating conditions may affect device reliability
or cause malfunction.
Handling Procedures
This device has built-in protection against high static
voltages or electric fields; however, anti-static precautions
must be taken as for any other CMOS component. Unless
otherwise specified, proper operation can only occur when
all terminal voltages are kept within the voltage range.
Unused inputs must always be tied to a defined logic
voltage level.
Operating Conditions
Parameter Symbol
Min
Typ
Max
Unit
Operating
Temperature
T
A
-40 +85
C
Logic supply voltage
V
DD
2 5 6 V
LCD supply voltage
V
LCD
2 5 9 V
Table 2
Electrical Characteristics
V
DD
= 5V 10%, V
LCD
= 2 to 7V and T
A
= -40 to +85C, unless otherwise specified
Parameter Symbol
Test
Conditions
Min.
Typ.
Max.
Units
Dynamic supply current
I
LCD
See
note
1
150 250
A
Dynamic supply current
I
DD
See note 1 at T
A
= 25C
0.1
1
A
Dynamic supply current
I
DD
See
note
1
3 12
A
Dynamic supply current
I
DD
See
note
2
200 250
A
Standby supply current
I
SS
See note 3 at T
A
= 25C
0.1
1
A
Control Signals DI, CLK, STR, FR
and COL
Input leakage
I
IN
0 < V
IN
< V
DD
1
1000
nA
Input capacitance
C
IN
at
T
A
= 25C
8
pF
Low level input voltage
V
IL
0 0.8 V
High level input voltage for DI, STR,
FR and COL
V
IH
2.0 V
DD
V
High level input voltage for CLK
V
IH
3.0 V
DD
V
Data Output DO
High level output voltage
V
OH
I
H
= 4 mA
2.4
V
Low level output voltage
V
OL
I
L
= 4 mA
0.4
V
Driver Outputs S1 ... S40
Driver impedance (note 4)
R
OUT
I
OUT
= 10A, V
LCD
= 7V
1.0
1.5
k
Driver impedance (note 4)
R
OUT
I
OUT
= 10A, V
LCD
= 3V
2.6
3.5
k
Driver impedance (note 4)
R
OUT
I
OUT
= 10A, V
LCD
= 2V
7
k
Bias impedance V1, V2, V3 (note 5)
R
BIAS
I
OUT
= 10A, V
LCD
= 7V
18
24
k
Bias impedance V1, V2, V3 (note 5)
R
BIAS
I
OUT
= 10A, V
LCD
= 3V
20
27
k
Bias impedance V1, V2, V3 (note 5)
R
BIAS
I
OUT
= 10A, V
LCD
= 2V
24
k
DC output component
VDC
see Tables 4a & 4b,
V
LCD
= 5V
30 50
mV
Table 3
Note 1
: All outputs open, STR at V
SS
, FR = 400 Hz, all other inputs at V
DD
.
Note 2
: All outputs open, STR at V
SS
, FR = 400 Hz, f
CLK
= 1 MHz, all other inputs at V
DD
.
Note 3
: All outputs open, all inputs at V
DD
.
Note 4
: This is the impedance between of the voltage bias level pins (V1, V2 or V3) and the output pins S1 to S40 when a
given voltage bias level is driving the outputs (S1 to S40)
Note 5
: This is the impedance seen at the segment pin. Outputs measured one at a time.
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V6116
Copyright
2005, EM Microelectronic-Marin SA
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Column Drivers
Outputs FR
Polarity COL
Column Data
Measured*
Guaranteed
S1 to S40
logic 1
logic 0
logic 1
Sx* - V
SS
S1 to S40
logic 0
logic 0
logic 1
V
LCD
- Sx*
V
LCD
- Sx* = Sx* - V
SS
25 mV
S1 to S40
logic 1
logic 0
logic 0
V
LCD
- Sx*
S1 to S40
logic 0
logic 0
logic 0
Sx* - V
SS
V
LCD
- Sx* = Sx* - V
SS
25 mV
Table 4a
*Sx = the output number (ie. S1 to S40)
Row Drivers
Outputs FR
Polarity COL
Column Data
Measured*
Guaranteed
S1 to Sn*
logic 1
logic 1
logic 1
V
LCD
- Sx
S1 to Sn*
logic 0
logic 1
logic 1
Sx - V
SS
V
LCD
- Sx = Sx - V
SS
25 mV
S1 to Sn*
logic 1
logic 1
logic 0
Sx - V
SS
S1 to Sn*
logic 0
logic
logic 0
V
LCD
- Sx
V
LCD
- Sx = Sx - V
SS
25 mV
Table 4b
*n = the V6116 mux programme number (ie. 2, 4 or 8)
Timing Characteristics
V
DD
= 5V 10%, V
LCD
= 2 to 7V and T
A
= -40 to +85C
Parameter Symbol
Test
Conditions
Min.
Typ.
Max.
Units
Clock high pulse width
t
CH
120
ns
Clock low pulse width
t
CL
120
ns
Clock and FR rise time
t
CR
200 ns
Clock and FR fall time
t
CF
200
ns
Data input setup time
t
DS
20 (note 1)
ns
Data input hold time
t
DH
30 (note 1)
ns
Data output propagation
t
PD
C
LOAD
= 50pF
100
ns
STR pulse width
t
STR
100
ns
CLK falling to STR rising
t
P
10
ns
STR falling to CLK falling
t
D
200
ns
FR frequency (2/4/8)
f
FR
(note 2) T
A
= 25C
128/256/512
Hz
Table 5a
Note 1
: t
DS
+ t
DH
minimum must be 100 ns. If t
DS
= 20 ns then t
DH
80ns.
Note 2
: V6116 n, FR = n times the desired LCD refresh rate where n is the V6116 mux mode number.
V
DD
= 2 to 6V, V
LCD
= 2 to 8V and T
A
= -40 to +85C
Parameter Symbol
Test
Conditions
Min.
Typ.
Max.
Units
Clock high pulse width
t
CH
500
ns
Clock low pulse width
t
CL
500
ns
Clock and FR rise time
t
CR
200
ns
Clock and FR fall time
t
CF
200
ns
Data input setup time
t
DS
100 (note 1)
ns
Data input hold time
t
DH
150 (note 1)
ns
Data output propagation
t
PD
C
LOAD
= 50pF
400
ns
STR pulse width
t
STR
500
ns
CLK falling to STR rising
t
P
10
ns
STR falling to CLK falling
t
D
1
s
FR frequency (2/4/8)
F
FR
(note 2)
128/256/512
Hz
Table 5b
Note 1
: t
DS
+ t
DH
minimum must be 500 ns. If t
DS
= 100 ns then t
DH
400ns.
Note 2
: V6116 n, FR = n times the desired LCD refresh rate where n is the V6116 mux mode number.
R
V6116
Copyright
2005, EM Microelectronic-Marin SA
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Timing Waveforms
Fig. 3
Programmation Data Bits
Command Bits 0 to 7
Mux Ratio (bit 0, 1)
0 1 2 3 4 5 6 7
0
1
Mux
Mode
0 0
2
Multiplex
Ratio
W RAM
Address
(see Fig. 5)
SET Blank
0 1
4
1 0
-
1 1
8
Bit 6: SET bit forces all column outputs ON
Bit 7: Blank bit forces all column outputs OFF
Bit 2: When "0", write RAM 1 and read RAM 2. When "0"
and RAM-Add = 0 and STR, write RAM 1 and read
RAM 1. When "1", write RAM 2 and read RAM1.
When "1" and RAM-Add = 0 and STR, write RAM 2
and read RAM 2.
Fig. 4
Data Transfer Cycle
V6116 as a row and column driver, 48 bit load cycle, RAM
selected address provided by command bits 3 to 5.
Command Bits 3 to 5
Display RAM 1 or 2
Mux
Mode 2
Mux
Mode 4
Mux
Mode 8
Address
LCD
Row
000
001
000
001
010
011
000
001
010
011
100
101
110
111
10000000
01000000
00100000
00010000
00001000
00000100
00000010
00000001
Row 1
Row 2
Row 3
Row 4
Row 5
Row 6
Row 7
Row 8
All mux mode programmations or COL states need
48 bit load cycle.
Fig. 5
R
V6116
Copyright
2005, EM Microelectronic-Marin SA
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Block Diagram
Note 1
: When falling edge of STR and RAM-Add = 0 and FR arrives, then the display selected RAM address
10000000 (which corresponds to row 1) has to be selected by the 8 bit sequencer. Cascaded V6116s
are synchronized in this way. The LCD picture restarts from row 1 each time full RAM data are written.
Fig. 6
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