This Data Sheet may be revised by subsequent versions 2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
1
EN25P20
Rev. A, Issue Date: 2006/03/24
FEATURES
Single power supply operation
- Full voltage range: 2.7-3.6 volt
2 Mbit Serial Flash
- 2 M-bit/256 K-byte/1024 pages
- 256 bytes per programmable page
High performance
- 50MHz clock rate
Low power consumption
- 5 mA typical active current
- 1
A typical power down current
Uniform Sector Architecture:
- Four 64-Kbyte sectors
Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
High performance program/erase speed
- Byte program time: 8s typical
- Sector erase time: 500ms typical
- Chip erase time: 2 Seconds
Minimum 100K endurance cycle
Package Options
- 8 pins SOP 150mil body width
- 8 contact VDFN
- All Pb-free packages are RoHS compliant
Commercial and industrial temperature
Range
GENERAL DESCRIPTION
The EN25P20 is a 2M-bit (256K-byte) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to
256 bytes at a time, using the Page Program instruction.
The EN25P20 is designed to allow either single Sector at a time or full chip erase operation. The
EN25P20 can be configured to protect part of the memory as the software protected mode. The
device can sustain a minimum of 100K program/erase cycles on each sector.
EN25P20
2 Mbit Uniform Sector, Serial Flash Memory
This Data Sheet may be revised by subsequent versions 2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
2
EN25P20
Rev. A, Issue Date: 2006/03/24
Figure.1 CONNECTION DIAGRAMS
Figure 2. BLOCK DIAGRAM
8 - LEAD SOP
8 - CONTACT VDFN
This Data Sheet may be revised by subsequent versions 2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
3
EN25P20
Rev. A, Issue Date: 2006/03/24
SIGNAL DESCRIPTION
Serial Data Input (DI)
The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be
serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK)
input pin.
Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from
(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device
is deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the
devices power consumption will be at standby levels unless an internal erase, program or status
register cycle is in progress. When CS# is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the
device. After power-up, CS# must transition from high to low before a new instruction will be
accepted.
Hold (HOLD#)
The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought
low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will
be ignored (don't care). The hold function can be useful when multiple devices are sharing the same
SPI signals.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used
in conjunction with the Status Register's Block Protect (BP0, BP1) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected.
Table 1. PIN Names
Symbol Pin
Name
CLK
Serial Clock Input
DI
Serial Data Input
DO
Serial Data Output
CS# Chip
Enable
WP# Write
Protect
HOLD# Hold
Input
Vcc
Supply Voltage (2.7-3.6V)
Vss Ground
This Data Sheet may be revised by subsequent versions 2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
4
EN25P20
Rev. A, Issue Date: 2006/03/24
MEMORY ORGANIZATION
The memory is organized as:
262,144
bytes
Uniform Sector Architecture
Four 64-Kbyte sectors
1024 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or
Bulk Erasable but not Page Erasable.
Table 2. Block Sector Architecture
Sector
SECTOR SIZE (KByte)
Address range
3
64 30000h
3FFFFh
2
64 20000h
2FFFFh
1
64 10000h
1FFFFh
0
64 00000h
0FFFFh
This Data Sheet may be revised by subsequent versions 2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
5
EN25P20
Rev. A, Issue Date: 2006/03/24
OPERATING FEATURES
SPI Modes
The EN25P20 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),
Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0
(0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in Figure
3, concerns the normal state of the SCK signal when the SPI bus master is in standby and data is not
being transferred to the Serial Flash. For Mode 0 the SCK signal is normally low. For Mode 3 the SCK
signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the SCK.
Data output on the DO pin is clocked out on the falling edge of SCK.
Figure 3. SPI Modes
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a
Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal
Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at
a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of
memory.
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the
bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time,
using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE)
instruction. This starts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be
preceded by a Write Enable (WREN) instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE)
can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress
(WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it
to establish when the previous Write cycle, Program cycle or Erase cycle is complete.
Active Power, Stand-by Power and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select
(CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles
have completed (Program, Erase, Write Status Register). The device then goes in to the Stand-by Power
mode. The device consumption drops to I
CC1
.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode
(DP) instruction) is executed. The device consumption drops further to I
CC2
. The device remains in this
mode until another specific instruction (the Release from Deep Power-down Mode and Read Device ID
(RDI) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as
an extra software protection mechanism, when the device is not in active use, to protect the device from
inadvertent Write, Program or Erase instructions.
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