4800 Great America Parkway, Suite 202
Tel: 408-235-8680
Santa
Clara,
CA
95054
Fax:
408-235-8685
1
EN29LV800
Rev 0.4 Release Date: 2002/04/16
da0.
FEATURES
Single power supply operation
- Full voltage range: 2.7-3.6 volt read and write
operations for battery-powered applications.
- Regulated voltage range: 3.0-3.6 volt read
and write operations and for compatibility with
high performance 3.3 volt microprocessors.
Manufactured on 0.28 m process technology
High performance
- Access times as fast as 70 ns
Low power consumption (typical values at 5
MHz)
- 7 mA typical active read current
- 15 mA typical program/erase current
- 1
A typical standby current (standard access
time to active mode)
Flexible Sector Architecture:
- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
- One 8 Kword, two 4 Kword, one 16 Kword
and fifteen 32 Kword sectors (word mode)
- Supports full chip erase
- Individual sector erase supported
- Sector protection:
Hardware locking of sectors to prevent
program or erase operations within individual
sectors
Additionally, temporary Sector Group
Unprotect allows code changes in previously
locked sectors.
High performance program/erase speed
- Byte/Word program time: 8s typical
- Sector erase time: 500ms typical
JEDEC Standard program and erase
commands
JEDEC standard DATA polling and toggle
bits feature
Single Sector and Chip Erase
Sector Unprotect Mode
Embedded Erase and Program Algorithms
Erase Suspend / Resume modes:
Read or program another Sector during
Erase Suspend Mode
0.28 m double-metal double-poly
triple-well CMOS Flash Technology
Low Vcc write inhibit < 2.5V
>100K program/erase endurance cycle
48-pin TSOP (Type 1)
Commercial Temperature Range
GENERAL DESCRIPTION
The EN29LV800 is an 8-Megabit, electrically erasable, read/write non-volatile flash memory,
organized as 1,048,576 bytes or 524,288 words. Any byte can be programmed typically in 10s.
The EN29LV800 features 3.0V voltage read and write operation, with access times as fast as 55ns to
eliminate the need for WAIT states in high-performance microprocessor systems.
The EN29LV800 has separate Output Enable ( OE ), Chip Enable (
CE
), and Write Enable (WE)
controls, which eliminate bus contention issues. This device is designed to allow either single
Sector
or full chip erase operation, where each Sector can be individually protected against program/erase
operations or temporarily unprotected to erase or program. The device can sustain a minimum of
100K program/erase cycles on each Sector.
EN29LV800
8 Megabit (1024K x 8-bit / 512K x 16-bit) Flash Memory
Boot Sector Flash Memory, CMOS 3.0 Volt-only
4800 Great America Parkway, Suite 202
Tel: 408-235-8680
Santa
Clara,
CA
95054
Fax:
408-235-8685
2
EN29LV800
Rev 0.4 Release Date: 2002/04/16
CONNECTION DIAGRAMS
TABLE 1. PIN DESCRIPTION
FIGURE 1. LOGIC DIAGRAM
Pin Name
Function
A0-A18 Addresses
DQ0-DQ14
15 Data Inputs/Outputs
DQ15 / A-1
DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
CE# Chip
Enable
OE# Output
Enable
RESET#
Hardware Reset Pin
RY/BY# Ready/Busy
Output
WE# Write
Enable
Vcc
Supply Voltage
(2.7-3.6V)
Vss Ground
NC
Not Connected to anything
BYTE# Byte/Word
Mode
EN29LV800
DQ0 DQ15
(A-1)
A0 - A18
WE
CE
OE
RY/BY
Reset
Byte
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Standard
TSOP
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE#
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
CE#
A0
4800 Great America Parkway, Suite 202
Tel: 408-235-8680
Santa
Clara,
CA
95054
Fax:
408-235-8685
3
EN29LV800
Rev 0.4 Release Date: 2002/04/16
TABLE 2A. TOP BOOT BLOCK SECTOR ARCHITECTURE
ADDRESS RANGE
Sect
or
(X16) (X8)
SECTOR
SIZE
(Kbytes /
Kwords)
A18 A17 A16 A15 A14 A13 A12
18 7E000h-7FFFFh
FC000h-FFFFFh 16/8 1 1 1 1 1 1 X
17 7D000h-7DFFFh
FA000h-FBFFFh 8/4 1 1 1 1 1 0 1
16 7C000h-7CFFFh
F8000h-F9FFFh 8/4 1 1 1 1 1 0 0
15 78000h-7BFFFh
F0000h
F7FFFh 32/16 1 1 1 1 0 X X
14
70000h-77FFFh
E0000h - EFFFFh
64/32
1
1
1
0
X
X
X
13
68000h-6FFFFh
D0000h - DFFFFh
64/32
1
1
0
1
X
X
X
12
60000h-6FFFFh
C0000h - CFFFFh
64/32
1
1
0
0
X
X
X
11
58000h-5FFFFh
B0000h - BFFFFh
64/32
1
0
1
1
X
X
X
10
50000h-57FFFh
A0000h - AFFFFh
64/32
1
0
1
0
X
X
X
9
48000h-4FFFFh
90000h - 9FFFFh
64/32
1
0
0
1
X
X
X
8
40000h-47FFFh
80000h - 8FFFFh
64/32
1
0
0
0
X
X
X
7
38000h-3FFFFh
70000h - 7FFFFh
64/32
0
1
1
1
X
X
X
6
30000h-37FFFh
60000h - 6FFFFh
64/32
0
1
1
0
X
X
X
5
28000h-2FFFFh
50000h 5FFFFh
64/32
0
1
0
1
X
X
X
4
20000h-27FFFh
40000h 4FFFFh
64/32
0
1
0
0
X
X
X
3
18000h-1FFFFh
30000h 3FFFFh
64/32
0
0
1
1
X
X
X
2
10000h-17FFFh
20000h - 2FFFFh
64/32
0
0
1
0
X
X
X
1
08000h-0FFFFh
10000h - 1FFFFh
64/32
0
0
0
1
X
X
X
0
00000h-07FFFh
00000h - 0FFFFh
64/32
0
0
0
0
X
X
X
4800 Great America Parkway, Suite 202
Tel: 408-235-8680
Santa
Clara,
CA
95054
Fax:
408-235-8685
4
EN29LV800
Rev 0.4 Release Date: 2002/04/16
TABLE 2B. BOTTOM BOOT BLOCK SECTOR ARCHITECTURE
ADDRESS RANGE
Sect
or
(X16) (X8)
SECTOR
SIZE
(Kbytes/
Kwords)
A18 A17 A16 A15 A14 A13 A12
18 78000h-7FFFFh F0000h
FFFFFh 64/32 1 1 1 1 X X X
17 70000h-77FFFh
E0000h
EFFFFh 64/32 1 1 1 0 X X X
16 68000h-6FFFFh
D0000h
DFFFFh 64/32 1 1 0 1 X X X
15 60000h-67FFFh
C0000h
CFFFFh 64/32 1 1 0 0 X X X
14 58000h-5FFFFh B0000h
-
BFFFFh 64/32 1 0 1 1 X X X
13 50000h-57FFFh A0000h
-
AFFFFh 64/32 1 0 1 0 X X X
12 48000h-4FFFFh 90000h
9FFFFh 64/32 1 0 0 1 X X X
11 40000h-47FFFh 80000h
8FFFFh 64/32 1 0 0 0 X X X
10 38000h-3FFFFh 70000h
7FFFFh 64/32 0 1 1 1 X X X
9 30000h-37FFFh 60000h
6FFFFh 64/32 0 1 1 0 X X X
8 28000h-2FFFFh 50000h
5FFFFh 64/32 0 1 0 1 X X X
7 20000h-27FFFh 40000h
4FFFFh 64/32 0 1 0 0 X X X
6 18000h-1FFFFh 30000h
3FFFFh 64/32 0 0 1 1 X X X
5 10000h-17FFFh 20000h
2FFFFh 64/32 0 0 1 0 X X X
4 08000h-0FFFFh 10000h
1FFFFh 64/32 0 0 0 1 X X X
3 04000h-07FFFh 08000h
0FFFFh 32/16 0 0 0 0 1 X X
2 03000h-03FFFh 06000h
07FFFh 8/4 0 0 0 0 0 1 1
1 02000h-02FFFh 04000h
05FFFh 8/4 0 0 0 0 0 1 0
0 00000h-01FFFh 00000h
01FFFh 16/8 0 0 0 0 0 0 X
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