New configuration of product number
Starting April 1, 2001, the configuration of product number descriptions will be changed as listed
below. To order from April 1, 2001 please use these product numbers. For further information, please
contact Epson sales representative.
Devices
S1
C
88104
F
0A01
Packing specification
Package (D: die form; F: QFP)
Model number
Model name (C: microcomputer, digital products)
Product classification (S1: semiconductor)
Development tools
S5U1
C
88348
D1
1
Packing specification
Version (1: Version 1)
Tool type (D1: Development Tool)
Corresponding model number (88348: for S1C88348)
Tool classification (C: microcomputer use)
Product classification
(S5U1: development tool for semiconductor products)
00
00
S1C88349 TECHNICAL MANUAL
EPSON
i
CONTENTS
Contents
1
INTRODUCTION .............................................................................................. 1
1.1
Features ............................................................................................................................. 1
1.2
Block Diagram ................................................................................................................... 2
1.3
Pin Layout Diagram .......................................................................................................... 3
1.4
Pin Description .................................................................................................................. 4
1.5
Mask Option ....................................................................................................................... 5
2
POWER SUPPLY ............................................................................................... 8
2.1
Operating Voltage .............................................................................................................. 8
2.2
Internal Power Supply Circuit ........................................................................................... 8
3
CPU AND BUS CONFIGURATION ................................................................ 9
3.1
CPU ...................................................................................................................................9
3.2
Internal Memory ................................................................................................................ 9
3.2.1 ROM ......................................................................................................................................... 9
3.2.2 RAM .......................................................................................................................................... 9
3.2.3 I/O memory ............................................................................................................................... 9
3.2.4 Display memory ........................................................................................................................ 9
3.3
Exception Processing Vectors ........................................................................................... 9
3.4
CC (Customized Condition Flag) ..................................................................................... 10
3.5
Chip Mode ......................................................................................................................... 10
3.5.1 MCU mode and MPU mode .................................................................................................... 10
3.5.2 Bus mode ................................................................................................................................. 11
3.6
External Bus ......................................................................................................................13
3.6.1 Data bus .................................................................................................................................. 13
3.6.2 Address bus ............................................................................................................................. 13
3.6.3 Read (RD)/write (WR) signals ................................................................................................. 13
3.6.4 Chip enable (CE) signal .......................................................................................................... 14
3.6.5 WAIT control ........................................................................................................................... 15
3.6.6 Bus authority release state ...................................................................................................... 16
4
INITIAL RESET ............................................................................................... 17
4.1
Initial Reset Factors ..........................................................................................................17
4.1.1 RESET terminal ....................................................................................................................... 17
4.1.2 Simultaneous LOW level input at input port terminals K00K03 ........................................... 17
4.1.3 Supply voltage detection (SVD) circuit ................................................................................... 18
4.1.4 Initial reset sequence ............................................................................................................... 18
4.2
Initial Settings After Initial Reset ...................................................................................... 19
5
PERIPHERAL CIRCUITS AND THEIR OPERATION ................................ 20
5.1
I/O Memory Map .............................................................................................................. 20
5.2
System Controller and Bus Control ..................................................................................33
5.2.1 Bus mode settings .................................................................................................................... 33
5.2.2 Address decoder (CE output) settings ..................................................................................... 35
5.2.3 WAIT state settings .................................................................................................................. 36
5.2.4 Setting the bus authority release request signal ...................................................................... 36
5.2.5 Stack page setting .................................................................................................................... 36
5.2.6 Control of system controller .................................................................................................... 37
5.2.7 Programming notes ................................................................................................................. 40