Document Outline

• S1D13503 TECHNICAL MANUAL
  • Customer Support Information
    • Comprehensive Support Tools
    • Evaluation / Demonstration Board
    • VGA Chip Documentation
    • Software
    • Application Engineering Support
    • Table of Contents
• S1D13503 Graphics LCD Controller
  • Description
  • Features
    • CPU Interface
    • Memory Interface
    • Display Modes
    • Display Support
    • Clock Source
    • Power Down Modes
    • Package
  • System Block Diagram
• Hardware Functional Specification
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 INTRODUCTION
    • 1.1 Scope
    • 1.2 Overview Description
  • 2 FEATURES
    • 2.1 Technology
    • 2.2 System
    • 2.3 Display Modes
    • 2.4 Display Support
    • 2.5 Power Management
  • 3 TYPICAL SYSTEM BLOCK DIAGRAMS
    • 3.1 16-Bit MC68000 MPU
      • Figure 1: 16-Bit 68000 Series (example implementation only - actual may vary)
    • 3.2 MPU with READY (or WAIT#) signal
      • Figure 2: 8-Bit Mode, Example: Z80 (example implementation only - actual may vary)
      • Figure 3: 16-Bit Mode, Example: i8086 (maximum mode) (example implementation only - actual may vary)
    • 3.3 ISA Bus
      • Figure 4: 8-Bit Mode (ISA) (example implementation only - actual may vary)
      • Figure 5: 16-Bit Mode (ISA) (example implementation only - actual may vary)
    • 3.4 Internal Block Diagram
      • Figure 6: Internal Block Diagram
    • 3.5 Functional Block Descriptions
      • 3.5.1 Bus Signal Translation
      • 3.5.2 Control Registers
      • 3.5.3 Sequence Controller
      • 3.5.4 LCD Panel Interface
      • 3.5.5 Look-Up Table
      • 3.5.6 Port Decoder
      • 3.5.7 Memory Decoder
      • 3.5.8 Data Bus Conversion
      • 3.5.9 Address Generator
      • 3.5.10 MPU / CRT Selector
      • 3.5.11 Display Data Formatter
      • 3.5.12 Clock Inputs / Timing
      • 3.5.13 SRAM Interface
  • 4 PINOUT DIAGRAM
    • Figure 7: S1D13503F00A Pinout Diagram
    • Figure 8: S1D13503F01A Pinout Diagram
    • Figure 9: S1D13503D00A Pad Diagram
    • Table 41: PAD Coordinates
  • 5 PIN DESCRIPTION
    • 5.1 Description
      • Table 51: Bus Interface
      • Table 52: Display Memory Interface
      • Table 53: LCD Interface
      • Table 54: Clock Inputs
      • Table 55: Power Supply
    • 5.2 Summary of Configuration Options
      • Table 56: Summary of Power On / Reset Options
      • Table 57: I/O and Memory Addressing Example
  • 6 D.C. CHARACTERISTICS
    • Table 61: Absolute Maximum Ratings
    • Table 62: Recommended Operating Conditions
    • Table 63: Input Specifications 
    • Table 64: Output Specifications
  • 7 A.C. CHARACTERISTICS
    • 7.1 Bus Interface Timing
      • 7.1.1 MC68000 Interface Timing
        • IOW# Timing
          • Figure 10: IOW# Timing (MC68000)
          • Table 71: IOW# Timing (MC68000)
        • IOR# Timing
          • Figure 11: IOR# Timing (MC68000)
          • Table 72: IOR# Timing (MC68000)
        • MEMW# Timing
          • Figure 12: MEMW# Timing (MC68000)
          • Table 73: MEMW# Timing (MC68000)
        • MEMR# Timing
          • Figure 13: MEMR# Timing (MC68000)
          • Table 74: MEMR# Timing (MC68000)
      • 7.1.2 Non-MC68000, MPU/Bus With READY (or WAIT#) Signal
        • IOW# Timing
          • Figure 14: IOW# Timing (Non-MC68000)
          • Table 75: IOW# Timing (Non-MC68000)
        • IOR# Timing
          • Figure 15: IOR# Timing (Non-MC68000)
          • Table 76: IOR# Timing (Non-MC68000)
        • MEMW# Timing
          • Figure 16: MEMW# Timing (Non-MC68000)
          • Table 77: MEMW# Timing (Non-MC68000)
        • MEMR# Timing
          • Figure 17: MEMR# Timing (Non-MC68000)
          • Table 78: MEMR# Timing (Non-MC68000)
    • 7.2 Clock Input Requirements
      • Figure 18: Clock Input Requirements
      • Table 79: Clock Input Requirements
      • 7.2.1 Recommended Clock Input
        • Figure 19: Recommended Clock Interface
    • 7.3 Display Memory Interface Timing
      • 7.3.1 Write Data to Display Memory
        • Figure 20: Write Data to Display Memory
        • Table 710: Write Data to Display Memory
      • 7.3.2 Read Data From Display Memory
        • Figure 21: Read Data From Display Memory
        • Table 711: Read Data From Display Memory
    • 7.4 LCD Interface
      • 7.4.1 LCD Interface Timing - 4-Bit Single, 8-Bit Single/Dual Monochrome Panels
        • Figure 22: LCD Interface Timing - Monochrome Panel
        • Table 712: LCD Interface Timing - 4-Bit Single and 8-Bit Single/Dual Monochrome Panel
      • 7.4.2 LCD Interface Timing - 4-Bit Single Color Panel
        • Figure 23: LCD Interface Timing - 4-Bit Single Color Panel
        • Table 713: LCD Interface Timing - 4-Bit Single Color Panel
      • 7.4.3 LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels
        • Figure 24: LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels
        • Table 714: LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels
      • 7.4.4 LCD Interface Timing - 16-Bit Single/Dual Color Panels
        • Figure 25: LCD Interface Timing - 16-Bit Single/Dual Color Panels
        • Table 715: LCD Interface Timing - 16-Bit Single/Dual Color Panels
      • 7.4.5 LCD Interface Timing - 8-Bit Single Color Panels Format 1
        • Figure 26: LCD Interface Timing - 8-Bit Single Color Panels Format 1
        • Table 716: LCD Interface Timing - 8-Bit Single Color Panels Format 1
      • 7.4.6 LCD Interface Options
        • Figure 27: 4-Bit Single Monochrome Panel Timing
        • Figure 28: 8-Bit Single Monochrome Panel Timing
        • Figure 29: 8-Bit Dual Monochrome Panel Timing
        • Figure 30: 4-Bit Single Color Panel Timing
        • Figure 31: 8-Bit Single Color Panel Timing - Format 1 : AUX[03] Bit 3 = 0 and AUX[01] Bit 2 = 1
        • Figure 32: 8-Bit Single Color Panel Timing - Format 2 : AUX[03] Bit 3 = 1 and AUX[01] Bit 2 = 1
        • Figure 33: 8-Bit Dual Color Panel Timing
        • Figure 34: External Circuit Required for 16-Bit Panel
        • Figure 35: 16-Bit Single Color Panel Timing with External Circuit
        • Figure 36: 16-Bit Dual Color Panel Timing with External Circuit
  • 8 HARDWARE REGISTER INTERFACE
    • 8.1 Register Descriptions
      • Table 81: Gray Shade/Color Mode Selection
      • Table 82: LCD Data Width
      • Table 83: Maximum Value of Line Byte Count Register - 8-Bit Display Memory Interface
      • Table 84: Maximum Value of Line Byte Count Register - 16-Bit Display Memory Interface
      • Table 85: Power Save Mode Selection
      • Table 86: ID Bit Usage
      • Table 87: Look-Up Table Access
    • 8.2 Look-Up Table Architecture
      • Table 88: Look-Up Table Configurations
      • 8.2.1 Gray Shade Display Modes
        • 4-Level Gray Shade Mode
          • Figure 37: 4-Level Gray-Shade Mode Look-Up Table Architecture
        • 16-Level Gray Shade Mode
          • Figure 38: 16-Level Gray-Shade Mode Look-Up Table Architecture
      • 8.2.2 Color Display Modes
        • 4-Level Color Mode
          • Figure 39: 4-Level Color Mode Look-Up Table Architecture
        • 16-Level Color Mode
          • Figure 40: 16-Level Color Mode Look-Up Table Architecture
        • 256-Level Color Mode
          • Figure 41: 256-Level Color Mode Look-Up Table Architecture
    • 8.3 Power Save Modes
      • Table 89: Power Save Mode Selection
      • 8.3.1 Power Save Mode 1
      • 8.3.2 Power Save Mode 2
      • 8.3.3 Power Save Mode Function Summary
        • Table 810: Power Save Mode Function Summary
      • 8.3.4 Pin States in Power Save Modes
        • Table 811: Pin States in Power Save Modes
  • 9 DISPLAY MEMORY INTERFACE
    • 9.1 SRAM Configurations Supported
      • 9.1.1 8-Bit Mode
        • Figure 42: 8-Bit Mode - 8K bytes SRAM
        • Figure 43: 8-Bit Mode - 16K bytes SRAM (Requires AUX[01] bit 0 = 0)
        • Figure 44: 8-Bit Mode - 32K bytes SRAM (Requires AUX[01] bit 0 = 1)
        • Figure 45: 8-Bit Mode - 40K bytes SRAM [either (8Kx8 + 32Kx8) requiring AUX[01] bit 0 = 0 or (32K...
        • Figure 46: 8-Bit Mode - 64K bytes SRAM (Requires AUX[01] bit 0 = 1)
      • 9.1.2 16-bit Mode
        • Figure 47: 16-Bit Mode - 16K bytes SRAM
        • Figure 48: 16-Bit Mode - 64K bytes SRAM
        • Figure 49: 16-Bit Mode - 128K bytes SRAM
    • 9.2 SRAM Access Time
      • 9.2.1 8-bit Display Memory Interface:
        • Table 91: 8-Bit Display Memory Interface SRAM Access Time
      • 9.2.2 16-bit Display Memory Interface:
        • Table 92: 16-Bit Display Memory Interface SRAM Access Time
    • 9.3 Frame Rate Calculation
      • 9.3.1 For single panel
      • 9.3.2 For dual panel
    • 9.4 Memory Size Calculation
    • 9.5 Memory Size Requirement
      • Table 93: Memory Size Requirement: Number of Horizontal Pixels = 640
      • Table 94: Memory Size Requirement: Number of Horizontal Pixels = 480
      • Table 95: Memory Size Requirement: Number of Horizontal Pixels = 320
  • 10 MECHANICAL DATA
    • Figure 50: Mechanical Drawing QFP5-100-S2 (S1D13503F00A)
    • Figure 51: Mechanical Drawing QFP15-100-STD (S1D13503F01A)
• Programming Notes and Examples
  • TABLE OF CONTENTS
  • LIST OF TABLES
  • LIST OF FIGURES
  • 1 INTRODUCTION
  • 2 INITIALIZING THE S1D13503
  • 3 GRAY SHADES / COLORS AND LOOK-UP TABLES
    • 3.1 Pixels
      • Table 31: Number Of Bits As Related To Colors
      • 3.1.1 Memory Organization for One Bit Pixel (Black-and-White)
        • Figure 1: Pixel Storage For 1 Bit (Black-and-White) In One Byte Of Display Memory
      • 3.1.2 Memory Organization for Two Bit Pixels (4 Colors/Gray Shades)
        • Figure 2: Pixel Storage For 2 Bits (4 Colors/Gray Shades) In One Byte Of Display Memory
      • 3.1.3 Memory Organization for Four Bit Pixels (16 Colors/Gray Shades)
        • Figure 3: Pixel Storage For 4 Bits (16 Colors/gray Shades) In One Byte Of Display Memory
      • 3.1.4 Memory Organization for Eight Bit Pixels (256 Colors)
        • Figure 4: Pixel Storage For 8 Bits (256 Colors) In One Byte Of Display Memory
    • 3.2 Look-Up Table (LUT)
      • 3.2.1 LUT Registers
        • Table 32: ID Bit Usage
        • Table 33: Look-Up Table Access
      • 3.2.2 Look-Up Table Description
        • Table 34: Look-Up Table Configurations
        • 3.2.2.1 Color Mode
        • 3.2.2.2 Monochrome Mode
          • Table 35: S1D13503 Color Look-up Table For 256 Color Mode
          • Table 36: S1D13503 Black-To-White Look-Up Table
          • Table 37: S1D13503 Inverted Look-Up Table (White-To-Black)
      • 3.2.3 Black-and-White (One Bit/Pixel)
      • 3.2.4 Four Gray Shades (Two Bits/Pixel in Monochrome Mode)
        • Table 38: S1D13503 Black-To-White Look-up Table For 4 Gray Shades
        • Figure 5: 4-Level Gray-Shade Mode Look-Up Table Architecture
      • 3.2.5 Four Colors (Two Bits/Pixel in Color Mode)
        • Table 39: S1D13503 Low To High Intensity Color Look-Up Table For 4 Colors
        • Figure 6: 4-Level Color Mode Look-Up Table Architecture
      • 3.2.6 Sixteen Gray Shades (Four Bits/Pixel in Monochrome Mode)
        • Figure 7: 16-Level Gray-Shade Mode Look-Up Table Architecture
      • 3.2.7 Sixteen Colors (Four Bits/Pixel in Color Mode)
        • Figure 8: 16-Level Color Mode Look-Up Table Architecture
        • Table 310: Simulation Of First 16 Entries Of Standard VGA Palette
      • 3.2.8 256 Colors (Eight Bits/Pixel in Color Mode)
        • Table 311: Examples Of 256 Pixel Colors Using Linear LUT
        • Figure 9: 256-Level Color Mode Look-Up Table Architecture
  • 4 DISPLAY MEMORY MODELS
    • 4.1 Registers
    • 4.2 Description
      • 4.2.1 S5U13503B00C Evaluation Board Display Memory
      • 4.2.2 Display Start Address Registers
    • 4.3 Common Display Memory Requirements for LCD Panel Sizes:
      • Table 41: Memory Size Requirements
      • Figure 10: Memory Map Example For 320 x 240 LCD Panel With 4 Colors/Gray Shades
      • Figure 11: Memory Map Example For 320 x 240 LCD Panel With 256 Colors
      • Figure 12: Memory Map Example For 640 x 200 LCD Panel With 16 Colors/Gray Shades
  • 5 ADVANCED TECHNIQUES
    • 5.1 Virtual Displays
      • 5.1.1 Registers
      • 5.1.2 Description
        • Figure 13: Moving A Viewport Inside A Virtual Display
    • 5.2 Bitmaps and Text Displays
      • Figure 14: Font For The Message �TEXT�
      • Figure 15: Display Memory Contents For Message �Text� In 256 Color Mode
    • 5.3 Mapping of Registers
      • 5.3.1 Indexed Mapping
      • 5.3.2 Direct Mapping
    • 5.4 Split Screen
      • 5.4.1 Description
      • 5.4.2 Single Panel LCD
        • Figure 16: Memory Map For Split Screen
        • Figure 17: 320 x 240 Single Panel For Split Screen
      • 5.4.3 Dual Panel LCD
        • Figure 18: 640 x 480 Dual Panel For Split Screen
        • 5.4.3.1 Displaying a Single Image on a Dual Panel
          • Figure 19: Memory Map For A Dual Panel Showing A Single Image
    • 5.5 Panning and Scrolling
      • 5.5.1 Initialization
      • 5.5.2 Panning Right and Left
        • Table 51: Smallest Number Of Pixels For Panning
      • 5.5.3 Scrolling Up and Down
    • 5.6 Power Saving
      • 5.6.1 Registers
        • Table 52: Power Save Mode Selection
      • 5.6.2 Power Save Modes
        • Table 53: Power Save Mode Selection
        • 5.6.2.1 Power Save Mode 1
        • 5.6.2.2 Power Save Mode 2
        • 5.6.2.3 Power Save Mode Function Summary
          • Table 54: Power Save Mode Function Summary
        • 5.6.2.4 Programming to Enter Power Down Mode
        • 5.6.2.5 Programming to Exit Power Down Mode
  • 6 IDENTIFYING THE S1D13503
    • Table 61: ID Bit Usage
  • 7 PROGRAMMING THE S1D13503
    • Figure 20: Display For 13503DEMO.EXE
    • 7.1 Main Loop Code
    • 7.2 Initialization Code
    • 7.3 Advanced Functions
  • 8 GLOSSARY
• S1D13503F00A Register Summary
• 13503SHOW.EXE Display Utility
  • 13503SHOW.EXE Display Utility
    • Program Requirements
      • S1D13503
      • Up to 640x480 LCD
      • Seiko Epson 13503BIOS version 1.xx or later
      • Yes
      • 3.0 or greater
      • No
      • Yes
      • Yes
      • Yes
    • Installation
    • Usage
    • Comments
    • Program Messages
• 13503VIRT.EXE Display Utility
  • 13503VIRT.EXE Display Utility
    • Program Requirements
    • Installation
    • Usage
    • Comments
    • Program Messages
• 13503BIOS.COM Utility
  • 13503BIOS.COM Utility
    • Program Requirements
    • Installation
    • Usage
    • Comments
    • Program Messages
• 13503MODE.EXE Display Utility
  • 13503MODE.EXE Display Utility
    • Program Requirements
    • Installation
    • Usage
    • Comments
    • Program Messages
• 13503PD.EXE Power Down Utility
  • 13503PD.EXE Power Down Utility
    • Program Requirements
    • Installation
    • Usage
    • Comments
    • Program Messages
• 13503READ.EXE Diagnostic Utility
  • 13503READ.EXE Diagnostic Utility
    • Program Requirements
      • S1D13503
      • Up to 640x480 LCD
      • Seiko Epson 13503BIOS.COM (optional)
      • Yes
      • 3.0 or greater
      • No
      • Yes
      • Yes
      • Yes
    • Installation
    • Usage
    • Comments
    • Program Messages
• S5U13503B00C Rev. 1.0 Evaluation Board User Manual
  • TABLE OF CONTENTS
  • LIST OF TABLES
  • LIST OF FIGURES
  • 1 S5U13503B00C REV 1.0 EVALUATION BOARD
    • 1.1 Features
  • 2 INSTALLATION AND CONFIGURATION
    • Table 21: Configuration DIP Switch Settings
    • Table 22: I/O Mapping Example
    • Table 23: Decoding Jumper Setting
    • Hard-Wired Configuration Inputs
      • Table 24: LCD Signal Connector J1 Pinout
      • Table 25: CPU/BUS Connector H1 Pinout
      • Table 26: CPU/BUS Connector H2 Pinout
  • 3 TECHNICAL DESCRIPTION
    • 3.1 ISA Bus Support
      • With VGA
      • With Monochrome
      • Stand-Alone
    • 3.2 Non-ISA Bus Support
    • 3.3 SRAM Support
    • 3.4 Monochrome LCD Support
    • 3.5 Color LCD Support
    • 3.6 Power Save Modes
    • 3.7 Adjustable LCD Panel Negative Power Supply
    • 3.8 Adjustable LCD Panel Positive Power Supply
    • 3.9 Crystal Support
    • 3.10 Oscillator Support
    • 3.11 CPU/Bus Interface Header Strips
    • 3.12 Schematic Notes
  • Appendix A Parts List
  • Appendix B S5U13503B00C Rev. 1.0 Schematic Diagrams
    • Figure 1: S5U13503B00C Rev. 1.0 Schematic Diagram (1 of 7)
    • Figure 2: S5U13503B00C Rev. 1.0 Schematic Diagram (2 of 7)
    • Figure 3: S5U13503B00C Rev. 1.0 Schematic Diagram (3 of 7)
    • Figure 4: S5U13503B00C Rev. 1.0 Schematic Diagram (4 of 7)
    • Figure 5: S5U13503B00C Rev. 1.0 Schematic Diagram (5 of 7)
    • Figure 6: S5U13503B00C Rev. 1.0 Schematic Diagram (6 of 7)
    • Figure 7: S5U13503B00C Rev. 1.0 Schematic Diagram (7 of 7)
• Power Consumption
  • 1 S1D13503 POWER CONSUMPTION
    • 1.1 Conditions
      • Table 11: S1D13503 Total Power Consumption - 3.0V Operation
      • Table 12: S1D13503 Total Power Consumption - 5.0V Operation
• ISA Bus Interface Considerations
  • Table of Contents
  • List of Figures
  • 1 INTRODUCTION
    • 1.1 Reference Material
  • 2 16-BIT ISA BUS INTERFACE
    • Figure 1: 16-Bit ISA Bus Implementation
    • 2.1 PAL Equations
    • 2.2 Additional Discrete Logic Description
    • 2.3 S1D13503 Default Setup
      • 2.3.1 Configuration Options
      • 2.3.2 Register Setting
  • 3 8-BIT ISA BUS INTERFACE
    • Figure 2: 8-Bit ISA Bus Implementation
    • 3.1 S1D13503 Default Setup
      • 3.1.1 Configuration Options
      • 3.1.2 Register Setting
• MC68340 Interface Considerations
  • Table of Contents
  • List of Figures
  • 1 INTRODUCTION
    • 1.1 Reference Material
  • 2 MC68340 MPU INTERFACE
    • Figure 1: MC68340 MPU Interface Block Diagram
    • 2.1 MC68340 Setup
    • 2.2 PAL Equations
    • 2.3 S1D13503 Default Setup
      • Configuration Options
      • Register Setting
• LCD Panel Options / Memory Requirements
  • Table of Contents
  • List of Figures
  • 1 INTRODUCTION
    • 1.1 Reference Material
  • 2 CONFIGURATION EQUATIONS
    • 2.1 Example
      • 2.1.1 Input Clock Requirement Calculation
    • 2.2 SRAM Size and Access Time Requirements
      • 2.2.1 SRAM Size
      • 2.2.2 SRAM Access Time
  • 3 CONCLUSIONS
  • 4 IMPLEMENTATION
    • 4.1 16-Bit Display Memory Interface
      • Figure 1: 16-Bit Memory Configuration Example
      • 4.1.1 Configuration Options
      • 4.1.2 Register Settings
• S1D13503 / S1D13502 Comparison
  • 1 S1D13503 / S1D13502 Comparison
    • 1.1 Feature Comparison
    • 1.2 S1D13503 Register Changes / Additions From The S1D13502
      • AUX[01h]
      • AUX[03h]
      • AUX[0Ch]
      • AUX[0Eh]
      • AUX[0Fh]