Document Outline

• S1D13504 TECHNICAL MANUAL
  • Customer Support Information
    • Comprehensive Support Tools
    • Evaluation / Demonstration Board
    • Chip Documentation
    • Software
    • Application Engineering Support
• Product Brief
  • Description
  • Features
    • Memory Interface
    • CPU Interface
    • Display Support
    • Display Modes
    • Clock Source
    • Power Down Modes
    • General Purpose IO pins
    • Operating Voltage
    • Package
  • System Block Diagram
• Hardware Functional Specification
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
    • 1.1 Scope
    • 1.2 Overview Description
  • 2 Features
    • 2.1 Memory Interface
    • 2.2 CPU Interface
    • 2.3 Display Support
    • 2.4 Display Modes
    • 2.5 Clock Source
    • 2.6 Miscellaneous
    • 2.7 Package and Pin
      • Table 21: S1D13504 Series Package list
  • 3 Typical System Implementation Diagrams
    • Figure 31: Typical System Diagram � SH-3 Bus, 1Mx16 FPM/EDO-DRAM
    • Figure 32: Typical System Diagram � MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000)
    • Figure 33: Typical System Diagram � MC68K Bus 2, 256Kx16 FPM/EDO-DRAM (32-Bit MC68030)
    • Figure 34: Typical System Diagram � Generic Bus, 1Mx16 FPM/EDO-DRAM
  • 4 Block Description
    • 4.1 Functional Block Diagram
      • Figure 41: System Block Diagram Showing Datapaths
    • 4.2 Functional Block Descriptions
      • 4.2.1 Host Interface
      • 4.2.2 Memory Controller
      • 4.2.3 Display FIFO
      • 4.2.4 Look-Up Table
      • 4.2.5 LCD Interface
      • 4.2.6 Power Save
  • 5 Pin Out
    • 5.1 Pinout Diagram for S1D13504F00A
      • Figure 51: Pinout Diagram of F00A
    • 5.2 Pinout Diagram for S1D13504F01A
      • Figure 52: Pinout Diagram of F01A
    • 5.3 Pinout Diagram for S1D13504F02A
      • Figure 53: Pinout Diagram of F02A
    • 5.4 Pin Description
      • 5.4.1 Host Interface
        • Table 51: Host Interface Pin Descriptions 
      • 5.4.2 Memory Interface
        • Table 52: Memory Interface Pin Descriptions 
      • 5.4.3 LCD Interface
        • Table 53: LCD Interface Pin Descriptions 
      • 5.4.4 Clock Input
        • Table 54: Clock Input Pin Description 
      • 5.4.5 CRT and External RAMDAC Interface
        • Table 55: CRT and RAMDAC Interface Pin Descriptions 
      • 5.4.6 Miscellaneous
        • Table 56: Miscellaneous Pin Descriptions 
      • 5.4.7 Power Supply
        • Table 57: Power Supply Pin Descriptions 
    • 5.5 Summary of Configuration Options
      • Table 58: Summary of Power On / Reset Options
    • 5.6 Multiple Function Pin Mapping
      • Table 59: Host Bus Interface Pin Mapping
      • Table 510: Memory Interface Pin Mapping
      • Table 511: LCD, CRT, RAMDAC Interface Pin Mapping
  • 6 D.C. Characteristics
    • Table 61: Absolute Maximum Ratings
    • Table 62: Recommended Operating Conditions
    • Table 63: Input Specifications
    • Table 64: Output Specifications
  • 7 A.C. Characteristics
    • 7.1 CPU Interface Timing
      • 7.1.1 SH-3 Interface Timing
        • Figure 71: SH-3 Interface Timing
        • Table 71: SH-3 Interface Timing
      • 7.1.2 MC68K Bus 1 Interface Timing (e.g. MC68000)
        • Figure 72: MC68K Bus 1 Interface Timing
        • Table 72: MC68K Bus 1 Interface Timing
      • 7.1.3 MC68K Bus 2 Interface Timing (e.g. MC68030)
        • Figure 73: MC68K Bus 2 Interface Timing
        • Table 73: MC68K Bus 2 Interface Timing
      • 7.1.4 Generic MPU Interface Synchronous Timing
        • Figure 74: Generic MPU Interface Synchronous Timing
        • Table 74: Generic MPU Interface Synchronous Timing
      • 7.1.5 Generic MPU Interface Asynchronous Timing
        • Figure 75: Generic MPU Interface Asynchronous Timing
        • Table 75: Generic MPU Interface Asynchronous Timing
    • 7.2 Clock Input Requirements
      • Figure 76: Clock Input Requirements
      • Table 76: Clock Input Requirements
    • 7.3 Memory Interface Timing
      • 7.3.1 EDO-DRAM Read Timing
        • Figure 77: EDO-DRAM Read Timing
        • Table 77: EDO DRAM Read Timing
      • 7.3.2 EDO-DRAM Write Timing
        • Figure 78: EDO-DRAM Write Timing
        • Table 78: EDO DRAM Write Timing
      • 7.3.3 EDO-DRAM Read-Write Timing
        • Figure 79: EDO-DRAM Read-Write Timing
        • Table 79: EDO DRAM Read-Write Timing
      • 7.3.4 EDO-DRAM CAS Before RAS Refresh Timing
        • Figure 710: EDO-DRAM CAS Before RAS Refresh Timing
        • Table 710: EDO-DRAM CAS Before RAS Refresh Timing
      • 7.3.5 EDO-DRAM Self-Refresh Timing
        • Figure 711: EDO-DRAM Self-Refresh Timing
        • Table 711: EDO-DRAM Self-Refresh Timing
      • 7.3.6 FPM-DRAM Read Timing
        • Figure 712: FPM-DRAM Read Timing
        • Table 712: FPM DRAM Read Timing
      • 7.3.7 FPM-DRAM Write Timing
        • Figure 713: FPM-DRAM Write Timing
        • Table 713: FPM-DRAM Write Timing
      • 7.3.8 FPM-DRAM Read-Write Timing
        • Figure 714: FPM-DRAM Read-Write Timing
        • Table 714: FPM-DRAM Read-Write Timing
      • 7.3.9 FPM-DRAM CAS# Before RAS# Refresh Timing
        • Figure 715: FPM-DRAM CAS# Before RAS# Refresh Timing
        • Table 715: FPM-DRAM CAS# Before RAS# Refresh Timing
      • 7.3.10 FPM-DRAM Self-Refresh Timing
        • Figure 716: FPM-DRAM CBR Self-Refresh Timing
        • Table 716: FPM-DRAM CBR Self-Refresh Timing
    • 7.4 Display Interface
      • 7.4.1 Power-On/Reset Timing
        • Figure 717: LCD Panel Power-On/Reset Timing
        • Table 717: LCD Panel Power-On/Reset Timing
      • 7.4.2 Suspend Timing
        • Figure 718: LCD Panel Suspend Timing
        • Table 718: LCD Panel Suspend Timing
      • 7.4.3 Single Monochrome 4-Bit Panel Timing
        • Figure 719: Single Monochrome 4-Bit Panel Timing
        • Figure 720: Single Monochrome 4-Bit Panel A.C. Timing
        • Table 719: Single Monochrome 4-Bit Panel A.C. Timing
      • 7.4.4 Single Monochrome 8-Bit Panel Timing
        • Figure 721: Single Monochrome 8-Bit Panel Timing
        • Figure 722: Single Monochrome 8-Bit Panel A.C. Timing
        • Table 720: Single Monochrome 8-Bit Panel A.C. Timing
      • 7.4.5 Single Color 4-Bit Panel Timing
        • Figure 723: Single Color 4-Bit Panel Timing
        • Figure 724: Single Color 4-Bit Panel A.C. Timing
        • Table 721: Single Color 4-Bit Panel A.C. Timing
      • 7.4.6 Single Color 8-Bit Panel Timing (Format 1)
        • Figure 725: Single Color 8-Bit Panel Timing (Format 1)
        • Figure 726: Single Color 8-Bit Panel A.C. Timing (Format 1)
        • Table 722: Single Color 8-Bit Panel A.C. Timing (Format 1)
      • 7.4.7 Single Color 8-Bit Panel Timing (Format 2)
        • Figure 727: Single Color 8-Bit Panel Timing (Format 2)
        • Figure 728: Single Color 8-Bit Panel A.C. Timing (Format 2)
        • Table 723: Single Color 8-Bit Panel A.C. Timing (Format 2)
      • 7.4.8 Single Color 16-Bit Panel Timing
        • Figure 729: Single Color 16-Bit Panel Timing
        • Figure 730: Single Color 16-Bit Panel A.C. Timing
        • Table 724: Single Color 16-Bit Panel A.C. Timing
      • 7.4.9 Dual Monochrome 8-Bit Panel Timing
        • Figure 731: Dual Monochrome 8-Bit Panel Timing
        • Figure 732: Dual Monochrome 8-Bit Panel A.C. Timing
        • Table 725: Dual Monochrome 8-Bit Panel A.C. Timing
      • 7.4.10 Dual Color 8-Bit Panel Timing
        • Figure 733: Dual Color 8-Bit Panel Timing
        • Figure 734: Dual Color 8-Bit Panel A.C. Timing
        • Table 726: Dual Color 8-Bit Panel A.C. Timing
      • 7.4.11 Dual Color 16-Bit Panel Timing
        • Figure 735: Dual Color 16-Bit Panel Timing
        • Figure 736: Dual Color 16-Bit Panel A.C. Timing
        • Table 727: Dual Color 16-Bit Panel A.C. Timing
      • 7.4.12 16-Bit TFT Panel Timing
        • Figure 737: 16-Bit TFT Panel Timing
        • Figure 738: TFT A.C. Timing
        • Table 728: TFT A.C. Timing
      • 7.4.13 CRT Timing
        • Figure 739: CRT Timing
        • Figure 740: CRT A.C. Timing
        • Table 729: CRT A.C. Timing
      • 7.4.14 External RAMDAC Read / Write Timing
        • Figure 741: Generic Bus RAMDAC Read / Write Timing
        • Table 730: Generic Bus RAMDAC Read / Write Timing
  • 8 Registers
    • 8.1 Register Mapping
      • Table 81: S1D13504 Addressing
    • 8.2 Register Descriptions
      • 8.2.1 Revision Code Register
      • 8.2.2 Memory Configuration Registers
        • Table 82: DRAM Refresh Rate Selection
      • 8.2.3 Panel/Monitor Configuration Registers
        • Table 83: Panel Data Width Selection
        • Table 84: FPLINE Polarity Selection
        • Table 85: FPFRAME Polarity Selection
      • 8.2.4 Display Configuration Registers
        • Table 86: Simultaneous Display Option Selection
        • Table 87: Number of Bits-Per-Pixel Selection
        • Table 88: Pixel Panning Selection
      • 8.2.5 Clock Configuration Register
        • Table 89: PCLK Divide Selection
      • 8.2.6 Power Save Configuration Registers
        • Table 810: Suspend Refresh Selection
      • 8.2.7 Miscellaneous Registers
        • Table 811: Minimum Memory Timing Selection
        • Table 812: RAS-to-CAS Delay Timing Select
        • Table 813: RAS Precharge Timing Select
        • Table 814: Optimal NRC, NRP, and NRCD Values at Maximum MCLK Frequency
      • 8.2.8 Look-Up Table Registers
        • Table 815: RGB Index Selection
      • 8.2.9 External RAMDAC Control Registers
  • 9 Display Buffer
    • Table 91: S1D13504 Addressing
    • Figure 91: Display Buffer Addressing
    • 9.1 Image Buffer
    • 9.2 Half Frame Buffer
  • 10 Display Configuration
    • 10.1 Display Mode Data Format
      • Figure 101: 1/2/4/8 Bit-Per-Pixel Format Memory Organization
      • Figure 102: 15/16 Bit-Per-Pixel Format Memory Organization
    • 10.2 Image Manipulation
      • Figure 103: Image Manipulation
  • 11 Clocking
    • 11.1 Maximum MCLK: PCLK Ratios
      • Table 111: Maximum PCLK Frequency with EDO-DRAM
      • Table 112: Maximum PCLK Frequency with FPM-DRAM
    • 11.2 Frame Rate Calculation
      • Table 113: Example Frame Rates
  • 12 Look-Up Table Architecture
    • Table 121: Look-Up Table Configurations
    • 12.1 Gray Shade Display Modes
      • Figure 121: 1 Bit-Per-Pixel � 2-Level Gray-Shade Mode Look-Up Table Architecture
      • Figure 122: 2 Bit-Per-Pixel � 4-Level Gray-Shade Mode Look-Up Table Architecture
      • Figure 123: 4 Bit-Per-Pixel � 16-Level Gray-Shade Mode Look-Up Table Architecture
    • 12.2 Color Display Modes
      • Figure 124: 1 Bit-Per-Pixel � 2-Level Color Look-Up Table Architecture
      • Figure 125: 2 Bit-Per-Pixel � 4-Level Color Mode Look-Up Table Architecture
      • Figure 126: 4 Bit-Per-Pixel � 16-Level Color Mode Look-Up Table Architecture
      • Figure 127: 8 Bit-Per-Pixel � 256-Level Color Mode Look-Up Table Architecture
  • 13 Power Save Modes
    • 13.1 Hardware Suspend
    • 13.2 Software Suspend
    • 13.3 Power Save Mode Function Summary
      • Table 131: Power Save Mode Function Summary
    • 13.4 Pin States in Power Save Modes
      • Table 132: Pin States in Power Save Modes
  • 14 Mechanical Data
    • 14.1 QFP15-128 (S1D13504F00A)
      • Figure 141: Mechanical Drawing QFP15-128
    • 14.2 TQFP15-128 (S1D13504F01A)
      • Figure 142: Mechanical Drawing TQFP15-128
    • 14.3 QFP20-144 (S1D13504F02A)
      • Figure 143: Mechanical Drawing QFP20-144
  • 15 References
  • 16 Sales and Technical Support
• Programming Notes and Examples
  • Table Of Contents
  • List Of Tables
  • List of Figures
  • 1 Introduction
  • 2 Programming the S1D13504 Registers
    • 2.1 Registers Requiring Special Consideration
      • 2.1.1 REG[01] bit 0 - Memory Type
      • 2.1.2 REG[22] bits 7-2 - Performance Enhancement Register 0
      • 2.1.3 REG[02] bit 1 - Dual/Single Panel Type
      • 2.1.4 REG[1B] bit 0 - Half Frame Buffer Disable
      • 2.1.5 REG[23] Display FIFO:
    • 2.2 Register Initialization
      • 2.2.1 Initialization Sequence
      • 2.2.2 Initialization Example
        • Table 21: Initializing the S1D13504 Registers
      • 2.2.3 Re-Programming Registers
    • 2.3 Disabling the Half Frame Buffer Sequence:
  • 3 Display Buffer
    • 3.1 Display Buffer Location
    • 3.2 Display Buffer Organization
      • 3.2.1 Memory Organization for One Bit-per-pixel (2 Colors/Gray Shades)
        • Table 31: Pixel Storage for 1 bpp (2 Colors/Gray Shades) in One Byte of Display Buffer
      • 3.2.2 Memory Organization for Two Bit-per-pixel (4 Colors/Gray Shades)
        • Table 32: Pixel Storage for 2 bpp (4 Colors/Gray Shades) in One Byte of Display Buffer
      • 3.2.3 Memory Organization for Four Bit-per-pixel (16 Colors/Gray Shades)
        • Table 33: Pixel Storage for 4 bpp (16 Colors/Gray Shades) in One Byte of Display Buffer
      • 3.2.4 Memory Organization for Eight Bit-per-pixel (256 Colors)
        • Table 34: Pixel Storage for 8 bpp (256 Colors) in One Byte of Display Buffer
      • 3.2.5 Memory Organization for 15 Bit-per-pixel (32768 Colors)
        • Table 35: Pixel Storage for 15 bpp (32768 Colors) in Two Bytes of Display Buffer
      • 3.2.6 Memory Organization for 16 Bit-per-pixel (65536 Colors)
        • Table 36: Pixel Storage for 16 bpp (65536 Colors) in Two Bytes of Display Buffer
    • 3.3 Look-Up Table (LUT)
      • 3.3.1 Look-Up Table Registers
      • 3.3.2 Look-Up Table Organization
        • Table 37: Look-Up Table Configurations
        • Table 38: Recommended LUT Values for 1 bpp Color Mode
        • Table 39: Recommended LUT Values for 2 bpp Color Mode
        • Table 310: Recommended LUT Values to Simulate VGA Default 16 Color Palette
        • Table 311: Recommended LUT Values For 8 bpp Color Mode
        • Table 312: Examples of 256 Pixel Colors Using Linear LUT
        • Table 313: Recommended LUT Values for 1 bpp Gray Shades
        • Table 314: Recommended LUT Values for 2 bpp Gray Shades
        • Table 315: Recommended LUT Values for 8 bpp Gray Shade
  • 4 Advanced Techniques
    • 4.1 Virtual Display
      • Figure 41: Viewport Inside a Virtual Display
      • 4.1.1 Registers
      • 4.1.2 Examples
    • 4.2 Panning and Scrolling
      • 4.2.1 Registers
        • Table 41: Number of Pixels Panned Using Start Address
        • Table 42: Active Pixel Pan Bits
      • 4.2.2 Examples
    • 4.3 Split Screen
      • Figure 42: 320x240 Single Panel For Split Screen
      • 4.3.1 Registers
      • 4.3.2 Examples
  • 5 LCD Power Sequencing and Power Save Modes
    • 5.1 Introduction to LCD Power Sequencing
    • 5.2 Introduction to Power Save Modes
    • 5.3 Registers
    • 5.4 Suspend Sequencing
      • 5.4.1 Suspend Enable Sequence
      • 5.4.2 Suspend Disable Sequence
    • 5.5 LCD Enable/Disable Sequencing (Reg[0D] bit 0)
  • 6 CRT Considerations
    • 6.1 Introduction
      • 6.1.1 CRT Only
        • Table 61: RAMDAC Register Mapping for Little/Big-Endian
        • Table 62: Related Register Data for CRT Only
      • 6.1.2 Simultaneous Display
        • Table 63: 8 bpp Recommended RAMDAC palette data for Simultaneous Display
        • Table 64: Related register data for Simultaneous Display
  • 7 Identifying the S1D13504
  • 8 Hardware Abstraction Layer (HAL)
    • 8.1 Introduction
    • 8.2 API for 13504HAL
      • 8.2.1 Initialization
      • 8.2.2 Screen Manipulation
      • 8.2.3 Color Manipulation
      • 8.2.4 Drawing
      • 8.2.5 Register Manipulation
      • 8.2.6 Miscellaneous
  • 9 Sample Code
    • 9.1 Introduction
      • 9.1.1 Sample code using 13504HAL API
      • 9.1.2 Sample code without using 13504HAL API
  • Appendix A Supported Panel Values
    • A.1 Supported Panel Values
      • Table 91: Passive Single Panel
      • Table 92: Passive Dual Panel
      • Table 93: TFT Panel
• Register Summary
  • REG[00h] Revision Code Register 2 R0
  • REG[01h] Memory Configuration Register 1/0 RW
  • REG[02h] Panel Type Register 1/0 RW
  • REG[03h] Mod Rate Register RW
  • REG[04h] Horizontal Display Width Register RW
  • REG[05h] Horizontal Non-Display Period Register RW
  • REG[06h] HRTC/FPLINE Start Position Register RW
  • REG[07h] HRTC/FPLINE Pulse Width Register RW
  • REG[08h] Vertical Display Height Register 0 RW
  • REG[09h] Vertical Display Height Register 1 RW
  • REG[0Ah] Vertical Non-Display Period Register RW
  • REG[0Bh] VRTC/FPFRAME Start Position Register RW
  • REG[0Ch] VRTC/FPFRAME Pulse Width Register RW
  • REG[0Dh] Display Mode Register RW
  • REG[0Eh] Screen 1 Line Compare Register 0 RW
  • REG[0Fh] Screen 1 Line Compare Register 1 RW
  • REG[10h] Screen 1 Display Start Address Register 0 RW
  • REG[11h] Screen 1 Display Start Address Register 1 RW
  • REG[12h] Screen 1 Display Start Address Register 2 RW
  • REG[13h] Screen 2 Display Start Address Register 0 RW
  • REG[14h] Screen 2 Display Start Address Register 1 RW
  • REG[15h] Screen 2 Display Start Address Register 2 RW
  • REG[16h] Memory Address Offset Register 0 RW
  • REG[17h] Memory Address Offset Register 1 RW
  • REG[18h] Pixel Panning Register RW
  • REG[19h] Clock Configuration Register RW
  • REG[1Ah] Power Save Configuration Register RW
  • REG[1Bh] Miscellanious Disable Register RW
  • REG[1Ch] MD Configuration Readback Register 0 RO
  • REG[1Dh] MD Configuration Readback Register 1 RO
  • REG[1Eh] General IO Pins Configuration Register 0 RW
  • REG[1Fh] General IO Pins Configuration Register 1 RW
  • REG[20h] General IO Pins Status / Control Register 0 RW
  • REG[21h] General IO Pins Status / Control Register 1 RW
  • REG[22h] Performance Enhancement Register 0 1/0 RW
  • REG[23h] Performance Enhancement Register 1 RW
  • REG[24h] Look-Up Table Address Register RW
  • REG[26h] Look-Up Table Data Register RW
  • REG[27h] Look-Up Table Bank Select Register RW
  • REG[28h] or REG[29h] 3 RAMDAC Pixel Read Mask Register RW
  • REG[2Ah] or REG[2Bh] 3 RAMDAC Read Mode Address Register RW
  • REG[2Ch] or REG[2Dh] 3 RAMDAC Write Mode Address Register RW
  • REG[2Eh] or REG[2Fh] 3 RAMDAC Palette Data Register RW
• 13504CFG.EXE Configuration Program
  • Table of Contents
  • List of Figures
  • 13504CFG.EXE
  • Program Requirements
    • Installation
    • Usage
  • Script Mode
  • Interactive Mode
    • 13504CFG Menu Bar
      • Figure 1: 13504CFG Menu Bar
      • Viewing 13504CFG Menu Contents
      • Making 13504CFG Menu Selections
        • Figure 2: 13504CFG Open File
      • Files Menu
        • Figure 3: 13504CFG Files Menu
      • View Menu
        • Figure 4: 13504CFG View Menu
        • Figure 5: 13504CFG Current Configuration
        • Figure 6: 13504CFG Advanced Configuration (Partial View of Screen)
      • Device Menu
        • Figure 7: 13504CFG Device Menu
        • Panel
          • Figure 8: 13504CFG Panel Setup
          • Figure 9: 13504CFG Edit Panel Setup
          • Figure 10: 13504CFG Panel Parameter Edit
        • CRT
          • Figure 11: 13504CFG CRT Setup
          • Figure 12: 13504CFG Edit CRT Setup
          • Figure 13: 13504CFG CRT Parameter Edit
        • Advanced Memory
          • Figure 14: 13504CFG Advanced Memory Setup
          • Figure 15: 13504CFG Edit Advanced Memory Setup
          • Figure 16: 13504CFG Memory Parameter Edit
        • Power Management
          • Figure 17: 13504CFG Power Setup
          • Figure 18: 13504CFG Edit Power Setup
          • Figure 19: 13504CFG Power Parameter Edit
        • Lookup Table (LUT)
          • Figure 20: 13504CFG LUT Setup
          • Figure 21: 13504CFG Edit LUT Setup
          • Figure 22: 13504CFG LUT Parameter Edit
        • Setup
          • Figure 23: 13504CFG Setup
          • Figure 24: 13504CFG Setup Parameter Edit For Register Location, Memory Location, and Memory Size.
      • Help Menu
    • Comments
    • Sample Program Messages
• 13504SHOW Demonstration Program
  • 13504SHOW
    • S1D13504 Supported Evaluation Platforms
    • Installation
    • Usage
    • Comments
    • Program Messages
• 13504SPLT Display Utility
  • 13504SPLT
    • S1D13504 Supported Evaluation Platforms
    • Installation
    • Usage
    • 13504SPLT Example
    • Comments
    • Program Messages
• 13504VIRT Display Utility
  • 13504VIRT
    • S1D13504 Supported Evaluation Platforms
    • Installation
    • Usage
    • 13504VIRT Example
    • Comments
    • Program Messages
• 13504PLAY Diagnostic Utility
  • 13504PLAY
    • S1D13504 Supported Evaluation Platforms
    • Installation
    • Usage
    • 13504PLAY Example
    • Scripting
    • Comments
    • Program Messages
• 13504BMP Demonstration Program
  • 13504BMP
    • Installation
    • Usage
    • Comments
    • Program Messages
• 13504PWR Software Suspend Power Sequencing Utility
  • 13504PWR
    • S1D13504 Supported Evaluation Platforms
    • Installation
    • Usage
    • Comments
    • Program Messages
• 13504DCFG Driver Configuration Program
  • Table of Contents
  • 13504DCFG
    • Installation
    • Usage
    • 13504DCFG Configuration Tabs
      • General Tab
      • Preferences Tab
      • Memory Tab
      • Clocks Tab
      • Panel Tab
      • CRT Tab
      • Registers Tab
    • 13504DCFG Menus
      • Export
      • Enable Tooltips
        • Tooltip Delay
      • ERD on the Web
      • Update Common Controls
      • About 13504DCFG
    • Comments
• Windows� CE 2.x Display Drivers
  • WINDOWS� CE 2.x DISPLAY DRIVERS
    • Example Driver Builds
    • Installation for CEPC Environment
    • Configuration
      • Compile Switches
      • Mode File
    • Comments
• Wind River WindML v2.0 Display Drivers
  • Wind River WindML v2.0 Display Drivers
    • Building a WindML v2.0 Display Driver
      • 1. Create a working directory and unzip the WindML display driver into it.
      • 2. Configure for the target execution model.
      • 3. Build the WindML v2.0 library.
      • 4. Build a boot ROM image.
      • 5. Create a bootable disk (in drive A:).
      • 6. If necessary, generate a new mode0.h configuration file.
      • 7. Open the S1D13504 workspace.
      • 8. Add support for single line comments.
        • a. In the Tornado �Workspace Views� window, click on the �Builds� tab.
        • b. Expand the �8bpp Builds� (or �16bpp Builds�) view by clicking on the �+� next to it. The expan...
        • c. Select the �C/C++ compiler� tab to display the command switches used in the build. Remove the ...
      • 9. Compile the VxWorks image.
      • 10. Copy the VxWorks file to the diskette.
      • 11. Start the VxWorks demo.
• Wind River UGL v1.2 Display Drivers
  • Wind River UGL v1.2 Display Drivers
    • Building a UGL v1.2 Display Driver
      • 1. Create a working directory and unzip the UGL display driver into it.
      • 2. Configure for the target execution model.
      • 3. Build a boot ROM image.
      • 4. Create a bootable disk (in drive A:).
      • 5. If necessary, generate a new mode0.h configuration file.
      • 6. Open the S1D13504 workspace.
      • 7. Add support for single line comments.
        • a. In the Tornado �Workspace� window, click on the �Builds� tab.
        • b. Expand the �8bpp Builds� (or �16bpp Builds�) view by clicking on the �+� next to it. The expan...
        • c. Select the �C/C++ compiler� tab to display the command switches used in the build. Remove the ...
      • 8. Compile the VxWorks image.
      • 9. Copy the VxWorks file to the diskette.
      • 10. Start the VxWorks demo.
• Linux Console Driver
  • Linux Console Driver
    • Building the Console Driver for Linux Kernel 2.2.x
      • 1. Acquire the Linux kernel source code.
      • 2. Unzip the console driver files.
      • 3. Copy the console driver files to the build directory.
      • 4. Modify s1d13504.h
      • 5. Configure the video options.
      • 6. Compile and install the kernel
      • 7. Boot to the Linux operating system
    • Building the Console Driver for Linux Kernel 2.4.x
      • 1. Acquire the Linux kernel source code.
      • 2. Unzip the console driver files.
      • 3. Copy the console driver files to the build directory. Make the directory /usr/src/linux/driver...
      • 4. Modify s1d13504.h
      • 5. Configure the video options.
      • 6. Compile and install the kernel
      • 7. Boot to the Linux operating system
• Windows� CE 3.x Display Drivers
  • WINDOWS� CE 3.x DISPLAY DRIVERS
    • Example Driver Builds
    • Installation for CEPC Environment
    • Configuration
      • Compile Switches
      • Mode File
      • Resource Management Issues
    • Comments
• S1D13XXX 32-Bit Windows Device Driver Installation Guide
  • S1D13XXX 32-Bit Windows Device Driver Installation Guide
    • Driver Requirements
    • Installation
      • Windows NT Version 4.0
      • Windows 2000
      • Windows 98/ME
      • Windows 95 OSR2
      • Previous Versions of Windows 95
• S5U13504B00C Rev. 1.0 ISA Bus Evaluation Board User Manual
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
    • 1.1 Features
  • 2 Installation and Configuration
    • Table 21: Configuration DIP Switch Settings
    • Table 22: Host Bus Selection
    • Table 23: Jumper Settings
  • 3 LCD / RAMDAC Interface Pin Mapping
    • Table 31: LCD Signal Connector (J6)
  • 4 CPU / BUS Interface Connector Pinouts
    • Table 41: CPU/BUS Connector (H1) Pinout
    • Table 42: CPU/BUS Connector (H2) Pinout
  • 5 Host Bus Interface Pin Mapping
    • Table 51: Host Bus Interface Pin Mapping
  • 6 Technical Description
    • 6.1 ISA Bus Support
    • 6.2 Non-ISA Bus Support
    • 6.3 DRAM Support
    • 6.4 Decode Logic
    • 6.5 Clock Input Support
    • 6.6 Monochrome LCD Panel Support
    • 6.7 Color Passive LCD Panel Support
    • 6.8 Color TFT LCD Panel Support
    • 6.9 External CMOS RAMDAC Support
    • 6.10 Power Save Modes
    • 6.11 Core VDD Power Supply
    • 6.12 IO VDD Power Supply
    • 6.13 Adjustable LCD Panel Negative Power Supply
    • 6.14 Adjustable LCD Panel Positive Power Supply
    • 6.15 CPU/Bus Interface Header Strips
    • 6.16 Schematic Notes
  • 7 Parts List
  • 8 Schematic Diagrams
    • Figure 1: S1D13504B00C Schematic Diagram (1 of 6)
    • Figure 2: S1D13504B00C Schematic Diagram (2 of 6)
    • Figure 3: S1D13504B00C Schematic Diagram (3 of 6)
    • Figure 4: S1D13504B00C Schematic Diagram (4 of 6)
    • Figure 5: S1D13504B00C Schematic Diagram (5 of 6)
    • Figure 6: S1D13504B00C Schematic Diagram (6 of 6)
• S5U13504B00C Rev. 2.0 PCI Evaluation Board User Manual
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Features
  • 3 Installation and Configuration
    • 3.1 Configuration DIP Switches
      • Figure 31: Configuration DIP Switch (S1) Location
      • Table 31: Configuration DIP Switch Settings
    • 3.2 Configuration Jumpers
      • Table 32: Jumper Settings
      • Figure 32: Configuration Jumper (JP1) Location
      • Figure 33: Configuration Jumper (JP2) Location
      • Figure 34: Configuration Jumper (JP3) Location
      • Figure 35: Configuration Jumper (JP4) Location
      • Figure 36: Configuration Jumper (JP5) Location
      • Figure 37: Configuration Jumper (JP6) Location
      • Figure 38: Configuration Jumper (JP7) Location
  • 4 Technical Description
    • 4.1 PCI Bus Support
    • 4.2 Non-PCI Host Interface Support
      • 4.2.1 CPU Interface Pin Mapping
        • Table 41: CPU Interface Pin Mapping
      • 4.2.2 CPU Bus Connector Pin Mapping
        • Table 42: CPU/BUS Connector (H1) Pinout
        • Table 43: CPU/BUS Connector (H2) Pinout
    • 4.3 LCD Support
      • 4.3.1 LCD Interface Pin Mapping
        • Table 44: LCD Signal Connector (J1)
      • 4.3.2 Buffered LCD Connector
      • 4.3.3 Adjustable LCD Panel Positive Power Supply (VDDH)
        • Table 45: Controlling the MAX754
      • 4.3.4 Manual/Software Adjustable LCD Panel Negative Power Supply (VLCD)
        • Table 46: Controlling the MAX749
    • 4.4 Current Consumption Measurement
  • 5 References
    • 5.1 Documents
    • 5.2 Document Sources
  • 6 Parts List
    • Table 61: Parts List
  • 7 Schematics
    • Figure 71: S5U13504B00C Rev. 2.0 Evaluation Board Schematics (1 of 5)
    • Figure 72: S5U13504B00C Rev. 2.0 Evaluation Board Schematics (2 of 5)
    • Figure 73: S5U13504B00C Rev. 2.0 Evaluation Board Schematics (3 of 5)
    • Figure 74: S5U13504B00C Rev. 2.0 Evaluation Board Schematics (4 of 5)
    • Figure 75: S5U13504B00C Rev. 2.0 Evaluation Board Schematics (5 of 5)
  • 8 Board Layout
    • Figure 81: S5U13504B00C Rev. 2.0 Evaluation Board Layout
  • 9 Technical Support
    • 9.1 EPSON LCD/CRT Controllers (S1D13504)
• Interfacing to the Philips MIPS PR31500/PR31700 Processor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the PR31500/PR31700
  • 3 S1D13504 Host Bus Interface
    • 3.1 Generic MPU Host Bus Interface Pin Mapping
      • Table 31: Generic MPU Host Bus Interface Pin Mapping
    • 3.2 Generic MPU Host Bus Interface Signals
  • 4 Direct Connection to the Philips PR31500/PR31700
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of S1D13504 to PR31500/PR31700 Direct Connection
    • 4.2 Memory Mapping and Aliasing
    • 4.3 S1D13504 Configuration
      • Table 41: S1D13504 Configuration for Direct Connection
      • Table 42: S1D13504 Host Bus Selection for Direct Connection
  • 5 System Design Using the IT8368E PC Card Buffer
    • 5.1 Hardware Description�Using One IT8368E
      • Figure 51: S1D13504 to PR31500/PR31700 Connection using One IT8368E
    • 5.2 Hardware Description�Using Two IT8368E�s
      • Figure 52: S1D13504 to PR31500/PR31700 Connection using Two IT8368E
    • 5.3 IT8368E Configuration
    • 5.4 Memory Mapping and Aliasing
      • Table 51: PR31500/PR31700 to Unbuffered PC Card Slots System Address Mapping
      • Table 52: PR31500/PR31700 to PC Card Slots Address Remapping using the IT8368E
    • 5.5 S1D13504 Configuration
      • Table 53: S1D13504 Configuration using the IT8368E
      • Table 54: S1D13504 Host Bus Selection using the IT8368E
  • 6 Software
  • 7 References
    • 7.1 Documents
    • 7.2 Document Sources
  • 8 Technical Support
    • 8.1 EPSON LCD/CRT Controllers (S1D13504)
    • 8.2 Philips MIPS PR31500/PR31700 Processor
    • 8.3 ITE IT8368E
• Power Consumption
  • 1 S1D13504 Power Consumption
    • 1.1 Conditions
      • Table 11: S1D13504 Total Power Consumption
  • 2 Summary
• Interfacing to the NEC VR4102� Microprocessor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the NEC VR4102
    • 2.1 The NEC VR4102 System Bus
      • 2.1.1 Overview
      • 2.1.2 LCD Memory Access Cycles
        • Figure 21: NEC VR4102 Read/Write Cycles
  • 3 S1D13504 Host Bus Interface
    • 3.1 Generic MPU Host Bus Interface Pin Mapping
      • Table 31: Generic MPU Host Bus Interface Pin Mapping
    • 3.2 Generic MPU Host Bus Interface Signals
  • 4 VR4102 to S1D13504 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of VR4102 to S1D13504 Interface
    • 4.2 S1D13504 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Options
      • Table 42: Host Bus Interface Selection
    • 4.3 NEC VR4102� Configuration
      • Table 42: NEC/S1D13504 Truth Table
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (S1D13504)
    • 7.2 NEC Electronics Inc. (VR4102).
• Interfacing to the Motorola MC68328 "Dragonball" Microprocessor
  • Document Number: X19A-G-013-03
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the MC68328
    • 2.1 The 68328 System Bus
    • 2.2 Chip-Select Module
  • 3 S1D13504 Host Bus Interface
    • 3.1 Generic MPU Host Bus Interface Pin Mapping
      • Table 31: Generic MPU Host Bus Interface Pin Mapping
    • 3.2 Generic MPU Host Bus Interface Signals
  • 4 MC68328 To S1D13504 Interface
    • 4.1 Hardware Description
      • Figure 41: Block Diagram of MC68328 to S1D13504 Interface - MC68000 Bus 1 Interface Mode
      • Figure 42: Block Diagram of MC68328 to S1D13504 Interface - Generic Interface Mode
    • 4.2 S1D13504 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Options
      • Table 42: S1D13504 Host Bus Selection
      • Table 43: Memory Configuration
    • 4.3 MC68328 Chip Select Configuration
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (S1D13504)
    • 7.2 Motorola MC68328 Processor
• Interfacing to the PC Card Bus
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the PC Card Bus
    • 2.1 The PC Card System Bus
      • 2.1.1 PC Card Overview
      • 2.1.2 Memory Access Cycles
        • Figure 21: PC Card Read Cycle
        • Figure 22: PC Card Write Cycle
  • 3 S1D13504 Host Bus Interface
    • 3.1 Generic MPU Host Bus Interface Pin Mapping
      • Table 31: Generic MPU Host Bus Interface Pin Mapping
    • 3.2 Generic MPU Host Bus Interface Signals
  • 4 PC Card to S1D13504 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of PC Card to S1D13504 Interface
    • 4.2 S1D13504 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Options
      • Table 42: Host Bus Interface Selection
    • 4.3 PAL Equations
    • 4.4 Register/Memory Mapping
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (S1D13504)
    • 7.2 PC Card Standard
• Interfacing to the Motorola MPC821 Microprocessor
  • Document Number: X19A-G-010-06
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the MPC821
    • 2.1 The MPC8xx System Bus
    • 2.2 MPC821 Bus Overview
      • 2.2.1 Normal (Non-Burst) Bus Transactions
        • Figure 21: Power PC Memory Read Cycle
        • Figure 22: Power PC Memory Write Cycle
    • 2.3 Memory Controller Module
      • 2.3.1 General-Purpose Chip Select Module (GPCM)
      • 2.3.2 User-Programmable Machine (UPM)
  • 3 S1D13504 Host Bus Interface
    • 3.1 Generic MPU Host Bus Interface Pin Mapping
      • Table 31: Generic MPU Host Bus Interface Pin Mapping
    • 3.2 Generic MPU Host Bus Interface Signals
  • 4 MPC821 to S1D13504 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of MPC821 to S1D13504 Interface
    • 4.2 Hardware Connections
      • Table 41: List of Connections from MPC821ADS to S1D13504
    • 4.3 S1D13504 Hardware Configuration
      • Table 42: Summary of Power-On/Reset Options
      • Table 42: Host Bus Interface Selection
    • 4.4 Register/Memory Mapping
    • 4.5 MPC821 Chip Select Configuration
    • 4.6 Test Software
      • 4.6.1 Source Code
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (S1D13504)
    • 7.2 Motorola MPC821 Processor
• Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the MCF5307
    • 2.1 The MCF5307 System Bus
      • 2.1.1 Overview
      • 2.1.2 Normal (Non-Burst) Bus Transactions
        • Figure 21: MCF5307 Memory Read Cycle
        • Figure 22: MCF5307 Memory Write Cycle
      • 2.1.3 Burst Cycles
    • 2.2 Chip-Select Module
  • 3 S1D13504 Bus Interface
    • 3.1 Generic MPU Host Bus Interface Pin Mapping
      • Table 31: Generic MPU Host Bus Interface Pin Mapping
    • 3.2 Generic MPU Host Bus Interface Signals
  • 4 MCF5307 To S1D13504 Interface
    • 4.1 Hardware Connections
      • Figure 41: Typical Implementation of MCF5307 to S1D13504 Interface
    • 4.2 S1D13504 Hardware Configuration
      • Table 41: S1D13504 Configuration Settings
      • Table 42: S1D13504 Host Bus Selection
    • 4.3 Memory/Register Mapping
    • 4.4 MCF5307 Chip Select Configuration
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (S1D13504)
    • 7.2 Motorola MCF5307 Processor
• Interfacing to the Toshiba MIPS TX3912 Processor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the TX3912
  • 3 S1D13504 Host Bus Interface
    • 3.1 Generic MPU Host Bus Interface Pin Mapping
      • Table 31: Generic MPU Host Bus Interface Pin Mapping
    • 3.2 Generic MPU Host Bus Interface Signals
  • 4 Direct Connection to the Toshiba TX3912
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of TX3912 to S1D13504 Direct Connection
    • 4.2 Memory Mapping and Aliasing
    • 4.3 S1D13504 Hardware Configuration
      • Table 41: S1D13504 Configuration for Direct Connection
      • Table 42: S1D13504 Host Bus Selection for Direct Connection
  • 5 System Design Using the IT8368E PC Card Buffer
    • 5.1 Hardware Description�Using One IT8368E
      • Figure 51: S1D13504 to TX3912 Connection using One IT8368E
    • 5.2 Hardware Description�Using Two IT8368E�s
      • Figure 52: S1D13504 to TX3912 Connection using Two IT8368E
    • 5.3 IT8368E Configuration
    • 5.4 Memory Mapping and Aliasing
      • Table 51: TX3912 to Unbuffered PC Card Slots System Address Mapping
      • Table 52: TX3912 to PC Card Slots Address Remapping using the IT8368E
    • 5.5 S1D13504 Configuration
      • Table 53: S1D13504 Configuration using the IT8368E
      • Table 54: S1D13504 Host Bus Selection using the IT8368E
  • 6 Software
  • 7 References
    • 7.1 Documents
    • 7.2 Document Sources
  • 8 Technical Support
    • 8.1 EPSON LCD/CRT Controllers (S1D13504)
    • 8.2 Toshiba MIPS TX3912 Processor
    • 8.3 ITE IT8368E