Document Outline

• S1D13506 TECHNICAL MANUAL
  • COMPREHENSIVE SUPPORT TOOLS
    • Documentation
    • Evaluation/Demonstration Board
  • Application Engineering Support
    • Application Engineering Support
• Product Brief
  • FEATURES
  • SYSTEM BLOCK DIAGRAM
  • DESCRIPTION
• Hardware Functional Specification
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
    • 1.1 Scope
    • 1.2 Overview Description
  • 2 Features
    • 2.1 Memory Interface
    • 2.2 CPU Interface
    • 2.3 Display Support
    • 2.4 Display Modes
    • 2.5 Display Features
    • 2.6 Clock Source
    • 2.7 Acceleration
    • 2.8 MediaPlug Interface
    • 2.9 Miscellaneous
  • 3 Typical System Implementation Diagrams
    • Figure 31: Typical System Diagram (Generic Bus)
    • Figure 32: Typical System Diagram (Hitachi SH-4 Bus)
    • Figure 33: Typical System Diagram (Hitachi SH-3 Bus)
    • Figure 34: Typical System Diagram (MC68K Bus 1, Motorola 16-Bit 68000)
    • Figure 35: Typical System Diagram (MC68K Bus 2, Motorola 32-Bit 68030)
    • Figure 36: Typical System Diagram (Motorola PowerPC Bus)
    • Figure 37: Typical System Diagram (NECVR41xx MIPS Bus)
    • Figure 38: Typical System Diagram (PC Card Bus)
    • Figure 39: Typical System Diagram (Philips MIPS PR31500/PR31700 Bus)
    • Figure 310: Typical System Diagram (Toshiba MIPS TX3912 Bus)
  • 4 Internal Description
    • 4.1 Block Diagram Showing Pipelines
      • Figure 41: S1D13506 Block Diagram
  • 5 Pins
    • 5.1 Pinout Diagram
      • Figure 51: Pinout Diagram
    • 5.2 Pin Description
      • 5.2.1 Host Bus Interface
        • Table 51: Host Bus Interface Pin Descriptions 
      • 5.2.2 Memory Interface
        • Table 52: Memory Interface Pin Descriptions 
      • 5.2.3 LCD Interface
        • Table 53: LCD Interface Pin Descriptions 
      • 5.2.4 CRT Interface
        • Table 54: CRT Interface Pin Descriptions 
      • 5.2.5 Miscellaneous
        • Table 55: Miscellaneous Interface Pin Descriptions 
    • 5.3 Summary of Configuration Options
      • Table 56: Summary of Power-On/Reset Options
    • 5.4 Multiple Function Pin Mapping
      • Table 57: CPU Interface Pin Mapping
      • Table 58: Memory Interface Pin Mapping
      • Table 59: LCD Interface Pin Mapping
      • Table 510: MA11, MA10, MA9, and DRDY Pin Mapping 
      • Table 511: MediaPlug Interface Pin Mapping
    • 5.5 CRT/TV Interface
      • Figure 52: External Circuitry for CRT/TV Interface
  • 6 D.C. Characteristics
    • Table 61: Absolute Maximum Ratings
    • Table 62: Recommended Operating Conditions
    • Table 63: Electrical Characteristics for VDD = 5.0V typical 
    • Table 64: Electrical Characteristics for VDD = 3.3V typical
    • Table 65: Electrical Characteristics for VDD = 3.0V typical
  • 7 A.C. Characteristics
    • 7.1 CPU Interface Timing
      • 7.1.1 Generic Timing
        • Figure 71: Generic Timing
        • Table 71: Generic Timing
      • 7.1.2 Hitachi SH-4 Interface Timing
        • Figure 72: Hitachi SH-4 Timing
        • Table 72: Hitachi SH-4 Timing
      • 7.1.3 Hitachi SH-3 Interface Timing
        • Figure 73: Hitachi SH-3 Timing
        • Table 73: Hitachi SH-3 Timing
      • 7.1.4 MIPS/ISA Interface Timing (e.g. NEC VR41xx)
        • Figure 74: MIPS/ISA Timing
        • Table 74: MIPS/ISA Timing
      • 7.1.5 Motorola MC68K Bus 1 Interface Timing (e.g. MC68000)
        • Figure 75: Motorola MC68000 Timing
        • Table 75: Motorola MC68000 Timing
      • 7.1.6 Motorola MC68K Bus 2 Interface Timing (e.g. MC68030)
        • Figure 76: Motorola MC68030 Timing
        • Table 76: Motorola MC68030 Timing
      • 7.1.7 Motorola PowerPC Interface Timing (e.g. MPC8xx, MC68040, Coldfire)
        • Figure 77: Motorola PowerPC Timing
        • Table 77: Motorola PowerPC Timing
      • 7.1.8 PC Card Timing (e.g. StrongARM)
        • Figure 78: PC Card Timing
        • Table 78: PC Card Timing
      • 7.1.9 Philips Interface Timing (e.g. PR31500/PR31700)
        • Figure 79: Philips Timing
        • Table 79: Philips Timing
      • 7.1.10 Toshiba Interface Timing (e.g. TX39xx)
        • Figure 710: Toshiba Timing
        • Table 710: Toshiba Timing
    • 7.2 Clock Timing
      • 7.2.1 Input Clocks
        • Figure 711: CLKI Clock Input Requirements
        • Table 711: Clock Input Requirements for CLKI/CLKI2/BUSCLK divided down internally
        • Table 712: Clock Input Requirements for CLKI or BUSCLK if used directly for MCLK1
      • 7.2.2 Internal Clocks
        • Table 713: Internal Clock Requirements
    • 7.3 Memory Interface Timing
      • 7.3.1 EDO-DRAM Read, Write, Read-Write Timing
        • Figure 712: EDO-DRAM Page Mode Timing
        • Figure 713: EDO-DRAM Read-Write Timing
        • Table 714: EDO-DRAM Read, Write, Read-Write Timing
      • 7.3.2 EDO-DRAM CAS Before RAS Refresh Timing
        • Figure 714: EDO-DRAM CAS Before RAS Refresh Timing
        • Table 715: EDO-DRAM CAS Before RAS Refresh Timing
      • 7.3.3 EDO-DRAM Self-Refresh Timing
        • Figure 715: EDO - DRAM Self-Refresh Timing
        • Table 716: EDO - DRAM Self-Refresh Timing
      • 7.3.4 FPM-DRAM Read, Write, Read-Write Timing
        • Figure 716: FPM-DRAM Page Mode Timing
        • Figure 717: FPM-DRAM Read-Write Timing
        • Table 717: FPM-DRAM Read, Write, Read-Write Timing
      • 7.3.5 FPM-DRAM CAS Before RAS Refresh Timing
        • Figure 718: FPM-DRAM CAS Before RAS Refresh Timing
        • Table 718: FPM-DRAM CAS Before RAS Refresh Timing
      • 7.3.6 FPM-DRAM Self-Refresh Timing
        • Figure 719: FPM - DRAM Self-Refresh Timing
        • Table 719: FPM-DRAM Self-Refresh Timing
    • 7.4 Power Sequencing
      • 7.4.1 LCD Power Sequencing
        • Figure 720: LCD Panel Power-off/Power-on Timing
        • Table 720: LCD Panel Power-off/Power-on Timing
      • 7.4.2 Power Save Mode
        • Figure 721: Power Save Mode Timing
        • Table 721: Power Save Mode Timing
    • 7.5 Display Interface
      • 7.5.1 Single Monochrome 4-Bit Panel Timing
        • Figure 722: Single Monochrome 4-Bit Panel Timing
        • Figure 723: Single Monochrome 4-Bit Panel A.C. Timing
        • Table 722: Single Monochrome 4-Bit Panel A.C. Timing
      • 7.5.2 Single Monochrome 8-Bit Panel Timing
        • Figure 724: Single Monochrome 8-Bit Panel Timing
        • Figure 725: Single Monochrome 8-Bit Panel A.C. Timing
        • Table 723: Single Monochrome 8-Bit Panel A.C. Timing
      • 7.5.3 Single Color 4-Bit Panel Timing
        • Figure 726: Single Color 4-Bit Panel Timing
        • Figure 727: Single Color 4-Bit Panel A.C. Timing
        • Table 724: Single Color 4-Bit Panel A.C. Timing
      • 7.5.4 Single Color 8-Bit Panel Timing (Format 1)
        • Figure 728: Single Color 8-Bit Panel Timing (Format 1)
        • Figure 729: Single Color 8-Bit Panel A.C. Timing (Format 1)
        • Table 725: Single Color 8-Bit Panel A.C. Timing (Format 1)
      • 7.5.5 Single Color 8-Bit Panel Timing (Format 2)
        • Figure 730: Single Color 8-Bit Panel Timing (Format 2)
        • Figure 731: Single Color 8-Bit Panel A.C. Timing (Format 2)
        • Table 726: Single Color 8-Bit Panel A.C. Timing (Format 2)
      • 7.5.6 Single Color 16-Bit Panel Timing
        • Figure 732: Single Color 16-Bit Panel Timing
        • Figure 733: Single Color 16-Bit Panel A.C. Timing
        • Table 727: Single Color 16-Bit Panel A.C. Timing
      • 7.5.7 Single Color 16-Bit Panel Timing with External Circuit
        • Figure 734: 16-Bit Single Color Panel Timing with External Circuit
        • Figure 735: External Circuit for Color Single 16-Bit Panel When the Media Plug is Enabled
        • Figure 736: Single Color 16-Bit Panel (with External Circuit) A.C. Timing
        • Table 728: Single Color 16-Bit Panel (with External Circuit) A.C. Timing
      • 7.5.8 Dual Monochrome 8-Bit Panel Timing
        • Figure 737: Dual Monochrome 8-Bit Panel Timing
        • Figure 738: Dual Monochrome 8-Bit Panel A.C. Timing
        • Table 729: Dual Monochrome 8-Bit Panel A.C. Timing
      • 7.5.9 Dual Color 8-Bit Panel Timing
        • Figure 739: Dual Color 8-Bit Panel Timing
        • Figure 740: Dual Color 8-Bit Panel A.C. Timing
        • Table 730: Dual Color 8-Bit Panel A.C. Timing
      • 7.5.10 Dual Color 16-Bit Panel Timing
        • Figure 741: Dual Color 16-Bit Panel Timing
        • Figure 742: Dual Color 16-Bit Panel A.C. Timing
        • Table 731: Dual Color 16-Bit Panel A.C. Timing
      • 7.5.11 Dual Color 16-Bit Panel Timing with External Circuit
        • Figure 743: 16-Bit Dual Color Panel Timing with External Circuit
        • Figure 744: External Circuit for Color Dual 16-Bit Panel When the Media Plug is Enabled
        • Figure 745: Dual Color 16-Bit Panel (with External Circuit) A.C. Timing
        • Table 732: Dual Color 16-Bit Panel (with External Circuit) A.C. Timing
      • 7.5.12 TFT/D-TFD Panel Timing
        • Figure 746: TFT/D-TFD Panel Timing
        • Figure 747: TFT/D-TFD A.C. Timing
        • Table 733: TFT/D-TFD A.C. Timing
      • 7.5.13 CRT Timing
        • Figure 748: CRT Timing
        • Figure 749: CRT A.C. Timing
        • Table 734: CRT A.C. Timing
    • 7.6 TV Timing
      • 7.6.1 TV Output Timing
        • Figure 750: NTSC Video Timing
        • Figure 751: PAL Video Timing
        • Figure 752: Horizontal Timing for NTSC/PAL
        • Table 735: Horizontal Timing for NTSC/PAL
        • Figure 753: Vertical Timing for NTSC/PAL
        • Table 736: Vertical Timing for NTSC/PAL
    • 7.7 MediaPlug Interface Timing
      • Figure 754: MediaPlug A.C. Timing
      • Table 737: MediaPlug A.C. Timing
  • 8 Registers
    • 8.1 Initializing the S1D13506
      • 8.1.1 Register/Memory Select Bit
    • 8.2 Register Mapping
      • Table 81: Register Mapping with CS# = 0 and M/R# = 0
    • 8.3 Register Descriptions
      • 8.3.1 Basic Registers
      • 8.3.2 General IO Pins Registers
        • Table 82: MA[11:9]/GPIO[1:3] Pin Functionality
      • 8.3.3 MD Configuration Readback Registers
      • 8.3.4 Clock Configuration Registers
        • Table 83: MCLK Source Select
        • Table 84: LCD PCLK Divide Selection
        • Table 85: LCD PCLK Source Selection
        • Table 86: CRT/TV PCLK Divide Selection
        • Table 87: CRT/TV PCLK Source Selection
        • Table 88: MediaPlug Clock Divide Selection
        • Table 89: Video Clock Source Selection
        • Table 810: Minimum Memory Timing Selection
      • 8.3.5 Memory Configuration Registers
        • Table 811: Memory Type Selection
        • Table 812: Refresh Selection
        • Table 813: DRAM Refresh Rate Selection
        • Table 814: DRAM Timing Control Selection
      • 8.3.6 Panel Configuration Registers
        • Table 815: Panel Data Width Selection
        • Table 816: Horizontal Display Width (Pixels)
        • Table 817: LCD FPLINE Polarity Selection
        • Table 818: LCD FPFRAME Polarity Selection
      • 8.3.7 LCD Display Mode Registers
        • Table 819: Setting SwivelView Modes
        • Table 820: LCD Bit-per-pixel Selection
        • Table 821: LCD Pixel Panning Selection
      • 8.3.8 CRT/TV Configuration Registers
        • Table 822: DAC Output Level Selection
      • 8.3.9 CRT/TV Display Mode Registers
        • Table 823: CRT/TV Bit-per-pixel Selection
        • Table 824: CRT/TV Pixel Panning Selection
      • 8.3.10 LCD Ink/Cursor Registers
        • Table 825: LCD Ink/Cursor Selection
        • Table 826: LCD Ink/Cursor Start Address Encoding
      • 8.3.11 CRT/TV Ink/Cursor Registers
        • Table 827: CRT/TV Ink/Cursor Selection
        • Table 828: CRT/TV Ink/Cursor Start Address Encoding
      • 8.3.12 BitBlt Configuration Registers
        • Table 829: BitBlt Active Status
        • Table 830: BitBlt FIFO Data Available
        • Table 831: BitBlt ROP Code/Color Expansion Function Selection
        • Table 832: BitBlt Operation Selection
        • Table 833: BitBlt Source Start Address Selection
      • 8.3.13 Look-Up Table Registers
        • Table 834: LUT Mode Selection
      • 8.3.14 Power Save Configuration Registers
      • 8.3.15 Miscellaneous Registers
      • 8.3.16 Common Display Mode Register
        • Table 835: Setting SwivelView Modes
        • Table 836: Display Mode Selection
      • 8.3.17 MediaPlug Register Descriptions
        • Table 837: MediaPlug LCMD Read/Write Descriptions
        • Table 838: Timeout Option Delay
        • Table 839: Cable Detect and Remote Powered Status
        • Table 840: MediaPlug CMD Read/Write Descriptions
        • Table 841: MediaPlug Commands
      • 8.3.18 BitBlt Data Registers Descriptions
  • 9 2D BitBlt Engine
    • 9.1 Functional Description
    • 9.2 BitBlt Operations
  • 10 Display Buffer
    • Table 101: S1D13506 Addressing
    • Figure 101: Display Buffer Addressing
    • 10.1 Image Buffer
    • 10.2 Ink Layer/Hardware Cursor Buffers
    • 10.3 Dual Panel Buffer
  • 11 Display Configuration
    • 11.1 Display Mode Data Format
      • Figure 111: 4/8/15/16 Bit-per-pixel Format Memory Organization
    • 11.2 Image Manipulation
      • Figure 112: Image Manipulation
  • 12 Look-Up Table Architecture
    • 12.1 Monochrome Modes
      • Figure 121: 4 Bit-Per-Pixel Monochrome Mode Data Output Path
    • 12.2 Color Modes
      • Figure 122: 4 Bit-Per-Pixel Color Mode Data Output Path
      • Figure 123: 8 Bit-Per-Pixel Color Mode Data Output Path
  • 13 TV Considerations
    • 13.1 NTSC/PAL Operation
    • 13.2 Clock Source
      • Table 131: Required Clock Frequencies for NTSC/PAL
    • 13.3 Filters
      • 13.3.1 Chrominance Filter (REG[05Bh] bit 5)
      • 13.3.2 Luminance Filter (REG[05Bh] bit 4)
      • 13.3.3 Anti-flicker Filter (REG[1FCh] bits [2:1])
    • 13.4 TV Output Levels
      • Figure 131: NTSC/PAL SVideo-Y (Luminance) Output Levels
      • Table 132: NTSC/PAL SVideo-Y (Luminance) Output Levels
      • Figure 132: NTSC/PAL SVideo-C (Chrominance) Output Levels
      • Table 133: NTSC/PAL SVideo-C (Chrominance) Output Levels
      • Figure 133: NTSC/PAL Composite Output Levels
      • Table 134: NTSC/PAL Composite Output Levels
    • 13.5 TV Image Display and Positioning
      • Figure 134: NTSC/PAL Image Positioning
      • Table 135: Minimum and Maximum Values for NTSC/PAL
      • Figure 135: Typical Total Display and Visible Display Dimensions for NTSC and PAL
      • Table 136: Register Values for Example NTSC/PAL Images
    • 13.6 TV Cursor Operation
  • 14 Ink Layer/Hardware Cursor Architecture
    • 14.1 Ink Layer/Hardware Cursor Buffers
      • Table 141: Ink/Cursor Start Address Encoding
    • 14.2 Ink/Cursor Data Format
      • Figure 141: Ink/Cursor Data Format
      • Table 142: Ink/Cursor Color Select
    • 14.3 Ink/Cursor Image Manipulation
      • 14.3.1 Ink Image
      • 14.3.2 Cursor Image
        • Figure 142: Unclipped Cursor Positioning
        • Figure 143: Clipped Cursor Positioning
  • 15 SwivelView�
    • 15.1 Concept
    • 15.2 90 SwivelView�
      • Figure 151: Relationship Between Screen Image and 90 Rotated Image in the Display Buffer
      • 15.2.1 Register Programming
      • 15.2.2 Physical Memory Requirement
        • Table 151: Minimum DRAM Size Required for SwivelView�
      • 15.2.3 Limitations
    • 15.3 180 SwivelView�
      • 15.3.1 Register Programming
      • 15.3.2 Limitations
    • 15.4 270 SwivelView�
      • 15.4.1 Register Programming
      • 15.4.2 Physical Memory Requirement
      • 15.4.3 Limitations
  • 16 EPSON Independent Simultaneous Display (EISD)
    • 16.1 Introduction
    • 16.2 Bandwidth Limitation
  • 17 MediaPlug Interface
    • 17.1 Revision Code
    • 17.2 How to enable the MediaPlug Slave
      • Table 171: MediaPlug Interface Pin Mapping
  • 18 Clocking
    • 18.1 Frame Rate Calculation
      • 18.1.1 LCD Frame Rate Calculation
      • 18.1.2 CRT Frame Rate Calculation
      • 18.1.3 TV Frame Rate Calculation
    • 18.2 Example Frame Rates
      • 18.2.1 Frame Rates for 640x480 with EISD Disabled
        • Table 181: Frame Rates for 640x480 with EISD Disabled
      • 18.2.2 Frame Rates for 800x600 with EISD Disabled
        • Table 182: Frame Rates for 800x600 with EISD Disabled
      • 18.2.3 Frame Rates for LCD and CRT (640x480) with EISD Enabled
        • Table 183: Frame Rates for LCD and CRT (640x480) with EISD Enabled
      • 18.2.4 Frame Rates for LCD and CRT (800x600) with EISD Enabled
        • Table 184: Frame Rates for LCD and CRT (800x600) with EISD Enabled
      • 18.2.5 Frame Rates for LCD and NTSC TV with EISD Enabled
        • Table 185: Frame Rates for LCD and NTSC TV with EISD Enabled
      • 18.2.6 Frame Rates for LCD and PAL TV with EISD Enabled
        • Table 186: Frame Rates for LCD and PAL TV with EISD Enabled
  • 19 Power Save Mode
    • 19.1 Display Modes
    • 19.2 Power Save Mode
    • 19.3 Power Save Status Bits
    • 19.4 Power Save Mode Summary
      • Table 191: Power Save Mode Summary
  • 20 Clocks
    • 20.1 Clock Selection
      • Figure 201: Clock Selection
    • 20.2 Clock Descriptions
      • 20.2.1 MCLK
      • 20.2.2 LCD PCLK
      • 20.2.3 CRT/TV PCLK
      • 20.2.4 MediaPlug Clock
    • 20.3 Clocks vs. Functions
      • Table 201: Clocks vs. Functions
  • 21 Mechanical Data
    • Figure 211: Mechanical Drawing QFP15
• Programming Notes and Examples
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Initialization
    • Table 21: S1D13506 Initialization Sequence
  • 3 Memory Models
    • 3.1 Display Buffer Location
    • 3.2 Memory Organization for 4 Bpp (16 Colors/16 Gray Shades)
      • Figure 31: Pixel Storage for 4 Bpp in One Byte of Display Buffer
    • 3.3 Memory Organization for 8 Bpp (256 Colors/16 Gray Shades)
      • Figure 32: Pixel Storage for 8 Bpp in One Byte of Display Buffer
    • 3.4 Memory Organization for 15 Bpp (32768 Colors/32 Gray Shades)
      • Figure 33: Pixel Storage for 15 Bpp in Two Bytes of Display Buffer
    • 3.5 Memory Organization for 16 Bpp (65536 Colors/64 Gray Shades)
      • Figure 34: Pixel Storage for 16 Bpp in Two Bytes of Display Buffer
  • 4 Look-Up Table (LUT)
    • 4.1 Registers
    • 4.2 Look-Up Table Organization
      • Table 41: Look-Up Table Configurations
      • 4.2.1 Color Modes
        • Table 42: Suggested LUT Values to Simulate VGA Default 16 Color Palette
        • Table 43: Suggested LUT Values to Simulate VGA Default 256 Color Palette
      • 4.2.2 Gray Shade Modes
        • Table 44: Suggested LUT Values for 4 Bpp Gray Shade
  • 5 Virtual Displays
    • 5.1 Virtual Display
      • Figure 51: Viewport Inside a Virtual Display
      • 5.1.1 Registers
      • 5.1.2 Examples
    • 5.2 Panning and Scrolling
      • 5.2.1 Registers
        • Table 51: Number of Pixels Panned When Start Address Changed By 1
        • Table 52: Active Pixel Pan Bits
      • 5.2.2 Examples
  • 6 Power Save Mode
    • 6.1 Overview
    • 6.2 Registers
      • 6.2.1 Enabling Power Save Mode
      • 6.2.2 Power Save Status Bits
      • 6.2.3 DRAM Refresh Selection
        • Table 61: Refresh Selection
  • 7 LCD Power Sequencing
    • 7.1 Automatic Sequencing
    • 7.2 Manual Sequencing
      • 7.2.1 Registers
      • 7.2.2 Enabling the LCD Panel
      • 7.2.3 Disabling the LCD Panel
  • 8 Hardware Cursor/Ink Layer
    • 8.1 Introduction
    • 8.2 Registers
      • Table 81: Ink/Cursor Mode
      • Table 82: Cursor/Ink Start Address Encoding
    • 8.3 Initialization
      • 8.3.1 Memory Considerations
      • 8.3.2 Examples
        • Table 83: LCD Hardware Cursor Initialization Sequence
        • Table 84: Ink Layer Start Address Encoding
        • Table 85: LCD Ink Layer Initialization Sequence
    • 8.4 Writing Cursor/Ink Layer Images
      • 8.4.1 Hardware Cursor/Ink Layer Data Format
        • Figure 81: Hardware Cursor/Ink Layer Data Format
        • Table 86: Ink/Cursor Color Select
      • 8.4.2 Cursor Image
      • 8.4.3 Ink Layer Image
    • 8.5 Cursor Movement
      • 8.5.1 Move Cursor in Landscape Mode (no rotation)
      • 8.5.2 Move Cursor in SwivelView 90 Rotation
      • 8.5.3 Move Cursor in SwivelView 180 Rotation
      • 8.5.4 Move Cursor in SwivelView 270 Rotation
  • 9 SwivelView�
    • 9.1 S1D13506 SwivelView
    • 9.2 Registers
      • Table 91: SwivelView Enable Bits
      • Table 92: LCD Memory Address Offset Values
      • Table 93: LCD Display Start Address Values
    • 9.3 Limitations
    • 9.4 Examples
    • 9.5 Simultaneous Display Considerations
  • 10 2D BitBLT Engine
    • 10.1 Registers
      • Table 101: BitBLT ROP Code/Color Expansion Function Selection
      • Table 102: BitBLT Operation Selection
      • Table 103: BitBLT Source Start Address Selection
    • 10.2 BitBLT Descriptions
      • 10.2.1 Write Blit with ROP
        • Table 104: Possible Blit FIFO Writes
      • 10.2.2 Color Expand BitBLT
        • Table 105: Possible Blit FIFO Writes
      • 10.2.3 Color Expand BitBLT With Transparency
      • 10.2.4 Solid Fill BitBLT
      • 10.2.5 Move BitBLT in a Positive Direction with ROP
        • Figure 101: Move BitBLT Usage
      • 10.2.6 Move BitBLT in Negative Direction with ROP
      • 10.2.7 Transparent Write Blit
        • Table 106: Possible Blit FIFO Writes
      • 10.2.8 Transparent Move BitBLT in Positive Direction
      • 10.2.9 Pattern Fill BitBLT with ROP
      • 10.2.10 Pattern Fill BitBLT with Transparency
      • 10.2.11 Move BitBLT with Color Expansion
      • 10.2.12 Transparent Move Blit with Color Expansion
      • 10.2.13 Read Blit
        • Table 107: Possible Blit FIFO Reads
    • 10.3 S1D13506 BitBLT Synchronization
    • 10.4 S1D13506 BitBLT Known Limitations
    • 10.5 Sample Code
  • 11 CRT/TV Considerations
    • 11.1 CRT Considerations
      • 11.1.1 Generating CRT timings with 13506CFG
      • 11.1.2 DAC Output Level Selection
      • 11.1.3 Examples
    • 11.2 TV Considerations
      • 11.2.1 NTSC Timings
      • 11.2.2 PAL Timings
      • 11.2.3 TV Filters
      • 11.2.4 Examples
    • 11.3 Simultaneous Display
  • 12 MediaPlug
    • 12.1 Programming
    • 12.2 Considerations
  • 13 Identifying the S1D13506
  • 14 Hardware Abstraction Layer (HAL)
    • 14.1 API for 13506HAL
      • Table 141: HAL Functions
    • 14.2 Initialization
      • 14.2.1 General HAL Support
      • 14.2.2 Advance HAL Functions
      • 14.2.3 Surface Support
      • 14.2.4 Register Access
      • 14.2.5 Memory Access
      • 14.2.6 Color Manipulation
      • 14.2.7 Virtual Display
      • 14.2.8 Drawing
      • 14.2.9 Hardware Cursor
      • 14.2.10 Ink Layer
      • 14.2.11 PCI Support
    • 14.3 Porting LIBSE to a new target platform
      • Figure 141: Components needed to build 13506 HAL application
      • 14.3.1 Building the LIBSE library for SH3 target example
      • 14.3.2 Building a complete application for the target example
  • 15 Sample Code
• Register Summary
  • REG[000h] Revision Code Register 2 (For S1D13506: Product Code=000100b, Revision Code=01b) RO
  • REG[001h] Miscellaneous Register 1/0 RW
  • REG[004h] General I/O Pins Configuration Register 3 1/0 RW
  • REG[008h] General I/O Pins Control Register RW
  • REG[00Ch] MD Configuration Readback Register 0 RW
  • REG[00Dh] MD Configuration Readback Register 1 RW
  • REG[010h] Memory Clock Configuration Register 4 RW
  • REG[014h] LCD Pixel Clock Configuration Register 5,6 RW
  • REG[018h] CRT/TV Pixel Clock Configuration Register 7,8 RW
  • REG[01Ch] MediaPlug Clock Configuration Register 9,10 RW
  • REG[01Eh] CPU To Memory Wait State Select Register 11 RW
  • REG[020h] Memory Configuration Register 12 RW
  • REG[021h] DRAM Refresh Rate Register 13,14 RW
  • REG[02Ah] DRAM Timing Control Register 0 15 RW
  • REG[02Bh] DRAM Timing Control Register 1 15 RW
  • REG[030h] Panel Type Register 16 RW
  • REG[031h] MOD Rate Register RW
  • REG[032h] LCD Horizontal Display Width Register RW
  • REG[034h] LCD Horizontal Non-Display Period Register RW
  • REG[035h] TFT FPLINE Start Position Register RW
  • REG[036h] TFT FPLINE Pulse Width Register 17 RW
  • REG[038h] LCD Vertical Display Height Register 0 RW
  • REG[039h] LCD Vertical Display Height Register 1 RW
  • REG[03Ah] LCD Vertical Non-Display Period Register RW
  • REG[03Bh] TFT FPFRAME Start Position Register RW
  • REG[03Ch] TFT FPFRAME Pulse Width Register 18 RW
  • REG[040h] LCD Display Mode Register 19 RW
  • REG[041h] LCD Miscellaneous Register RW
  • REG[042h] LCD Display Start Address Register 0 RW
  • REG[043h] LCD Display Start Address Register 1 RW
  • REG[044h] LCD Display Start Address Register 2 RW
  • REG[046h] LCD Memory Address Offset Register 0 RW
  • REG[047h] LCD Memory Address Offset Register 1 RW
  • REG[048h] LCD Pixel Panning Register 20 RW
  • REG[04Ah] LCD Display FIFO High Threshold Control Register RW
  • REG[04Bh] LCD Display FIFO Low Threshold Control Register RW
  • REG[050h] CRT/TV Horizontal Display Width Register RW
  • REG[052h] CRT/TV Horizontal Non-Display Period Register RW
  • REG[053h] CRT/TV HRTC Start Position Register RW
  • REG[054h] CRT HRTC Pulse Width Register RW
  • REG[056h] CRT/TV Vertical Display Height Register 0 RW
  • REG[057h] CRT/TV Vertical Display Height Register 1 RW
  • REG[058h] CRT/TV Vertical Non-Display Period Register RW
  • REG[059h] CRT/TV VRTC Start Position Register RW
  • REG[05Ah] CRT/TV VRTC Pulse Width Register RW
  • REG[05Bh] CRT/TV Output Control Register RW
  • REG[060h] CRT/TV Display Mode Register 21 RW
  • REG[062h] CRT/TV Display Start Address Register 0 RW
  • REG[063h] CRT/TV Display Start Address Register 1 RW
  • REG[064h] CRT/TV Display Start Address Register 2 RW
  • REG[066h] CRT/TV Memory Address Offset Register 0 RW
  • REG[067h] CRT/TV Memory Address Offset Register 1 RW
  • REG[068h] CRT/TV Pixel Panning Register 22 RW
  • REG[06Ah] CRT/TV Display FIFO High Threshold Control Register RW
  • REG[06Bh] CRT/TV Display FIFO Low Threshold Control Register RW
  • REG[070h] LCD Ink/Cursor Control Register 23 RW
  • REG[071h] LCD Ink/Cursor Start Address Register 24 RW
  • REG[072h] LCD Cursor X Position Register 0 RW
  • REG[073h] LCD Curxor X Position Register 1 RW
  • REG[074h] LCD Cursor Y Position Register 0 RW
  • REG[075h] LCD Cursor Y Position Register 1 RW
  • REG[076h] LCD Ink/Cursor Blue Color 0 Register RW
  • REG[077h] LCD Ink/Cursor Green Color 0 Register RW
  • REG[078h] LCD Ink/Cursor Red Color 0 Register RW
  • REG[07Ah] LCD Ink/Cursor Blue Color 1 Register RW
  • REG[07Bh] LCD Ink/Cursor Green Color 1 Register RW
  • REG[07Ch] LCD Ink/Cursor Red Color 1 Register RW
  • REG[07Eh] LCD Ink/Cursor FIFO Thrshold Register RW
  • REG[080h] CRT/TV Ink/Cursor Control Register 25 RW
  • REG[081h] CRT/TV Ink/Cursor Start Address Register 26 RW
  • REG[082h] CRT/TV Cursor X Position Register 0 RW
  • REG[083h] CRT/TV Cursor X Position Register 1 RW
  • REG[084h] CRT/TV Cursor Y Position Register 0 RW
  • REG[085h] CRT/TV Cursor Y Position Register 1 RW
  • REG[086h] CRT/TV Ink/Cursor Blue Color 0 Register RW
  • REG[087h] CRT/TV Ink/Cursor Green Color 0 Register RW
  • REG[088h] CRT/TV Ink/Cursor Red Color 0 Register RW
  • REG[08Ah] CRT/TV Ink/Cursor Blue Color 1 Register RW
  • REG[08Bh] CRT/TV Ink/Cursor Green Color 1 Register RW
  • REG[08Ch] CRT/TV Ink/Cursor Red Color 1 Register RW
  • REG[08Eh] CRT/TV Ink/Cursor FIFO Threshold Register RW
  • REG[100h] BitBlt Control Register 0 27 RW
  • REG[101h] BitBlt Control Register 1 RW
  • REG[102h] BitBlt ROP Code/Color Expansion Register 28 RW
  • REG[103h] BitBlt Operation Register 29 RW
  • REG[104h] BitBlt Source Start Address Register 0 30 RW
  • REG[105h] BitBlt Source Start Address Register 1 30 RW
  • REG[106h] BitBlt Source Start Address Register 2 30 RW
  • REG[108h] BitBlt Destination Start Address Register 0 RW
  • REG[109h] BitBlt Destination Start Address Register 1 RW
  • REG[10Ah] BitBlt Destination Start Address Register 2 RW
  • REG[10Ch] BitBlt Memory Address Offset Register 0 RW
  • REG[10Dh] BitBlt Memory Address Offset Register 1 RW
  • REG[110h] BitBlt Width Register 0 RW
  • REG[111h] BitBlt Width Register 1 RW
  • REG[112h] BitBlt Height Register 0 RW
  • REG[113h] BitBlt Height Register 1 RW
  • REG[114h] BitBlt Backgroud Color Register 0 RW
  • REG[115h] BitBlt Background Color Register 1 RW
  • REG[118h] BitBlt Foreground Color Register 0 RW
  • REG[119h] BitBlt Foreground Color Register 1 RW
  • REG[1E0h] Look-Up Table Mode Register 31 RW
  • REG[1E2h] Look-Up Table Address Register RW
  • REG[1E4h] Look-Up Table Data Register RW
  • REG[1F0h] Power Save Configuration Register RW
  • REG[1F1h] Power Save Status Register RO
  • REG[1F4h] CPU-to-Memory Access Watchdog Timer Register RW
  • REG[1FCh] Display Mode Register 32 RW
  • REG[1000h] MediaPlug LCMD Register RW
  • REG[1002h] MediaPlug Reserved LCMD Register RW
  • REG[1004h] MediaPlug CMD Register RW
  • REG[1006h] MediaPlug Reserved CMD Register RW
  • REG[1008h] to REG[1FFEh], even address MediaPlug Data Registers RW
  • A20-A0 = 100000h-1FFFFEh, even address BitBlt Data Register 0 RW
• 13506CFG Configuration Program
  • Table of Contents
  • 13506CFG
    • S1D13506 Supported Evaluation Platforms
    • Installation
    • Usage
    • 13506CFG Configuration Tabs
      • General Tab
      • Preferences Tab
      • Memory Tab
      • Clocks Tab
      • Panel Tab
      • CRT/TV Tab
      • Registers Tab
    • 13506CFG Menus
      • Open...
      • Save
      • Save As...
      • Configure Multiple
      • Export
      • Enable Tooltips
      • ERD on the Web
      • About 13506CFG
    • Comments
• 13506SHOW Demonstration Program
  • 13506SHOW
    • S1D13506 Supported Evaluation Platforms
    • Installation
    • Usage
    • Display Surfaces
      • Table 1: Display Surfaces
    • 13506SHOW Examples
      • Using 13506SHOW For Demonstration
      • Using 13506SHOW For Testing
    • Comments
    • Program Messages
• 13506PLAY Diagnostic Utility
  • 13506PLAY
    • S1D13506 Supported Evaluation Platforms
    • Installation
    • Usage
    • Commands
      • Table 1: iCrtTv Selection
    • 13506PLAY Example
    • Scripting
    • Comments
    • Program Messages
• 13506BMP Demonstration Program
  • 13506BMP
    • S1D13506 Supported Evaluation Platforms
    • Installation
    • Usage
    • Display Surfaces
      • Table 1: Display Surfaces
    • 13506BMP Examples
    • Comments
    • Program Messages
• 13506FILT Test Utility
  • 13506FILT
    • S1D13506 Supported Evaluation Platforms
    • Installation
    • Usage
    • Filter Dialog Box
      • Figure 1: Filter Dialog Box
    • Filter Descriptions
      • Anti-flicker Filter
      • Chrominance Filter
      • Luminance Filter
    • Comments
• 13506SWIVEL Demonstration Utility
  • 13506SWIVEL
    • S1D13506 Supported Evaluation Platforms
    • Installation
    • Usage
    • Example
    • Comments
• Windows� CE Display Drivers
  • WINDOWS� CE DISPLAY DRIVERS
    • Program Requirements
    • Example Driver Builds
    • Installation for CEPC Environment
    • Comments
• Wind River WindML v2.0 Display Drivers
  • Wind River WindML v2.0 DISPLAY DRIVERS
    • Building a WindML v2.0 Display Driver
      • 1. Create a working directory and unzip the WindML display driver into it.
      • 2. Configure for the target execution model.
      • 3. Build a boot ROM image.
      • 4. Create a bootable disk (in drive A:).
      • 5. If necessary, generate a new mode0.h configuration file.
      • 6. Build the WindML v2.0 library.
      • 7. Open the S1D13506 workspace.
      • 8. Add support for single line comments.
        • a. In the Tornado �Workspace Views� window, click on the �Builds� tab.
        • b. Expand the �8bpp Builds� (or �16bpp Builds�) view by clicking on the �+� next to it. The expan...
        • c. Select the �C/C++ compiler� tab to display the command switches used in the build. Remove the ...
      • 9. Compile the VxWorks image.
      • 10. Copy the VxWorks file to the diskette.
      • 11. Start the VxWorks demo.
• Wind River UGL v1.2 Display Drivers
  • Wind River UGL v1.2 Display Drivers
    • Building a UGL v1.2 Display Driver
      • 1. Create a working directory and unzip the UGL display driver into it
      • 2. Configure for the target execution model.
      • 3. Build a boot ROM image.
      • 4. Create a bootable disk (in drive A:).
      • 5. If necessary, generate a new mode0.h configuration file.
      • 6. Open the S1D13506 workspace.
      • 7. Add support for single line comments.
        • a. In the Tornado �Workspace� window, click on the �Builds� tab.
        • b. Expand the �8bpp Builds� (or �16bpp Builds�) view by clicking on the �+� next to it. The expan...
        • c. Select the �C/C++ compiler� tab to display the command switches used in the build. Remove the ...
      • 8. Compile the VxWorks image.
      • 9. Copy the VxWorks file to the diskette.
      • 10. Start the VxWorks demo.
• Linux Console Driver
  • Linux Console Driver
    • Building the S1D13506 Console Driver
      • 1. Acquire the Linux kernel source code.
      • 2. Unzip the console driver files.
      • 3. Copy the console driver files to the build directory.
      • 4. Modify s1d13506.h
      • 5. Configure the video options.
      • 6. Compile and install the kernel
      • 7. Boot to the Linux operating system
• QNX Photon v2.0 Display Driver
  • QNX Photon v2.0 Display Driver
    • Building the Photon v2.0 Display Driver
      • Unpack the Graphics Driver Development Kit Archive
      • Configure the Driver
      • Build the Driver
      • Installing the Driver
      • Run the Driver
    • Comments
• S1D13XXX 32-Bit Windows Device Driver Installation Guide
  • S1D13XXX 32-Bit Windows Device Driver Installation Guide
    • Driver Requirements
    • Installation
      • Windows NT Version 4.0
      • Windows 2000
      • Windows 98/ME
      • Windows 95 OSR2
      • Previous Versions of Windows 95
• S5U13506B00C Evaluation Board User Manual
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Features
  • 3 Installation and Configuration
    • 3.1 Configuration DIP Switches
      • Table 31: Configuration DIP Switch Settings
      • Table 32: Host Bus Selection
    • 3.2 Configuration Jumpers
      • Table 33: Jumper Settings
  • 4 Technical Description
    • 4.1 PCI Bus Support
      • Table 41: S1D13506 Memory Mapping onto 4M byte PCI Address Block
      • 4.1.1 On-Board PCI Configuration Registers
        • Read-Only Registers
          • Table 42: PCI Configuration Register Read Values
        • Read/Write Registers
          • Table 43: PCI Configuration Register Write Values
      • 4.1.2 Utility Software
    • 4.2 Non-PCI Host Interface Support
      • 4.2.1 CPU Interface Pin Mapping
        • Table 44: CPU Interface Pin Mapping
      • 4.2.2 CPU Bus Connector Pin Mapping
        • Table 45: CPU/BUS Connector (H1) Pinout
        • Table 46: CPU/BUS Connector (H2) Pinout
    • 4.3 LCD Support
      • 4.3.1 LCD Interface Pin Mapping
        • Table 47: LCD Signal Connector (J1)
      • 4.3.2 Buffered LCD Connector
      • 4.3.3 16-bit Passive Color Panel Support with MediaPlug Enabled
        • Figure 41: External Circuit for Color Single 16-Bit Panel with MediaPlug Enabled
        • Figure 42: External Circuit for Color Dual 16-Bit Panel with MediaPlug Enabled
      • 4.3.4 Adjustable LCD Panel Positive Power Supply
      • 4.3.5 Adjustable LCD Panel Negative Power Supply
    • 4.4 CRT/TV Support
      • 4.4.1 CRT/TV Interface Pin Mapping
        • Table 48: CRT/TV Interface Pin Mapping
      • 4.4.2 CRT Support
      • 4.4.3 TV Support
    • 4.5 MediaPlug Interface
      • Table 49: MediaPlug Connector (J5) Pin Mapping
    • 4.6 Clock Synthesizer and Clock Options
      • Figure 43: Symbolic Clock Synthesizer Connections
      • 4.6.1 Clock Programming
  • 5 References
    • 5.1 Documents
    • 5.2 Document Sources
  • 6 Parts List
    • Table 61: Parts List
  • 7 Schematic Diagrams
    • Figure 71: S5U13506B00C Schematic Diagram (1 of 7)
    • Figure 72: S5U13506B00C Schematic Diagram (2 of 7)
    • Figure 73: S5U13506B00C Schematic Diagram (3 of 7)
    • Figure 74: S5U13506B00C Schematic Diagram (4 of 7)
    • Figure 75: S5U13506B00C Schematic Diagram (5 of 7)
    • Figure 76: S5U13506B00C Schematic Diagram (6 of 7)
    • Figure 77: S5U13506B00C Schematic Diagram (7 of 7)
  • 8 Technical Support
    • 8.1 EPSON LCD/CRTControllers (S1D13506)
• Interfacing to the PC Card Bus
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the PC Card Bus
    • 2.1 The PC Card System Bus
      • 2.1.1 PC Card Overview
      • 2.1.2 Memory Access Cycles
        • Figure 21: PC Card Read Cycle
        • Figure 22: PC Card Write Cycle
  • 3 S1D13506 Host Bus Interface
    • 3.1 PC Card Host Bus Interface Pin Mapping
      • Table 31: PC Card Host Bus Interface Pin Mapping
    • 3.2 PC Card Host Bus Interface Signals
  • 4 PC Card to S1D13506 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of PC Card to S1D13506 Interface
    • 4.2 S1D13506 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Options
    • 4.3 Performance
    • 4.4 Register/Memory Mapping
      • Table 42: Register/Memory Mapping for Typical Implementation
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 Epson LCD/CRT Controllers (S1D13506)
    • 7.2 PC Card Standard
• Power Consumption
  • 1 S1D13506 Power Consumption
    • 1.1 Conditions
      • Table 11: S1D13506 Power Consumption
  • Summary
• Interfacing to the NEC VR4102/VR4111� Microprocessors
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the VR4102/VR4111
    • 2.1 The NEC VR4102/VR4111 System Bus
      • 2.1.1 Overview
      • 2.1.2 LCD Memory Access Cycles
        • Figure 21: NEC VR4102/VR4111 Read/Write Cycles
  • 3 S1D13506 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signal Descriptions
  • 4 VR4102/VR4111 to S1D13506 Interface
    • 4.1 Hardware Description
      • Figure 41: NEC VR4102/VR4111 to S1D13506 Configuration Schematic
    • 4.2 S1D13506 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Options
    • 4.3 NEC VR4102/VR4111 Configuration
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (S1D13506)
    • 7.2 NEC Electronics Inc. (VR4102/VR4111).
• Interfacing to the Motorola MPC821 Microprocessor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the MPC821
    • 2.1 The MPC8xx System Bus
    • 2.2 MPC821 Bus Overview
      • 2.2.1 Normal (Non-Burst) Bus Transactions
        • Figure 21: Power PC Memory Read Cycle
        • Figure 22: Power PC Memory Write Cycle
      • 2.2.2 Burst Cycles
    • 2.3 Memory Controller Module
      • 2.3.1 General-Purpose Chip Select Module (GPCM)
      • 2.3.2 User-Programmable Machine (UPM)
  • 3 S1D13506 Host Bus Interface
    • 3.1 PowerPC Host Bus Interface Pin Mapping
      • Table 31: PowerPC Host Bus Interface Pin Mapping
    • 3.2 PowerPC Host Bus Interface Signals
  • 4 MPC821 to S1D13506 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of MPC821 to S1D13506 Interface
    • 4.2 Hardware Connections
      • Table 41: List of Connections from MPC821ADS to S1D13506 
    • 4.3 S1D13506 Hardware Configuration
      • Table 42: Summary of Power-On/Reset Options
    • 4.4 Register/Memory Mapping
    • 4.5 MPC821 Chip Select Configuration
    • 4.6 Test Software
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (S1D13506)
    • 7.2 Motorola MPC821 Processor
• Interfacing to the Philips MIPS PR31500/PR31700 Processor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the PR31500/PR31700
  • 3 S1D13506 Host Bus Interface
    • 3.1 PR31500/PR31700 Host Bus Interface Pin Mapping
      • Table 31: PR31500/PR31700 Host Bus Interface Pin Mapping
    • 3.2 PR31500/PR31700 Host Bus Interface Signals
  • 4 Direct Connection to the Philips PR31500/PR31700
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of Direct Connection
    • 4.2 S1D13506 Configuration
      • Table 41: S1D13506 Configuration for Direct Connection
    • 4.3 Memory Mapping and Aliasing
      • Table 42: PR31500/PR31700 to PC Card Slots Address Remapping for Direct Connection
  • 5 System Design Using the IT8368E PC Card Buffer
    • 5.1 Hardware Description
      • Figure 51: IT8368E Implementation Block Diagram
    • 5.2 IT8368E Configuration
    • 5.3 S1D13506 Configuration
  • 6 Software
  • 7 References
    • 7.1 Documents
    • 7.2 Document Sources
  • 8 Technical Support
    • 8.1 EPSON LCD/CRT Controllers (S1D13506)
    • 8.2 Philips MIPS PR31500/PR31700 Processor
    • 8.3 ITE IT8368E
• Interfacing to the Toshiba MIPS TX3912 Processor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the TX3912
  • 3 S1D13506 Host Bus Interface
    • 3.1 TX3912 Host Bus Interface Pin Mapping
      • Table 31: TX3912 Host Bus Interface Pin Mapping
    • 3.2 TX3912 Host Bus Interface Signals
  • 4 Direct Connection to the Toshiba TX3912
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of Direct Connection
    • 4.2 S1D13506 Configuration
      • Table 41: S1D13506 Configuration for Direct Connection
    • 4.3 Memory Mapping and Aliasing
      • Table 42: TX3912 to PC Card Slots Address Remapping for Direct Connection
  • 5 System Design Using the IT8368E PC Card Buffer
    • 5.1 Hardware Description
      • Figure 51: IT8368E Implementation Block Diagram
    • 5.2 IT8368E Configuration
    • 5.3 S1D13506 Configuration
  • 6 Software
  • 7 References
    • 7.1 Documents
    • 7.2 Document Sources
  • 8 Technical Support
    • 8.1 EPSON LCD/CRT Controllers (S1D13506)
    • 8.2 Toshiba MIPS TX3912 Processor
    • 8.3 ITE IT8368E
• Interfacing to the NEC VR4121� Microprocessor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the NEC VR4121
    • 2.1 The NEC VR4121 System Bus
      • 2.1.1 Overview
      • 2.1.2 LCD Memory Access Cycles
        • Figure 21: NEC VR4121 Read/Write Cycles
  • 3 S1D13506 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signal Descriptions
  • 4 VR4121 to S1D13506 Interface
    • 4.1 Hardware Description
      • Figure 41: NEC VR4121 to S1D13506 Configuration Schematic
    • 4.2 S1D13506 Configuration
      • Table 41: Summary of Power-On/Reset Options
    • 4.3 NEC VR4121 Configuration
    • 4.4 Memory Mapping and Aliasing
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 Epson LCD/CRT Controllers (S1D13506)
    • 7.2 NEC Electronics Inc. (VR4121).
• Interfacing to the NEC V832� Microprocessor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the NEC V832
    • 2.1 The NEC V832 System Bus
      • 2.1.1 Overview
      • 2.1.2 Access Cycles
        • Figure 21: NEC V832 Read/Write Cycles
  • 3 S1D13506 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signal Descriptions
  • 4 V832 to S1D13506 Interface
    • 4.1 Hardware Description
      • Figure 41: NEC V832 to S1D13506 Configuration Schematic
    • 4.2 S1D13506 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Options
    • 4.3 NEC V832 Configuration
      • Table 42: NEC V832 Wait States vs. Bus Clock Frequency
    • 4.4 Memory Mapping and Aliasing
      • Table 43: NEC V832 IO Address Range For Each CSn Line
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 Epson LCD/CRT Controllers (S1D13506)
    • 7.2 NEC Electronics Inc. (V832).
• Interfacing to the StrongARM SA-1110 Processor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the StrongARM SA-1110 Bus
    • 2.1 The StrongARM SA-1110 System Bus
      • 2.1.1 StrongARM SA-1110 Overview
      • 2.1.2 Variable-Latency IO Access Overview
      • 2.1.3 Variable-Latency IO Access Cycles
        • Figure 21: SA-1110 Variable-Latency IO Read Cycle
        • Figure 22: SA-1110 Variable-Latency IO Write Cycle
  • 3 S1D13506 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signal Descriptions
  • 4 StrongARM SA-1110 to S1D13506 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of SA-1110 to S1D13506 Interface
    • 4.2 S1D13506 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Options
    • 4.3 Performance
    • 4.4 Register/Memory Mapping
      • Table 42: Register/Memory Mapping for Typical Implementation
    • 4.5 StrongARM SA-1110 Register Configuration
      • Table 43: RDFx Parameter Value versus CPU Maximum Frequency
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (S1D13506)
    • 7.2 Intel StrongARM SA-1110 Micro-processor