Document Outline

• S1D13806 TECHNICAL MANUAL
  • COMPREHENSIVE SUPPORT TOOLS
    • Documentation
    • Evaluation/Demonstration Board
  • Application Engineering Support
    • Application Engineering Support
• Product Brief
  • FEATURES
  • SYSTEM BLOCK DIAGRAM
  • DESCRIPTION
• Hardware Functional Specification
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
    • 1.1 Scope
    • 1.2 Overview Description
  • 2 Features
    • Table 21 : S1D13806 Features
  • 3 Typical System Implementation Diagrams
    • Figure 31: Typical System Diagram (Generic Bus)
    • Figure 32: Typical System Diagram (Hitachi SH-4 Bus)
    • Figure 33: Typical System Diagram (Hitachi SH-3 Bus)
    • Figure 34: Typical System Diagram (MC68K Bus 1, Motorola 16-Bit 68000)
    • Figure 35: Typical System Diagram (MC68K Bus 2, Motorola 32-Bit 68030)
    • Figure 36: Typical System Diagram (Motorola Power PC Bus)
    • Figure 37: Typical System Diagram (NEC MIPS VR41xx Bus)
    • Figure 38: Typical System Diagram (PC Card Bus)
    • Figure 39: Typical System Diagram (Philips MIPS PR31500/PR31700 Bus)
    • Figure 310: Typical System Diagram (Toshiba MIPS TX39xx Bus)
  • 4 Pins
    • 4.1 Pinout Diagram
      • Figure 41: Pinout Diagram 144-Pin QFP20 Surface Mount Packages
      • Figure 42: Pinout Diagram 220-Pin PFBGA Surface Mount Package
      • Table 41: PFBGA 220-pin Mapping
    • 4.2 Pin Description
      • 4.2.1 Host Interface
        • Table 42 : Host Interface Pin Descriptions 
      • 4.2.2 LCD Interface
        • Table 43 : LCD Interface Pin Descriptions 
      • 4.2.3 MediaPlug Interface
        • Table 44 : MediaPlug Pin Description 
      • 4.2.4 CRT Interface
        • Table 45 : CRT Interface Pin Descriptions 
      • 4.2.5 General Purpose IO
        • Table 46 : General Purpose IO Pin Descriptions 
      • 4.2.6 Configuration
        • Table 47 : Configuration Pin Descriptions 
      • 4.2.7 Miscellaneous
        • Table 48 : Miscellaneous Interface Pin Descriptions 
    • 4.3 Summary of Configuration Options
      • Table 49 : Summary of Power-On/Reset Options
    • 4.4 Multiple Function Pin Mapping
      • Table 410 : CPU Interface Pin Mapping
    • 4.5 LCD Interface Pin Mapping
      • Table 411 : LCD Interface Pin Mapping
    • 4.6 CRT/TV Interface
      • Figure 43: External Circuitry for CRT Interface
  • 5 D.C. Characteristics
    • Table 51 : Absolute Maximum Ratings
    • Table 52 : Recommended Operating Conditions
    • Table 53 : Electrical Characteristics for VDD = 3.3V typical
  • 6 A.C. Characteristics
    • 6.1 Clock Timing
      • Figure 61: Clock Input Requirement
      • Table 61 : Clock Input Requirements for BUSCLK, CLKI, CLKI2, and CLKI3 When Not Divided
      • Table 62 : Clock Input Requirements for MCLK Source when Source Divided
      • Table 63 : Clock Input Requirements for LCD PCLK, CRT/TV PCLK, or MediaPlug Source when Source D...
    • 6.2 Internal Clocks
      • Table 64: Internal Clock Requirements
    • 6.3 CPU Interface Timing
      • 6.3.1 Generic Interface Timing
        • Figure 62: Generic Interface Timing
        • Table 65 : Generic Interface Timing
      • 6.3.2 Hitachi SH-4 Interface Timing
        • Figure 63: Hitachi SH-4 Interface Timing
        • Table 66 : Hitachi SH-4 Interface Timing
      • 6.3.3 Hitachi SH-3 Interface Timing
        • Figure 64: Hitachi SH-3 Interface Timing
        • Table 67 : Hitachi SH-3 Interface Timing
      • 6.3.4 MIPS/ISA Interface Timing (e.g. NEC VR41xx)
        • Figure 65: MIPS/ISA Interface Timing
        • Table 68 : MIPS/ISA Interface Timing
      • 6.3.5 Motorola MC68K Bus 1 Interface Timing (e.g. MC68000)
        • Figure 66: Motorola MC68K Bus 1 Interface Timing
        • Table 69 : Motorola MC68K Bus 1 Interface Timing
      • 6.3.6 Motorola MC68K Bus 2 Interface Timing (e.g. MC68030)
        • Figure 67: Motorola MC68K Bus 2 Interface Timing
        • Table 610 : Motorola MC68K Bus 2 Interface Timing
      • 6.3.7 Motorola PowerPC Interface Timing (e.g. MPC8xx, MC68040, Coldfire)
        • Figure 68: Motorola PowerPC Interface Timing
        • Table 611 : Motorola PowerPC Interface Timing
      • 6.3.8 PC Card Timing (e.g. StrongARM)
        • Figure 69: PC Card Timing
        • Table 612: PC Card Timing
      • 6.3.9 Philips Interface Timing (e.g. PR31500/PR31700)
        • Figure 610: Philips Interface Timing
        • Table 613 : Philips Interface Timing
      • 6.3.10 Toshiba Interface Timing (e.g. TX39xx)
        • Figure 611: Toshiba Interface Timing
        • Table 614 : Toshiba Interface Timing
    • 6.4 Power Sequencing
      • 6.4.1 LCD Power Sequencing
        • Figure 612: LCD Panel Power-off/Power-on Timing
        • Table 615 : LCD Panel Power-off/Power-on
      • 6.4.2 Power Save Status
        • Figure 613: Power Save Status Bits and Local Bus Memory Access Relative to Power Save Mode
        • Table 616 : Power Save Status and Local Bus Memory Access Relative to Power Save Mode
        • Table 617 : SDRAM Refresh Period Selection
    • 6.5 Display Interface
      • 6.5.1 Single Monochrome 4-Bit Panel Timing
        • Figure 614: Single Monochrome 4-Bit Panel Timing
        • Figure 615: Single Monochrome 4-Bit Panel A.C. Timing
        • Table 618 : Single Monochrome 4-Bit Panel A.C. Timing
      • 6.5.2 Single Monochrome 8-Bit Panel Timing
        • Figure 616: Single Monochrome 8-Bit Panel Timing
        • Figure 617: Single Monochrome 8-Bit Panel A.C. Timing
        • Table 619 : Single Monochrome 8-Bit Panel A.C. Timing
      • 6.5.3 Single Color 4-Bit Panel Timing
        • Figure 618: Single Color 4-Bit Panel Timing
        • Figure 619: Single Color 4-Bit Panel A.C. Timing
        • Table 620 : Single Color 4-Bit Panel A.C. Timing
      • 6.5.4 Single Color 8-Bit Panel Timing (Format 1)
        • Figure 620: Single Color 8-Bit Panel Timing (Format 1)
        • Figure 621: Single Color 8-Bit Panel A.C. Timing (Format 1)
        • Table 621 : Single Color 8-Bit Panel A.C. Timing (Format 1)
      • 6.5.5 Single Color 8-Bit Panel Timing (Format 2)
        • Figure 622: Single Color 8-Bit Panel Timing (Format 2)
        • Figure 623: Single Color 8-Bit Panel A.C. Timing (Format 2)
        • Table 622 : Single Color 8-Bit Panel A.C. Timing (Format 2)
      • 6.5.6 Single Color 16-Bit Panel Timing
        • Figure 624: Single Color 16-Bit Panel Timing
        • Figure 625: Single Color 16-Bit Panel A.C. Timing
        • Table 623 : Single Color 16-Bit Panel A.C. Timing
      • 6.5.7 Dual Monochrome 8-Bit Panel Timing
        • Figure 626: Dual Monochrome 8-Bit Panel Timing
        • Figure 627: Dual Monochrome 8-Bit Panel A.C. Timing
        • Table 624 : Dual Monochrome 8-Bit Panel A.C. Timing
      • 6.5.8 Dual Color 8-Bit Panel Timing
        • Figure 628: Dual Color 8-Bit Panel Timing
        • Figure 629: Dual Color 8-Bit Panel A.C. Timing
        • Table 625 : Dual Color 8-Bit Panel A.C. Timing
      • 6.5.9 Dual Color 16-Bit Panel Timing
        • Figure 630: Dual Color 16-Bit Panel Timing
        • Figure 631: Dual Color 16-Bit Panel A.C. Timing
        • Table 626 : Dual Color 16-Bit Panel A.C. Timing
      • 6.5.10 TFT/D-TFD Panel Timing
        • Figure 632: TFT/D-TFD Panel Timing
        • Figure 633: TFT/D-TFD A.C. Timing
        • Table 627 : TFT/D-TFD A.C. Timing
      • 6.5.11 CRT Timing
        • Figure 634: CRT Timing
        • Figure 635: CRT A.C. Timing
        • Table 628 : CRT A.C. Timing
    • 6.6 TV Timing
      • 6.6.1 TV Output Timing
        • Figure 636: NTSC Video Timing
        • Figure 637: PAL Video Timing
        • Figure 638: Horizontal Timing for NTSC/PAL
        • Table 629 : Horizontal Timing for NTSC/PAL
        • Figure 639: Vertical Timing for NTSC/PAL
        • Table 630 : Vertical Timing for NTSC/PAL
    • 6.7 MediaPlug Interface Timing
      • Figure 640: MediaPlug A.C. Timing
      • Table 631: MediaPlug A.C. Timing
  • 7 Clocks
    • 7.1 Clock Overview
      • Figure 71: Clock Overview Diagram
    • 7.2 Clock Descriptions
      • 7.2.1 MCLK
      • 7.2.2 LCD PCLK
      • 7.2.3 CRT/TV PCLK
      • 7.2.4 MediaPlug Clock
        • Figure 72: MediaPlug Clock Output Signals
    • 7.3 Clock Selection
      • Table 71 : Clock Selection
    • 7.4 Clocks vs. Functions
      • Table 72: Clocks vs. Functions
  • 8 Registers
    • 8.1 Initializing the S1D13806
      • 8.1.1 Register Memory Select Bit
      • 8.1.2 SDRAM Initialization Bit
    • 8.2 Register Mapping
      • Table 81 : Register Mapping with CS# = 0 and M/R# = 0
    • 8.3 Register Set
      • Table 82 : S1D13806 Register Set
    • 8.4 Register Descriptions
      • 8.4.1 Basic Registers
      • 8.4.2 General IO Pins Registers
        • Table 83 : Media Plug/GPIO12 Pin Functionality
      • 8.4.3 Configuration Readback Register
      • 8.4.4 Clock Configuration Registers
        • Table 84 : MCLK Source Select
        • Table 85 : LCD PCLK Divide Selection
        • Table 86 : LCD PCLK Source Selection
        • Table 87 : CRT/TV PCLK Divide Selection
        • Table 88 : CRT/TV PCLK Source Selection
        • Table 89 : MediaPlug Clock Divide Selection
        • Table 810 : MediaPlug Clock Source Selection
        • Table 811 : Minimum Memory Timing Selection
      • 8.4.5 Memory Configuration Registers
        • Figure 81: SDRAM Initialization Sequence
        • Table 812 : SDRAM Refresh Rate Selection
        • Table 813 : SDRAM Timings Control Register Settings
      • 8.4.6 Panel Configuration Registers
        • Table 814 : Panel Data Width Selection
        • Table 815: Horizontal Display Width (Pixels)
        • Table 816 : LCD FPLINE Polarity Selection
        • Table 817 : LCD FPFRAME Polarity Selection
      • 8.4.7 LCD Display Mode Registers
        • Table 818: Setting SwivelView Modes
        • Table 819 : LCD Bit-per-pixel Selection
        • Table 820 : LCD Pixel Panning Selection
      • 8.4.8 CRT/TV Configuration Registers
        • Table 821: DAC Output Level Selection
      • 8.4.9 CRT/TV Display Mode Registers
        • Table 822 : CRT/TV Bit-per-pixel Selection
        • Table 823 : CRT/TV Pixel Panning Selection
      • 8.4.10 LCD Ink/Cursor Registers
        • Table 824 : LCD Ink/Cursor Selection
        • Table 825 : LCD Ink/Cursor Start Address Encoding
      • 8.4.11 CRT/TV Ink/Cursor Registers
        • Table 826 : CRT/TV Ink/Cursor Selection
        • Table 827 : CRT/TV Ink/Cursor Start Address Encoding
      • 8.4.12 BitBLT Configuration Registers
        • Table 828 : BitBLT Active Status
        • Table 829: BitBLT FIFO Words Available
        • Table 830 : BitBLT ROP Code/Color Expansion Function Selection
        • Table 831 : BitBLT Operation Selection
        • Table 832 : BitBLT Source Start Address Selection
      • 8.4.13 Look-Up Table Registers
        • Table 833 : LUT Mode Selection
      • 8.4.14 Power Save Configuration Registers
      • 8.4.15 Miscellaneous Registers
      • 8.4.16 Common Display Mode Register
        • Table 834: Setting SwivelView Modes
        • Table 835: Display Mode Selection
    • 8.5 MediaPlug Registers Descriptions
      • 8.5.1 MediaPlug Control Registers
        • Table 836: MediaPlug LCMD Read/Write Descriptions
        • Table 837: Timeout Option Delay
        • Table 838: Cable Detect and Remote Powered Status
        • Table 839: MediaPlug CMD Read/Write Descriptions
        • Table 840: MediaPlug Commands
      • 8.5.2 MediaPlug Data Registers
    • 8.6 BitBLT Data Registers Descriptions
  • 9 2D BitBLT Engine
    • 9.1 Overview
    • 9.2 BitBLT Operations
  • 10 Display Buffer
    • Table 101 : S1D13806 Addressing
    • Figure 101: Display Buffer Addressing
    • 10.1 Image Buffer
    • 10.2 Ink Layer/Hardware Cursor Buffers
    • 10.3 Dual Panel Buffer
  • 11 Display Configuration
    • 11.1 Display Mode Data Format
      • Figure 111: 4/8/16 Bit-per-pixel Format Memory Organization
    • 11.2 Image Manipulation
      • Figure 112: Image Manipulation
  • 12 Look-Up Table Architecture
    • 12.1 Monochrome Modes
      • 4 Bit-Per-Pixel Monochrome Mode
        • Figure 121: 4 Bit-Per-Pixel Monochrome Mode Data Output Path
      • 8 Bit-Per-Pixel Monochrome Mode
        • Figure 122: 8 Bit-Per-Pixel Monochrome Mode Data Output Path
      • 16 Bit-Per-Pixel Monochrome Mode
    • 12.2 Color Modes
      • 4 Bit-Per-Pixel Color Mode
        • Figure 123: 4 Bit-Per-Pixel Color Mode Data Output Path
      • 8 Bit-Per-Pixel Color Mode
        • Figure 124: 8 Bit-Per-Pixel Color Mode Data Output Path
      • 16 Bit-Per-Pixel Color Modes
  • 13 TV Considerations
    • 13.1 NTSC/PAL Operation
    • 13.2 Clock Source
      • Table 131 : Required Clock Frequencies for NTSC/PAL
    • 13.3 Filters
      • 13.3.1 Chrominance Filter (REG[05Bh] bit 5)
      • 13.3.2 Luminance Filter (REG[05Bh] bit 4)
      • 13.3.3 Anti-flicker Filter (REG[1FCh] bits [2:1])
    • 13.4 TV Output Levels
      • Figure 131: NTSC/PAL SVideo-Y (Luminance) Output Levels
      • Table 132 : NTSC/PAL SVideo-Y (Luminance) Output Levels
      • Figure 132: NTSC/PAL SVideo-C (Chrominance) Output Levels
      • Table 133 : NTSC/PAL SVideo-C (Chrominance) Output Levels
      • Figure 133: NTSC/PAL Composite Output Levels
      • Table 134 : NTSC/PAL Composite Output Levels
      • 13.4.1 TV Image Display and Positioning
        • Figure 134: NTSC/PAL Image Positioning
        • Table 135 : Minimum and Maximum Values for NTSC/PAL TV
        • Figure 135: Typical Display Dimensions and Visible Display Dimensions for NTSC and PAL
        • Table 136 : Register Values for Example NTSC/PAL Images
      • 13.4.2 TV Cursor Operation
  • 14 Ink Layer/Hardware Cursor Architecture
    • 14.1 Ink Layer/Hardware Cursor Buffers
      • Table 141 : Ink/Cursor Start Address Encoding
    • 14.2 Ink/Cursor Data Format
      • Figure 141: Ink/Cursor Data Format
      • Table 142 : Ink/Cursor Color Select
    • 14.3 Ink/Cursor Image Manipulation
      • 14.3.1 Ink Image
      • 14.3.2 Cursor Image
        • Figure 142: Unclipped Cursor Positioning
        • Figure 143: Clipped Cursor Positioning
  • 15 SwivelView�
    • 15.1 Concept
    • 15.2 90 SwivelView
      • Figure 151: Relationship Between Screen Image and 90 Rotated Image in the Display Buffer
      • 15.2.1 Register Programming
      • 15.2.2 Physical Memory Requirement
        • Table 151 : Memory Size Required for SwivelView 90 and 270
      • 15.2.3 Limitations
    • 15.3 180 SwivelView
      • 15.3.1 Register Programming
      • 15.3.2 Physical Memory Requirement
      • 15.3.3 Limitations
    • 15.4 270 SwivelView
      • 15.4.1 Register Programming
      • 15.4.2 Physical Memory Requirement
      • 15.4.3 Limitations
  • 16 EPSON Independent Simultaneous Display (EISD)
    • 16.1 Registers
    • 16.2 Display Mapping
    • 16.3 Bandwidth Limitation
  • 17 MediaPlug Interface
    • 17.1 Revision Code
    • 17.2 How to enable the MediaPlug Slave
    • 17.3 MediaPlug Interface Pin Mapping
      • Table 171: MediaPlug Interface Pin Mapping
  • 18 Clocking
    • 18.1 Frame Rate Calculation
      • 18.1.1 LCD Frame Rate Calculation
      • 18.1.2 CRT Frame Rate Calculation
      • 18.1.3 TV Frame Rate Calculation
    • 18.2 Example Frame Rates
      • 18.2.1 Frame Rates for 640x480 with EISD Disabled
        • Table 181: Frame Rates for 640x480 with EISD Disabled
      • 18.2.2 Frame Rates for 800x600 with EISD Disabled
        • Table 182: Frame Rates for 800x600 with EISD Disabled
      • 18.2.3 Frame Rates for 1024x768 with EISD Disabled
        • Table 183: Frame Rates for 1024x768 with EISD Disabled
      • 18.2.4 Frame Rates for LCD and CRT (640x480) with EISD Enabled
        • Table 184: Frame Rates for LCD and CRT (640x480) with EISD Enabled
      • 18.2.5 Frame Rates for LCD and CRT (800x600) with EISD Enabled
        • Table 185: Frame Rates for LCD and CRT (800x600) with EISD Enabled
      • 18.2.6 Frame Rates for LCD and CRT (1024x768) with EISD Enabled
        • Table 186: Frame Rates for LCD and CRT (1024x768) with EISD Enabled
      • 18.2.7 Frame Rates for LCD and NTSC TV with EISD Enabled
        • Table 187: Frame Rates for LCD and NTSC TV with EISD Enabled
      • 18.2.8 Frame Rates for LCD and PAL TV with EISD Enabled
        • Table 188: Frame Rates for LCD and PAL TV with EISD Enabled
  • 19 Power Save Mode
    • 19.1 Overview
    • 19.2 Power Save Status Bits
    • 19.3 Power Save Mode Summary
      • Table 191: Power Save Mode Summary
  • 20 Mechanical Data
    • Figure 201: Mechanical Drawing 144-pin QFP20
    • Figure 202: Mechanical Drawing 220-pin PFBGA
  • 21 References
  • 22 Sales and Technical Support
• Programming Notes and Examples
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Initialization
    • Table 21: S1D13806 Initialization Sequence
  • 3 Memory Models
    • 3.1 Display Buffer Location
    • 3.2 Memory Organization for 4 Bpp (16 Colors/16 Gray Shades)
      • Figure 31: Pixel Storage for 4 Bpp in One Byte of Display Buffer
    • 3.3 Memory Organization for 8 Bpp (256 Colors/16 Gray Shades)
      • Figure 32: Pixel Storage for 8 Bpp in One Byte of Display Buffer
    • 3.4 Memory Organization for 16 Bpp (65536 Colors/64 Gray Shades)
      • Figure 33: Pixel Storage for 16 Bpp in Two Bytes of Display Buffer
  • 4 Look-Up Table (LUT)
    • 4.1 Registers
    • 4.2 Look-Up Table Organization
      • Table 41: Look-Up Table Configurations
      • 4.2.1 Color Modes
        • Table 42: Suggested LUT Values to Simulate VGA Default 16 Color Palette
        • Table 43: Suggested LUT Values to Simulate VGA Default 256 Color Palette
      • 4.2.2 Gray Shade Modes
        • Table 44: Suggested LUT Values for 4 Bpp Gray Shade
  • 5 Virtual Displays
    • 5.1 Virtual Display
      • Figure 51: Viewport Inside a Virtual Display
      • 5.1.1 Registers
      • 5.1.2 Examples
    • 5.2 Panning and Scrolling
      • 5.2.1 Registers
        • Table 51: Number of Pixels Panned When Start Address Changed By 1
        • Table 52: Active Pixel Pan Bits
      • 5.2.2 Examples
  • 6 Power Save Mode
    • 6.1 Overview
    • 6.2 Registers
      • 6.2.1 Enabling Power Save Mode
      • 6.2.2 Power Save Status Bits
    • 6.3 Enabling Power Save Mode
    • 6.4 Disabling Power Save Mode
  • 7 LCD Power Sequencing
    • 7.1 Enabling the LCD Panel
    • 7.2 Disabling the LCD Panel
  • 8 Hardware Cursor/Ink Layer
    • 8.1 Introduction
    • 8.2 Registers
      • Table 81: Ink/Cursor Mode
      • Table 82: Cursor/Ink Start Address Encoding
    • 8.3 Initialization
      • 8.3.1 Memory Considerations
      • 8.3.2 Examples
        • Table 83: LCD Hardware Cursor Initialization Sequence
        • Table 84: Ink Layer Start Address Encoding
        • Table 85: LCD Ink Layer Initialization Sequence
    • 8.4 Writing Cursor/Ink Layer Images
      • 8.4.1 Hardware Cursor/Ink Layer Data Format
        • Figure 81: Hardware Cursor/Ink Layer Data Format
        • Table 86: Ink/Cursor Color Select
      • 8.4.2 Cursor Image
      • 8.4.3 Ink Layer Image
    • 8.5 Cursor Movement
      • 8.5.1 Move Cursor in Landscape Mode (no rotation)
      • 8.5.2 Move Cursor in SwivelView 90 Rotation
      • 8.5.3 Move Cursor in SwivelView 180 Rotation
      • 8.5.4 Move Cursor in SwivelView 270 Rotation
  • 9 SwivelView�
    • 9.1 SwivelView 90
    • 9.2 SwivelView 180
    • 9.3 SwivelView 270
    • 9.4 SwivelView Registers
      • Table 91: SwivelView Enable Bits
      • 9.4.1 SwivelView 0 (Landscape)
      • 9.4.2 SwivelView 90
      • 9.4.3 SwivelView 180
      • 9.4.4 SwivelView 270
    • 9.5 Limitations
    • 9.6 Simultaneous Display Considerations
    • 9.7 Examples
  • 10 2D BitBLT Engine
    • 10.1 Registers
      • Table 101: BitBLT ROP Code/Color Expansion Function Selection
      • Table 102: BitBLT Operation Selection
      • Table 103: BitBLT Source Start Address Selection
    • 10.2 BitBLT Descriptions
      • 10.2.1 Write BitBLT with ROP
        • Table 104: Possible BitBLT FIFO Writes
      • 10.2.2 Color Expand BitBLT
        • Table 105: Possible BitBLT FIFO Writes
      • 10.2.3 Color Expand BitBLT With Transparency
      • 10.2.4 Solid Fill BitBLT
      • 10.2.5 Move BitBLT in a Positive Direction with ROP
        • Figure 101: Move BitBLT Usage
      • 10.2.6 Move BitBLT in Negative Direction with ROP
      • 10.2.7 Transparent Write BitBLT
        • Table 106: Possible BitBLT FIFO Writes
      • 10.2.8 Transparent Move BitBLT in Positive Direction
      • 10.2.9 Pattern Fill BitBLT with ROP
      • 10.2.10 Pattern Fill BitBLT with Transparency
      • 10.2.11 Move BitBLT with Color Expansion
      • 10.2.12 Transparent Move BitBLT with Color Expansion
      • 10.2.13 Read BitBLT
        • Table 107: Possible BitBLT FIFO Reads
    • 10.3 S1D13806 BitBLT Synchronization
    • 10.4 S1D13806 BitBLT Known Limitations
    • 10.5 Sample Code
  • 11 CRT/TV Considerations
    • 11.1 CRT Considerations
      • 11.1.1 Generating CRT timings with 1386CFG
      • 11.1.2 DAC Output Level Selection
      • 11.1.3 Examples
    • 11.2 TV Considerations
      • 11.2.1 NTSC Timings
      • 11.2.2 PAL Timings
      • 11.2.3 TV Filters
      • 11.2.4 Examples
    • 11.3 Simultaneous Display
  • 12 MediaPlug
    • 12.1 Programming
    • 12.2 Considerations
  • 13 Identifying the S1D13806
  • 14 Hardware Abstraction Layer (HAL)
    • 14.1 API for 1386HAL
      • Table 141: HAL Functions
    • 14.2 Initialization
      • 14.2.1 General HAL Support
      • 14.2.2 Advanced HAL Functions
      • 14.2.3 Surface Support
      • 14.2.4 Register Access
      • 14.2.5 Memory Access
      • 14.2.6 Color Manipulation
      • 14.2.7 Virtual Display
      • 14.2.8 Drawing
      • 14.2.9 Hardware Cursor
      • 14.2.10 Ink Layer
      • 14.2.11 Register/Display Memory
    • 14.3 Porting LIBSE to a new target platform
      • Figure 141: Components needed to build 1386 HAL application
      • 14.3.1 Building the LIBSE library for SH3 target example
      • 14.3.2 Building a complete application for the target example
  • 15 Sample Code
• Register Summary
  • REG[000h] Revision Code Register 2 (For S1D13806: Product Code=000111b, Revision Code=00b) RO
  • REG[001h] Miscellaneous Register 1/0 RW
  • REG[004h] General IO Pins Configuration Register 0 1/0 RW
  • REG[005h] General IO Pins Configuration Register 1 3 1/0 RW
  • REG[008h] General IO Pins Control Register 0 RW
  • REG[009h] General IO Pins Control Register 1 RW
  • REG[00Ch] Configuration Status Register R0
  • REG[010h] Memory Clock Configuration Register 4 RW
  • REG[014h] LCD Pixel Clock Configuration Register 5, 6 RW
  • REG[018h] CRT/TV Pixel Clock Configuration Register 7, 8 RW
  • REG[01Ch] MediaPlug Clock Configuration Register 9, 10 RW
  • REG[01Eh] CPU To Memory Wait State Select Register 11 RW
  • REG[020h] Memory Configuration Register RW
  • REG[021h] DRAM Refresh Rate Register 12 RW
  • REG[02Ah] DRAM Timing Control Register 0 13 RW
  • REG[02Bh] DRAM Timing Control Register 1 13 RW
  • REG[030h] Panel Type Register 14 RW
  • REG[031h] MOD Rate Register RW
  • REG[032h] LCD Horizontal Display Width Register RW
  • REG[034h] LCD Horizontal Non-Display Period Register RW
  • REG[035h] TFT FPLINE Start Position Register RW
  • REG[036h] TFT FPLINE Pulse Width Register 15 RW
  • REG[038h] LCD Vertical Display Height Register 0 RW
  • REG[039h] LCD Vertical Display Height Register 1 RW
  • REG[03Ah] LCD Vertical Non-Display Period Register RW
  • REG[03Bh] TFT FPFRAME Start Position Register RW
  • REG[03Ch] TFT FPFRAME Pulse Width Register 16 RW
  • REG[03Eh] LCD Line Count Register 0 RO
  • REG[040h] LCD Display Mode Register 17 RW
  • REG[041h] LCD Miscellaneous Register RW
  • REG[042h] LCD Display Start Address Register 0 RW
  • REG[043h] LCD Display Start Address Register 1 RW
  • REG[044h] LCD Display Start Address Register 2 RW
  • REG[046h] LCD Memory Address Offset Register 0 RW
  • REG[047h] LCD Memory Address Offset Register 1 RW
  • REG[048h] LCD Pixel Panning Register 18 RW
  • REG[04Ah] LCD Display FIFO High Threshold Control Register RW
  • REG[04Bh] LCD Display FIFO Low Threshold Control Register RW
  • REG[050h] CRT/TV Horizontal Display Width Register RW
  • REG[052h] CRT/TV Horizontal Non-Display Period Register RW
  • REG[053h] CRT/TV HRTC Start Position Register RW
  • REG[054h] CRT/TV HRTC Pulse Width Register RW
  • REG[056h] CRT/TV Vertical Display Height Register 0 RW
  • REG[057h] CRT/TV Vertical Display Height Register 1 RW
  • REG[058h] CRT/TV Vertical Non-Display Period Register RW
  • REG[059h] CRT/TV VRTC Start Position Register RW
  • REG[05Ah] CRT VRTC Pulse Width Register RW
  • REG[05Bh] TV Output Control Register 19 RW
  • REG[05Eh] CRT/TV Line Count Register 0 RW
  • REG[060h] CRT/TV Display Mode Register 20 RW
  • REG[062h] CRT/TV Display Start Address Register 0 RW
  • REG[063h] CRT/TV Display Start Address Register 1 RW
  • REG[064h] CRT/TV Display Start Address Register 2 RW
  • REG[066h] CRT/TV Memory Address Offset Register 0 RW
  • REG[067h] CRT/TV Memory Address Offset Register 1 RW
  • REG[068h] CRT/TV Pixel Panning Register 21 RW
  • REG[06Ah] CRT/TV Display FIFO High Threshold Control Register RW
  • REG[06Bh] CRT/TV Display FIFO Low Threshold Control Register RW
  • REG[070h] LCD Ink/Cursor Control Register 22 RW
  • REG[071h] LCD Ink/Cursor Start Address Register 23 RW
  • REG[072h] LCD Cursor X Position Register 0 RW
  • REG[073h] LCD Curxor X Position Register 1 RW
  • REG[074h] LCD Cursor Y Position Register 0 RW
  • REG[075h] LCD Cursor Y Position Register 1 RW
  • REG[076h] LCD Ink/Cursor Blue Color 0 Register RW
  • REG[077h] LCD Ink/Cursor Green Color 0 Register RW
  • REG[078h] LCD Ink/Cursor Red Color 0 Register RW
  • REG[07Ah] LCD Ink/Cursor Blue Color 1 Register RW
  • REG[07Bh] LCD Ink/Cursor Green Color 1 Register RW
  • REG[07Ch] LCD Ink/Cursor Red Color 1 Register RW
  • REG[07Eh] LCD Ink/Cursor FIFO Thrshold Register RW
  • REG[080h] CRT/TV Ink/Cursor Control Register 24 RW
  • REG[081h] CRT/TV Ink/Cursor Start Address Register 25 RW
  • REG[082h] CRT/TV Cursor X Position Register 0 RW
  • REG[083h] CRT/TV Cursor X Position Register 1 RW
  • REG[084h] CRT/TV Cursor Y Position Register 0 RW
  • REG[085h] CRT/TV Cursor Y Position Register 1 RW
  • REG[086h] CRT/TV Ink/Cursor Blue Color 0 Register RW
  • REG[087h] CRT/TV Ink/Cursor Green Color 0 Register RW
  • REG[088h] CRT/TV Ink/Cursor Red Color 0 Register RW
  • REG[08Ah] CRT/TV Ink/Cursor Blue Color 1 Register RW
  • REG[08Bh] CRT/TV Ink/Cursor Green Color 1 Register RW
  • REG[08Ch] CRT/TV Ink/Cursor Red Color 1 Register RW
  • REG[08Eh] CRT/TV Ink/Cursor FIFO Threshold Register RW
  • REG[100h] BitBLT Control Register 0 26, 27 RW
  • REG[101h] BitBLT Control Register 1 RW
  • REG[102h] BitBLT ROP Code/Color Expansion Register 28 RW
  • REG[103h] BitBLT Operation Register 29 RW
  • REG[104h] BitBLT Source Start Address Register 0 30 RW
  • REG[105h] BitBLT Source Start Address Register 1 30 RW
  • REG[106h] BitBLT Source Start Address Register 2 30 RW
  • REG[108h] BitBLT Destination Start Address Register 0 RW
  • REG[109h] BitBLT Destination Start Address Register 1 RW
  • REG[10Ah] BitBLT Destination Start Address Register 2 RW
  • REG[10Ch] BitBLT Memory Address Offset Register 0 RW
  • REG[10Dh] BitBLT Memory Address Offset Register 1 RW
  • REG[110h] BitBLT Width Register 0 RW
  • REG[111h] BitBLT Width Register 1 RW
  • REG[112h] BitBLT Height Register 0 RW
  • REG[113h] BitBLT Height Register 1 RW
  • REG[114h] BitBLT Backgroud Color Register 0 RW
  • REG[115h] BitBLT Background Color Register 1 RW
  • REG[118h] BitBLT Foreground Color Register 0 RW
  • REG[119h] BitBLT Foreground Color Register 1 RW
  • REG[1E0h] Look-Up Table Mode Register 31 RW
  • REG[1E2h] Look-Up Table Address Register RW
  • REG[1E4h] Look-Up Table Data Register RW
  • REG[1F0h] Power Save Configuration Register RW
  • REG[1F1h] Power Save Status Register RO
  • REG[1F4h] CPU-to-Memory Access Watchdog Timer Register RW
  • REG[1FCh] Display Mode Register 32 RW
  • REG[1000h] MediaPlug LCMD Register RW
  • REG[1002h] MediaPlug Reserved LCMD Register RW
  • REG[1004h] MediaPlug CMD Register RW
  • REG[1006h] MediaPlug Reserved CMD Register RW
  • REG[1008h] to REG[1FFEh], even address MediaPlug Data Registers RW
  • A20-A0 = 100000h-1FFFFEh, even address BitBLT Data Register 0 RW
• 13806CFG Configuration Program
  • Table of Contents
  • 13806CFG
    • S1D13806 Supported Evaluation Platforms
    • Installation
    • Usage
    • 13806CFG Configuration Tabs
      • General Tab
      • Preferences Tab
      • Clocks Tab
      • Panel Tab
      • Panel Power Tab
      • CRT/TV Tab
      • Registers Tab
    • 13806CFG Menus
      • Open...
      • Save
      • Save As...
      • Configure Multiple
      • Export
      • Enable Tooltips
      • ERD on the Web
      • About 13806CFG
    • Comments
• 13806SHOW Demonstration Program
  • 13806SHOW
    • S1D13806 Supported Evaluation Platforms
    • Installation
    • Usage
    • Display Surfaces
      • Table 1: Display Surfaces
    • 13806SHOW Examples
      • Using 13806SHOW For Demonstration
      • Using 13806SHOW For Testing
    • Comments
    • Program Messages
• 13806PLAY Diagnostic Utility
  • 13806PLAY
    • S1D13806 Supported Evaluation Platforms
    • Installation
    • Usage
    • Commands
      • Table 1: iCrtTv Selection
    • 13806PLAY Example
    • Scripting
    • Comments
    • Program Messages
• 13806BMP Demonstration Program
  • 13806BMP
    • S1D13806 Supported Evaluation Platforms
    • Installation
    • Usage
    • Display Surfaces
      • Table 1: Display Surfaces
    • 13806BMP Examples
    • Comments
    • Program Messages
• 13806FILT Test Utility
  • 13806FILT
    • S1D13806 Supported Evaluation Platforms
    • Installation
    • Usage
    • Filter Dialog Box
      • Figure 1: Filter Dialog Box
    • Filter Descriptions
      • Anti-flicker Filter
      • Chrominance Filter
      • Luminance Filter
    • Comments
• 13806SWIVEL Demonstration Utility
  • 13806SWIVEL
    • S1D13806 Supported Evaluation Platforms
    • Installation
    • Usage
    • Example
    • Comments
• Windows� CE 2.x Display Drivers
  • WINDOWS� CE 2.x DISPLAY DRIVERS
    • Example Driver Builds
    • Installation for CEPC Environment
    • Configuration
      • Compile Switches
      • Mode File
    • Comments
• Wind River WindML v2.0 Display Drivers
  • Wind River WindML v2.0 DISPLAY DRIVERS
    • Building a WindML v2.0 Display Driver
      • 1. Create a working directory and unzip the WindML display driver into it.
      • 2. Configure for the target execution model.
      • 3. Build a boot ROM image.
      • 4. Create a bootable disk (in drive A:).
      • 5. If necessary, generate a new mode0.h configuration file.
      • 6. Build the WindML v2.0 library.
      • 7. Open the S1D13506 workspace.
      • 8. Add support for single line comments.
        • a. In the Tornado �Workspace Views� window, click on the �Builds� tab.
        • b. Expand the �8bpp Builds� (or �16bpp Builds�) view by clicking on the �+� next to it. The expan...
        • c. Select the �C/C++ compiler� tab to display the command switches used in the build. Remove the ...
      • 9. Compile the VxWorks image.
      • 10. Copy the VxWorks file to the diskette.
      • 11. Start the VxWorks demo.
• Wind River UGL v1.2 Display Drivers
  • Wind River UGL v1.2 Display Drivers
    • Building a UGL v1.2 Display Driver
      • 1. Create a working directory and unzip the UGL display driver into it.
      • 2. Configure for the target execution model.
      • 3. Build a boot ROM image.
      • 4. Create a bootable disk (in drive A:).
      • 5. If necessary, generate a new mode0.h configuration file.
      • 6. Open the S1D13806 workspace.
      • 7. Add support for single line comments.
        • a. In the Tornado �Workspace� window, click on the �Builds� tab.
        • b. Expand the �8bpp Builds� (or �16bpp Builds�) view by clicking on the �+� next to it. The expan...
        • c. Select the �C/C++ compiler� tab to display the command switches used in the build. Remove the ...
      • 8. Compile the VxWorks image.
      • 9. Copy the VxWorks file to the diskette.
      • 10. Start the VxWorks demo.
• Linux Console Driver
  • Linux Console Driver
    • Building the Console Driver for Linux Kernel 2.2.x
      • 1. Acquire the Linux kernel source code.
      • 2. Unzip the console driver files.
      • 3. Copy the console driver files to the build directory.
      • 4. Modify s1d13806.h
      • 5. Configure the video options.
      • 6. Compile and install the kernel
      • 7. Boot to the Linux operating system
    • Building the Console Driver for Linux Kernel 2.4.x
      • 1. Acquire the Linux kernel source code.
      • 2. Unzip the console driver files.
      • 3. Copy the console driver files to the build directory. Make the directory /usr/src/linux/driver...
      • 4. Modify s1d13806.h
      • 5. Configure the video options.
      • 6. Compile and install the kernel
      • 7. Boot to the Linux operating system
• QNX Photon v2.0 Display Driver
  • QNX Photon v2.0 Display Driver
    • Building the Photon v2.0 Display Driver
      • Unpack the Graphics Driver Development Kit Archive
      • Configure the Driver
      • Build the Driver
      • Installing the Driver
      • Run the Driver
    • Comments
• Windows� CE 3.x Display Drivers
  • WINDOWS� CE 3.x DISPLAY DRIVERS
    • Example Driver Builds
    • Installation for CEPC Environment
    • Configuration
      • Compile Switches
      • Mode File
      • Resource Management Issues
    • Comments
• S1D13XXX 32-Bit Windows Device Driver Installation Guide
  • S1D13XXX 32-Bit Windows Device Driver Installation Guide
    • Driver Requirements
    • Installation
      • Windows NT Version 4.0
      • Windows 2000
      • Windows 98/ME
      • Windows 95 OSR2
      • Previous Versions of Windows 95
• S5U13806B00C Evaluation Board User Manual
  • Table of Contents
  • List of Tables
  • List Of Figures
  • 1 Introduction
  • 2 Features
  • 3 Installation and Configuration
    • 3.1 Configuration DIP Switches
      • Figure 31: Configuration DIP Switch (S1) Location
      • Table 31: Configuration DIP Switch Settings
    • 3.2 Configuration Jumpers
      • Table 32: Jumper Summary
      • Figure 32: Configuration Jumper (JP1) Location
      • Figure 33: Configuration Jumper (JP2) Location
      • Figure 34: Configuration Jumper (JP3) Location
  • 4 CPU Host Interface
    • 4.1 PCI Bus Support
      • Table 41: S1D13806 Memory Mapping onto 4M byte PCI Address Block
      • 4.1.1 On-Board PCI Configuration Registers
        • Table 42: PCI Configuration Register Read Values
        • Table 43: PCI Configuration Register Write Values
      • 4.1.2 Utility Software
    • 4.2 Non-PCI Host Interface Support
      • 4.2.1 CPU Interface Pin Mapping
        • Table 44: CPU Interface Pin Mapping
    • 4.3 External CPU Host Connector Pin Mapping
      • Table 45: External CPU Host Connector (H1) Pinout
      • Table 46: External CPU Host Connector (H2) Pinout
  • 5 LCD Interface
    • 5.1 LCD Connector Pin Mapping
      • Table 51: LCD Signal Connector (H3)
    • 5.2 Voltage Translation Buffers
    • 5.3 Adjustable LCD Panel Positive Supply (VDDH)
    • 5.4 Adjustable LCD Panel Negative Power Supply (VLCD)
    • 5.5 LCD Power Sequencing
  • 6 CRT/TV Interface
    • 6.1 CRT/TV Connectors Pin Mapping
      • Table 61: CRT/TV Connectors Pin Mapping
    • 6.2 DAC Output Level Select for CRT
  • 7 MediaPlug Interface (for WINNOV Videum�Cam)
    • 7.1 MediaPlug Interface Pin Mapping
      • Table 71: MediaPlug Connector (J1) Pin Mapping
  • 8 Clock Synthesizer and Clock Options
    • Figure 81: Symbolic Clock Synthesizer Connections
    • 8.1 Clock Programming
  • 9 References
    • 9.1 Documents
    • 9.2 Document Sources
  • 10 Parts List
    • Table 101: Parts List
  • 11 Schematic Diagrams
    • Figure 111: S5U13806B00C Schematics (1 of 8)
    • Figure 112: S5U13806B00C Schematics (2 of 8)
    • Figure 113: S5U13806B00C Schematics (3 of 8)
    • Figure 114: S5U13806B00C Schematics (4 of 8)
    • Figure 115: S5U13806B00C Schematics (5 of 8)
    • Figure 116: S5U13806B00C Schematics (6 of 8)
    • Figure 117: S5U13806B00C Schematics (7 of 8)
    • Figure 118: S5U13806B00C Schematics (8 of 8)
  • 12 PCB Layout
    • Figure 121: PCB Layout
  • 13 Technical Support
    • 13.1 EPSON LCD/CRT Controllers (S1D13806)
• Interfacing to the PC Card Bus
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the PC Card Bus
    • 2.1 The PC Card System Bus
      • 2.1.1 PC Card Overview
      • 2.1.2 Memory Access Cycles
        • Figure 21: PC Card Read Cycle
        • Figure 22: PC Card Write Cycle
  • 3 S1D13806 Host Bus Interface
    • 3.1 PC Card Host Bus Interface Pin Mapping
      • Table 31: PC Card Host Bus Interface Pin Mapping
    • 3.2 PC Card Host Bus Interface Signals
  • 4 PC Card to S1D13806 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of PC Card to S1D13806 Interface
    • 4.2 S1D13806 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Options
    • 4.3 Performance
    • 4.4 Register/Memory Mapping
      • Table 42: Register/Memory Mapping for Typical Implementation
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 Epson LCD/CRT Controllers (S1D13806)
    • 7.2 PC Card Standard
• Power Consumption
  • 1 S1D13806 Power Consumption
    • 1.1 Conditions
      • Table 11: S1D13806ES Total Power Consumption in mW
  • 2 Summary
• Interfacing to the NEC VR4102/VR4111� Microprocessors
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the VR4102/VR4111
    • 2.1 The NEC VR4102/VR4111 System Bus
      • 2.1.1 Overview
      • 2.1.2 LCD Memory Access Cycles
        • Figure 21: NEC VR4102/VR4111 Read/Write Cycles
  • 3 S1D13806 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signal Descriptions
  • 4 VR4102/VR4111 to S1D13806 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of NEC VR4102/VR4111 to S1D13806 Interface
    • 4.2 S1D13806 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Options
    • 4.3 NEC VR4102/VR4111 Configuration
    • 4.4 Register/Memory Mapping
      • Table 42: Register/Memory Mapping for Typical Implementation
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (S1D13806)
    • 7.2 NEC Electronics Inc. (VR4102/VR4111).
• Interfacing to the Motorola MPC821 Microprocessor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the MPC821
    • 2.1 The MPC8xx System Bus
    • 2.2 MPC821 Bus Overview
      • 2.2.1 Normal (Non-Burst) Bus Transactions
        • Figure 21: Power PC Memory Read Cycle
        • Figure 22: Power PC Memory Write Cycle
    • 2.3 Memory Controller Module
      • 2.3.1 General-Purpose Chip Select Module (GPCM)
      • 2.3.2 User-Programmable Machine (UPM)
  • 3 S1D13806 Host Bus Interface
    • 3.1 PowerPC Host Bus Interface Pin Mapping
      • Table 31: PowerPC Host Bus Interface Pin Mapping
    • 3.2 PowerPC Host Bus Interface Signals
  • 4 MPC821 to S1D13806 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of MPC821 to S1D13806 Interface
    • 4.2 Hardware Connections
      • Table 41: List of Connections from MPC821ADS to S1D13806 
    • 4.3 S1D13806 Hardware Configuration
      • Table 42: Summary of Power-On/Reset Options
    • 4.4 Register/Memory Mapping
      • Table 43: Register/Memory Mapping for Typical Implementation
    • 4.5 MPC821 Chip Select Configuration
    • 4.6 Test Software
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (S1D13806)
    • 7.2 Motorola MPC821 Processor
• Interfacing to the Philips MIPS PR31500/PR31700 Processor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the PR31500/PR31700
  • 3 S1D13806 Host Bus Interface
    • 3.1 PR31500/PR31700 Host Bus Interface Pin Mapping
      • Table 31: PR31500/PR31700 Host Bus Interface Pin Mapping
    • 3.2 PR31500/PR31700 Host Bus Interface Signals
  • 4 Direct Connection to the Philips PR31500/PR31700
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of Direct Connection
    • 4.2 S1D13806 Configuration
      • Table 41: Summary of Power-On/Reset Options
    • 4.3 Memory Mapping and Aliasing
      • Table 42: PR31500/PR31700 to PC Card Slots Address Remapping for Direct Connection
  • 5 System Design Using the IT8368E PC Card Buffer
    • 5.1 Hardware Description
      • Figure 51: IT8368E Implementation Block Diagram
    • 5.2 IT8368E Configuration
    • 5.3 S1D13806 Configuration
  • 6 Software
  • 7 References
    • 7.1 Documents
    • 7.2 Document Sources
  • 8 Technical Support
    • 8.1 EPSON LCD/CRT Controllers (S1D13806)
    • 8.2 Philips MIPS PR31500/PR31700 Processor
    • 8.3 ITE IT8368E
• Interfacing to the Toshiba MIPS TX3912 Processor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the TX3912
  • 3 S1D13806 Host Bus Interface
    • 3.1 TX3912 Host Bus Interface Pin Mapping
      • Table 31: TX3912 Host Bus Interface Pin Mapping
    • 3.2 TX3912 Host Bus Interface Signals
  • 4 Direct Connection to the Toshiba TX3912
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of Direct Connection
    • 4.2 S1D13806 Configuration
      • Table 41: Summary of Power-On/Reset Options
    • 4.3 Memory Mapping and Aliasing
      • Table 42: TX3912 to PC Card Slots Address Remapping for Direct Connection
  • 5 System Design Using the IT8368E PC Card Buffer
    • 5.1 Hardware Description
      • Figure 51: IT8368E Implementation Block Diagram
    • 5.2 IT8368E Configuration
    • 5.3 S1D13806 Configuration
  • 6 Software
  • 7 References
    • 7.1 Documents
    • 7.2 Document Sources
  • 8 Technical Support
    • 8.1 EPSON LCD/CRT Controllers (S1D13806)
    • 8.2 Toshiba MIPS TX3912 Processor
    • 8.3 ITE IT8368E
• Interfacing to the NEC VR4121� Microprocessor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the NEC VR4121
    • 2.1 The NEC VR4121 System Bus
      • 2.1.1 Overview
      • 2.1.2 LCD Memory Access Cycles
        • Figure 21: NEC VR4121 Read/Write Cycles
  • 3 S1D13806 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signal Descriptions
  • 4 VR4121 to S1D13806 Interface
    • 4.1 Hardware Description
      • Figure 41: NEC VR4121 to S1D13806 Configuration Schematic
    • 4.2 S1D13806 Configuration
      • Table 41: Summary of Power-On/Reset Options
    • 4.3 NEC VR4121 Configuration
    • 4.4 Register/Memory Mapping
      • Table 42: Register/Memory Mapping for Typical Implementation
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 Epson LCD/CRT Controllers (S1D13806)
    • 7.2 NEC Electronics Inc. (VR4121).
• Interfacing to the StrongARM SA-1110 Processor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the StrongARM SA-1110 Bus
    • 2.1 The StrongARM SA-1110 System Bus
      • 2.1.1 StrongARM SA-1110 Overview
      • 2.1.2 Variable-Latency IO Access Overview
      • 2.1.3 Variable-Latency IO Access Cycles
        • Figure 21: SA-1110 Variable-Latency IO Read Cycle
        • Figure 22: SA-1110 Variable-Latency IO Write Cycle
  • 3 S1D13806 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signal Descriptions
  • 4 StrongARM SA-1110 to S1D13806 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of SA-1110 to S1D13806 Interface
    • 4.2 S1D13806 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Options
    • 4.3 Performance
    • 4.4 StrongARM SA-1110 Register Configuration
      • Table 42: RDFx Parameter Value versus CPU Maximum Frequency
    • 4.5 Register/Memory Mapping
      • Table 43: Register/Memory Mapping for Typical Implementation
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (S1D13806)
    • 7.2 Intel StrongARM SA-1110 Processor
• Interfacing to the Intel Cotulla Application Processor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the Intel Cotulla Bus
    • 2.1 The Intel Cotulla Memory Bus
      • 2.1.1 Intel Cotulla Overview
      • 2.1.2 Variable-Latency IO Access Overview
      • 2.1.3 Variable-Latency IO Access Cycles
        • Figure 21 Cotulla Variable-Latency IO Read Cycle
        • Figure 22 Cotulla Variable-Latency IO Write Cycle
  • 3 S1D13806 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31 Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signal Descriptions
  • 4 Intel Cotulla to S1D13806 Interface
    • 4.1 Hardware Description
      • Figure 41 Typical Implementation of Cotulla to S1D13806 Interface
    • 4.2 S1D13806 Hardware Configuration
      • Table 41 Summary of Power-On/Reset Options
    • 4.3 Performance
    • 4.4 Intel Cotulla Register Configuration
    • 4.5 Register/Memory Mapping
      • Table 42 Register/Memory Mapping for Typical Implementation
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (S1D13806)
    • 7.2 Intel Cotulla Processor