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Электронный компонент: S1L32162/163

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1
Master
2-layer Metal
S1L30182 S1L30302 S1L30422 S1L30552 S1L30752 S1L31092 S1L31252 S1L32162
Features
3-layer Meta S1L30183 S1L30303 S1L30423 S1L30553 S1L30753 S1L31093 S1L31253 S1L32163
Total BCs
Dual Power Supply
18,544
30,846
42,262
55,341
75,450
109,080
125,836
216,216
(Raw Gates)
Single Power Supply
23,572
37,232
49,680
63,784
85,251
120,802
138,400
232,582
Usable BCs 2-layer Metal 2-layer Metal
9,272
15,423
19,863
26,010
33,952
49,086
54,109
86,486
(Dual Power Supply)
3-layer Metal
16,318
26,219
35,077
44,272
58,851
81,810
94,377
151,351
Usable BCs 2-layer Metal 2-layer Meta
11,786
18,616
23,349
29,978
38,362
54,360
59,512
93,032
(Single Power Supply) 3-layer Metal
20,743
31,647
41,234
51,027
66,495
90,601
103,800
162,807
Number of PADs
128
160
184
208
240
256
304
376
Propagation
Internal Gates
tpd = 0.25ns (standard at 5.0V), tpd = 0.33ns (standard at 3.3V)
Delay
Input Buffers
tpd = 0.48ns (standard at 5.0V), tpd = 0.63ns (standard at 3.3V)
Output Buffers
tpd = 2.08ns (standard at 5.0V), tpd = 2.86ns (standard at 3.3V) CL = 50pF
I/O Level
CMOS, TTL, PCI
Input Mode
TTL, CMOS, Pull-up/Pull-down, schmitt, 3.0/3.3/5.0V Level interface (Level shifter)
Output Mode
Normal, open drain, 3-state, Bi-directional, 3.0/3.3/5.0V Level interface (Level shifter)
PF757-02
High Speed Gate Array
S1L30000 Series
s
DESCRIPTION
The S1L30000 Series is an SOG-type CMOS gate array featuring the very high-speed operations, high density,
and high output drive capability. This series has a full lineup of gate arrays to cover 18,544 to 216,216 gates for
the large-scale, and high-speed systems. They can drive with both +5V and +3V supply voltages.
This series also has a built-in level shifter to provide dual-power interfacing in various low-voltage applications. The
I/O cells supporting the PCI Revision 2.0 are available for PCs and peripheral equipments. Also, the micro-ampere
order, low-noise output cells are available for portable equipments and instruments of various applications.
s
FEATURES
q
Super-high density (adopting 0.6
m silicon gate CMOS with 2 and 3-metal layers)
q
High-speed operation (operation delay of internal gate = 0.25ns at 5.0V, 2-input power NAND standard)
q
Selectable supply voltage: 5.0V, 3.3V, 3.0V and built-in dual-power supplies level shift circuit
q
Output drivability (I
OL
= 100
, 1, 4, 8, 12 mA when PCI = 5.0V, I
OL
= 50
, 500
, 4, 6, 12 mA when PCI = 3.3V)
q
On-chip RAM available
q
I/O cells supporting the PCI Revision 2.0 and low noise output cells available
s
PRODUCT LINEUP
q
Super high-speed, and high density gate array
q
Dual power supply operation
q
Raw gates from 18K to 216K gates
(Sea of gates)
Wide Voltage
Operation
Products
2
S1L30000
Series
(V
SS
=0V)
Item
Symbol
Rating
Unit
Power voltage
V
DD
0.3 ~ 6.0
V
Input voltage
V
I
0.3 to V
DD
+0.5
V
Output voltage
V
O
0.3 to V
DD
+0.5
V
Output current/pin
I
OUT
25(
50
*1
)
mA
Storage temperature
Tstg
65 ~150
C
*1: For cell of 24mA output current
s
RECOMMENDED OPERATING CONDITIONS
q
Single power supply
Item
Symbol
Min.
Typ.
Max.
Unit
2.70
3.00
3.30
Power voltage
V
DD
3.00
3.30
3.60
V
4.75
5.00
5.25
4.50
5.00
5.50
Input voltage
V
I
V
SS
V
DD
V
Operating temperature
Topr
0
25
70
C
40
25
85
C
Normal input during input
t
ri
50
ns
rise time
Normal input during input
t
fi
50
ns
fall time
Schmitt input during input
t
ri
5
ms
rise time
Schmitt input during input
t
fi
5
ms
fall time
Item
Symbol
Min.
Typ.
Max.
Unit
Power voltage
HV
DD
4.75
5.00
5.25
V
(High voltage)
HV
DD
4.50
5.00
5.50
V
Power voltage
LV
DD
2.70
3.00
3.30
V
(Low voltage)
LV
DD
3.00
3.30
3.60
V
Input voltage
HV
I
V
SS
HV
DD
V
LV
I
V
SS
LV
DD
V
Operating temperature
Topr
0
25
70
C
40
25
85
C
Normal input during input
t
ri
50
ns
rise time
Normal input during input
t
fi
50
ns
fall time
Schmitt input during input
t
ri
5
ms
rise time
Schmitt input during input
t
fi
5
ms
fall time
q
Dual power supply
s
ABSOLUTE MAXIMUM RATINGS
3
S1L30000
Series
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Stand-by current *
I
DDS
Stop position
400
A
Input leakage current
I
LI
1
1
A
Off-state leakage current
I
OZ
1
1
A
I
OH
= 0.1mA (Type S),
1mA (Type M),
High level output voltage
V
OH
4mA (Type 1),
V
DD
V
8mA (Type 2),
4
12mA (Type 3, 4)
V
DD
= Min.
I
OL
= 0.1mA (Type S),
1mA (Type M),
4mA (Type 1),
Low level output voltage
V
OL
8mA (Type 2),
0.4
V
12mA (Type 3),
24mA (Type 4)
V
DD
= Min.
High level input voltage
V
IH1
CMOS level, V
DD
= Max.
3.5
V
Low level input voltage
V
IL1
CMOS level, V
DD
= Min.
1.0
V
High level input voltage
V
T1+
CMOS Schmitt, V
DD
= 5.0V
4.0
V
Low level input voltage
V
T1-
CMOS Schmitt, V
DD
= 5.0V
0.8
V
Hysterisis voltage
V
H1
CMOS Schmitt, V
DD
= 5.0V
0.3
V
High level input voltage
V
IH2
TTL level, V
DD
= Max.
2.0
V
Low level input voltage
V
IL2
TTL level, V
DD
= Min.
0.8
V
High level input voltage
V
T2+
TTL Schmitt, V
DD
= 5.0V
2.4
V
Low level input voltage
V
T2-
TTL Schmitt, V
DD
= 5.0V
0.6
V
Hysterisis voltage
V
H2
TTL Schmitt, V
DD
= 5.0V
0.1
V
High level input voltage
V
IH3
PCI level, V
DD
= Max.
2.0
V
Low level input voltage
V
IL3
PCI level, V
DD
= Min.
0.8
V
High level output current
I
OH3
Available for PCI , V
OH
= 1.4V,
44
mA
V
DD
= Min., V
OH
= 3.1V, V
DD
= Max.
142
mA
Low level output currrent
I
OL3
Available for PCI , V
OL
= 2.2V,
95
mA
V
DD
= Min., V
OL
= 0.71V, V
DD
= Max.
206
mA
Pull-up resistor
R
PU
V
I
= 0V
Type 1
25
50
100
K
Type 2
50
100
200
Pull-down resistor
R
PD
V
I
= V
DD
Type 1
25
50
100
K
Type 2
50
100
200
High level hold current
I
BHH1
Available for bus holding, V
IN
= 3.5V
90
A
(CMOS system) V
DD
= Max.
Low level hold current
I
BHL1
Available for bus holding, V
IN
= 1.0V
60
A
(CMOS system) V
DD
= Max.
High level hold current
I
BHH2
Available for bus holding, V
IN
= 2.0V
110
A
(TTL system) V
DD
= Max.
Low level hold current
I
BHL2
Available for bus holding, V
IN
= 0.8V
50
A
(TTL system) V
DD
= Max.
High level inversion current
I
BHHO
Available for bus holding, V
DD
= Min.
900
mA
Low level inversion current
I
BHLO
Available for bus holding, V
DD
= Min.
530
mA
Input pin capacitance
C
I
f = 1MHz, V
DD
= 0V
12
pF
Output pin capacitance
C
O
f = 1MHz, V
DD
= 0V
12
pF
I/O pin capacitance
C
IO
f = 1MHz, V
DD
= 0V
12
pF
* Stand by current is a representative value of eresy series
s
ELECTRICAL CHARACTERISTICS (V
DD
=5V)
(V
DD
= 5V, V
SS
= 0V, Ta =40 to 85
C)
4
S1L30000
Series
s
ELECTRICAL CHARACTERISTICS (V
DD
=3V)
(V
DD
= 3V
0.3V, V
SS
= 0V, Ta = 40 to 85
C)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Stand-by current*
I
DDS
Stop position
260
A
Input leakage current
I
LI
1
1
A
Off-state leakage current
I
OZ
1
1
A
I
OH
= 0.05mA (Type S),
0.5mA (Type M),
High level output voltage
V
OH
1.8mA (Type 1),
V
DD
V
3.5mA (Type 2),
0.3
5mA (Type 3, 4)
V
DD
= Min.
I
OL
= 0.05mA (Type S),
0.5mA (Type M),
1.8mA (Type 1),
Low level output voltage
V
OL
3.5mA (Type 2),
0.3
V
5mA (Type 3),
10mA (Type 4)
V
DD
= Min.
High level input voltage
V
IH1
CMOS level, V
DD
= Max.
2.0
V
Low level input voltage
V
IL1
CMOS level, V
DD
= Min.
0.8
V
High level input voltage
V
T1+
CMOS Schmitt, V
DD
= 3.0V
2.3
V
Low level input voltage
V
T1-
CMOS Schmitt, V
DD
= 3.0V
0.5
V
Hysterisis voltage
V
H1
CMOS Schmitt, V
DD
= 3.0V
0.1
V
High level input voltage
V
IH3
PCI level, V
DD
= Max.
1.58
V
Low level input voltage
V
IL3
PCI level, V
DD
= Min.
0.88
V
High level output currrent
I
OH3
Available for PCI, V
OH
= 0.81V,
33
mA
V
DD
= Min., V
OH
= 2.31V, V
DD
= Max.
105
mA
Low level output current
I
OL3
Available for PCI, V
OL
= 1.62V,
44
mA
V
DD
= Min., V
OL
= 0.60V, V
DD
= Max.
125
mA
Pull-up resistor
R
PU
V
I
= 0V
Type 1
50
100
200
K
Type 2
100
200
400
Pull-down resistor
R
PD
V
O
= V
DD
Type 1
50
100
200
K
Type 2
100
200
400
High level hold current
I
BHH
Available for bus holding, V
IN
= 2.0V
32
A
V
DD
= Max.
Low level hold current
I
BHL
Available for bus holding, V
IN
= 0.8V
27
A
V
DD
= Max.
High level inversion current
I
BHHO
Available for bus holding, V
DD
= Min.
290
mA
Low level inversion current
I
BHLO
Available for bus holding, V
DD
= Min.
170
mA
Input pin capacitance
C
I
f = 1MHz, V
DD
= 0V
12
pF
Output pin capacitance
C
O
f = 1MHz, V
DD
= 0V
12
pF
I/O pin capacitance
C
IO
f = 1MHz, V
DD
= 0V
12
pF
* Stand by current is a representative value of eresy series
5
S1L30000
Series
s
ELECTRICAL CHARACTERISTICS (V
DD
=3.3V)
(V
DD
= 3.3V
0.3V, V
SS
= 0V, Ta = 40 to 85
C)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Stand-by current*
I
DDS
Stop position
290
A
Input leakage current
I
LI
1
1
A
Off-state leakage current
I
OZ
1
1
A
I
OH
= 0.05mA (Type S),
0.5mA (Type M),
High level output voltage
V
OH
2mA (Type 1),
V
DD
V
4mA (Type 2),
0.3
6mA (Type 3, 4)
V
DD
= Min.
I
OL
= 0.05mA (Type S),
0.5mA (Type M),
2mA (Type 1),
Low level output voltage
V
OL
4mA (Type 2),
0.3
V
6mA (Type 3),
12mA (Type 4)
V
DD
= Min.
High level input voltage
V
IH1
CMOS level, V
DD
= Max.
2.2
V
Low level input voltage
V
IL1
CMOS level, V
DD
= Min.
0.8
V
High level input voltage
V
T1+
CMOS Schmitt, V
DD
= 3.3V
2.4
V
Low level input voltage
V
T1-
CMOS Schmitt, V
DD
= 3.3V
0.6
V
Hysterisis voltage
V
H1
CMOS Schmitt, V
DD
= 3.3V
0.1
V
High level input voltage
V
IH3
PCI level, V
DD
= Max.
1.71
V
Low level input voltage
V
IL3
PCI level, V
DD
= Min.
0.98
V
High level output current
I
OH3
Available for PCI, V
OH
= 0.90V,
36
mA
V
DD
= Min., V
OH
= 2.52V, V
DD
= Max.
115
mA
Low level input current
I
OL3
Available for PCI, V
OL
= 1.8V,
48
mA
V
DD
= Min., V
OL
= 0.65V, V
DD
= Max.
137
mA
Pull-up resistor
R
PU
V
I
= 0V
Type 1
45
90
180
K
Type 2
90
180
360
Pull-down resistor
R
PD
V
I
= V
DD
Type 1
45
90
180
K
Type 2
100
200
360
High level hold current
I
BHH
Available for bus holding, V
IN
= 2.0V
40
A
V
DD
= Max.
Low level hold current
I
BHL
Available for bus holding, V
IN
= 0.8V
30
A
V
DD
= Max.
High level inversion current
I
BHHO
Available for bus holding, V
DD
= Min.
350
A
Low level inversion current
I
BHLO
Available for bus holding, V
DD
= Min.
210
A
Input pin capacitance
C
I
f = 1MHz, V
DD
= 0V
12
pF
Output pin capacitance
C
O
f = 1MHz, V
DD
= 0V
12
pF
I/O pin capacitance
C
IO
f = 1MHz, V
DD
= 0V
12
pF
* Stand by current is a representative value of eresy series