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DEVICES
S1
L
60843
F
00A0
Packing specification
Specifications
Shape (
2)
Model number
Model name (
1)
Product classification (S1:semiconductor)
00
Previous number
New Number
SLA35000 series
S1L35000 series
SLA3504 S1L35043
SLA3506 S1L35063
SLA3509 S1L35093
SLA3516 S1L35163
1: Model name
2: Shape
K Standard Cell
L
Gate Array
X Embedded Array
B Assembled on board, COB,
BGA
C Plastic DIP
D Bare Chip
F
Plastic QFP
H Ceramic DIP
L
Ceramic QFP
M Plastic SOP
R TABQFP
T
Tape Carrier (TAB)
2
TSOP (Standard Bent)
3
TSOP (Reverse Bent)
Contents
GATE ARRAY S1L35000 SERIES
EPSON
i
DESIGN GUIDE
S1L35000 Series Table of Contents
Chapter 1 Overview................................................................................................. 1
1.1 Features of the S1L35000 Series ................................................................................ 1
1.2 Master Structure of the S1L35000 Series.................................................................... 1
1.3 Electrical Characteristics and Specifications of the S1L35000 Series......................... 2
1.4 Overview of Gate Array Development Flow................................................................. 6
Chapter 2 Estimating Gate Density and Selecting the Master............................ 8
2.1 Dividing up Logic between Chips................................................................................. 8
2.2 Determining Gate Density............................................................................................ 8
2.3 Estimating the Number of Input/Output Terminals....................................................... 8
2.4 Selecting the Master .................................................................................................... 8
2.5 Estimating the BCs That can be Used in Circuits Which Include RAM........................ 9
Chapter 3 Cautions and Notes Regarding Circuit Design................................. 10
3.1 Inserting Input/Output Buffers .................................................................................... 10
3.2 The Use of Differentiating Circuits is Forbidden ........................................................ 10
3.3 Wired Logic is Forbidden ........................................................................................... 10
3.4 Hazard Countermeasures.......................................................................................... 11
3.5 Fan-Out Constraints................................................................................................... 11
3.6 Bus Circuits................................................................................................................ 11
3.7 Schematic Capture Guidelines .................................................................................. 12
3.8 Clock Tree Synthesis ................................................................................................. 13
3.9 Restrictions and Constraints on VHDL/Verilog-HDL Netlist....................................... 17
3.9.1 Common Restrictions and Constraints ............................................................................. 17
3.9.2 Restrictions and Constraints for Verilog Netlist................................................................. 17
3.9.3 Restrictions and Constraints on VHDL Netlist .................................................................. 18
Chapter 4 Input/Out Buffer and Their Use .......................................................... 19
4.1 Types of Input/Output Buffer in the S1L35000 Series ............................................... 19
4.1.1 Selecting I/O Buffer ........................................................................................................... 19
4.2 I/O Buffer Configurations with a Single Power Supply............................................... 20
4.2.1 I/O Buffer Configurations with a Single 5.0V Power Supply ............................................. 20
4.2.1.1 Input Buffer Configurations with a Single 5.0V Power Supply.................................. 20
4.2.1.2 Output Buffer Configurations with a Single 5.0V Power Supply............................... 20
4.2.1.3 Bi-directional Buffer Configurations with a Single 5.0V Power Supply..................... 23
4.2.2 I/O Buffer Configurations with a Single 3.0/3.3 V Power Supply ...................................... 24
4.2.2.1 Input Buffer Configurations with a Single 3.0/3.3 V Power Supply........................... 24
4.2.2.2 Output Buffer Configurations with a Single 3.0/3.3V Power Supply......................... 25
4.2.2.3 Bi-directional Buffer Configurations with a Single 3.0/3.3 V Power Supply.............. 27
4.3 Oscillation Circuit ....................................................................................................... 30
4.3.1 Oscillation Circuit Configurations ...................................................................................... 30
4.3.2 Oscillator Circuit Considerations ....................................................................................... 30
Chapter 5 RAM ...................................................................................................... 32
5.1 Features..................................................................................................................... 32
5.2 RAM Configuration and Simulation Model Selection ................................................. 32
5.3 RAM Size ................................................................................................................... 33
5.4 Investigating RAM Placement on Master Slice .......................................................... 35
5.5 Explanation of Functions............................................................................................ 36
5.6 Delay Parameters ...................................................................................................... 38
5.7 Timing Charts............................................................................................................. 46
Contents
ii
EPSON
GATE ARRAY S1L35000 SERIES
DESIGN GUIDE
5.8 RAM Test Method ......................................................................................................49
5.9 Estimating RAM Current Consumption ......................................................................49
5.10 RAM Symbols and How They are Used ..................................................................49
Chapter 6 Circuit Design Taking Testability Into Account ............................... 51
6.1 Considerations Regarding Circuit Initialization ..........................................................51
6.2 Considerations Regarding Compressing the Test Patterns .......................................51
6.3 RAM Test Circuit ........................................................................................................52
6.3.1 RAM Test Pattterns .......................................................................................................... 53
6.4 Function Cell Test Circuits .........................................................................................58
6.4.1 Test Circuit Structures ..................................................................................................... 58
6.4.2 Test Patterns .................................................................................................................... 58
6.4.3 Test Circuit Data ............................................................................................................... 59
6.5 Test Circuit Which Simplifies AC and DC Testing .....................................................60
Chapter 7 Propagation Delay and Timing .......................................................... 67
7.1 Simple Delay Models .................................................................................................67
7.2 Load Due to Input Capacitance (Load A)...................................................................68
7.3 Load Due to Interconnect Capacitance (Load B).......................................................69
7.4 Propagation Delay Calculations.................................................................................70
7.5 Calculating Output Buffer Delay.................................................................................72
7.6 Sequential Cell Setup/Hold Time ...............................................................................72
7.7 Chip Internal Skew .....................................................................................................75
Chapter 8 Test Pattern Generation ..................................................................... 76
8.1 Testability Considerations ..........................................................................................76
8.2 Waveform Types ........................................................................................................76
8.3 Constraints on the Types of Test Patterns.................................................................77
8.3.1 Test Period ....................................................................................................................... 77
8.3.2 Input Delay........................................................................................................................ 77
8.3.3 Pulse Width....................................................................................................................... 77
8.3.4 Input Waveform Format .................................................................................................... 78
8.3.5 Strobe ............................................................................................................................... 78
8.4 Notes Regarding DC Testing .....................................................................................78
8.5 Notes Regarding the Use of Oscillation Circuits ........................................................80
8.6 Regarding AC Testing................................................................................................81
8.6.1 Constraints Regarding Measurement Events ................................................................... 81
8.6.2 Constraints on the Measurement Locations for AC Testing ............................................. 82
8.6.3 Constraints Regarding the Path Delay Which is Tested................................................... 82
8.6.4 Other Constraints.............................................................................................................. 82
8.7 Test Pattern Constraints for Bi-directional Terminals ................................................82
Chapter 9 Estimating the Power Consumption ................................................. 83
9.1 Calculating the Power Consumption ..........................................................................83
9.2 Constraints on Power Consumption ..........................................................................86
Chapter 10 Pin Layout Considerations............................................................... 87
10.1 Estimating the Number of Power Supply Terminals ................................................87
10.2 Number of Simultaneous Operations and Adding Power Supplies..........................87
10.3 Cautions and Notes Regarding the Layout of Terminals .........................................89
10.3.1 Fixed Power Supply Pins................................................................................................ 89
10.3.2 Cautions and Notes Regarding the Pin Layout............................................................... 89
10.3.3 Examples of Recommended Pin Connections ............................................................... 96
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