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1
DATA SHEET
ASIC
S
1L60000 Series
May 2000
Epson Electronics America, Inc.
8
150 River Oaks Pkwy
8
San Jose, CA 95134
8
Tel: (408)922-0200
8
S
1L60000 SERIES HIGH DENSITY GATE ARRAY
DESCRIPTION
The EEA S1L60000 Series is a family of ultra high-speed VLSI CMOS gate arrays utilizing a
0.25
m "sea-of-gates" architecture.
Ultra-high-speed, high density and low power consumption
Low voltage operation: 2.5V and 2.0V
Number of raw gates: 2,519,604 gates
FEATURES
Process
0.25
m 3/4 layer metalization CMOS process
Integration
A maximum of 2,519,604 gates (2 input NAND gate equivalent)
Operating Speed
Internal gates: 107ps (2.5V Typ), 140 ps (2.0V Typ)
(2-input pair NAND, F/O = 1, Typical wire load)
Input buffer:
260 ps (3.3V Typ), Built-in level shifter used.
270 ps (2.5V Typ), 360 ps (2.0 Typ)
(F/O = 2, Typical wire load)
Output buffer: 1.5ns (3.3V Typ) Built-in level shifter used.
1.6ns (2.5V Typ), 2.3ns (2.0V Typ) (C
L
=15 pF)
I/F Levels
CMOS/LVTTL compatible
Input Modes
CMOS, LVTTL, CMOS Schmitt, LVTTL Schmitt, PCI-3V
Built-in pull-up and pull-down resistor can be usable.
(2 types for each resistor value)
Output Modes
Normal, 3-state, bi-directional, PCI-3V
Output Drive
I
OL
= 0.1, 1, 3, 6, 12, 24 mA selectable
(built-in level shifter is used at 3.3V)
I
OL
= 0.1, 1,3,6,9,18mA selectable (at 2.5V)
I
OL
= 0.05,0.3,1,1,3,6mA selectable (at 2.0V)
RAM
Asynchronous 1-port, asynchronous 2-port
Dual Power
Operation supported by using level-shifter circuit
Internal logic: Operation supported by low voltage.
I/O Buffer:
Built-in interfaces of both high and low voltages
possible.
PRELIMINARY
2
Epson Electronics America, Inc.
8
150 River Oaks Pkwy
8
San Jose, CA 95134
8
Tel: (408)922-0200
ASIC
S
1L60000 Series
DATA SHEET
Master Structure
The S1L60000 Series comprises 10 types of masters, from which the customer is able to select the
master most suitable.
Cell Utilization Ratio
(U)
*1
Master
Total
BC
(Raw Gates)
Number
of
Pads
Number
of
Columns (X)
Number
of
Rows (Y)
3-layer
metal
4-layer
metal
S1L60093 99220 112 605 164 80 90
S1L60173 171720 148 795 216 80 90
S1L60283 284394 188 1023 278 70 85
S1L60403 400290 224 1213 330 70 85
S1L60593 595362 272 1481 402 70 85
S1L60833 831572 284 1747 476 65 80
S1L61233 1234820 344 2129 580 65 80
S1L61583 1587754 388 2413 658 65 80
S1L61903 1902960 424 2643 720 60 75
S1L62513 2519604 488 3043 828 60 75
NOTE:
*
1: This is the value when there are no cells, such as RAM cells. The cell use efficiency is dependent not only on the scope of
the circuits, but also on the number of signals, the number of branches per signal, etc.; thus, use the values in this table only
as an estimate
ELECTRICAL CHARACTERISTICS AND SPECIFICATIONS
Absolute Maximum Ratings (For single Power Supplies):
(V
ss
= 0V)
Item
Symbol
Limits
Unit
Power Supply Voltage
V
DD
-0.3 to 3.0
V
Input Voltage
V
I
-0.3 to V
DD
+ 0.5
*1
V
Output Voltage
V
O
-0.3 to V
DD
+ 0.5
*1
V
Output Current/Pin
I
OUT
30
mA
Storage Temperature
T
STG
-65 to 150
C
*
*1: Possible to use from 0.3V to 4.0V of N channel open drain bi-directional buffers and input buffer.
3
DATA SHEET
ASIC
S
1L60000 Series
May 2000
Epson Electronics America, Inc.
8
150 River Oaks Pkwy
8
San Jose, CA 95134
8
Tel: (408)922-0200
8
Absolute Maximum Ratings (For Dual Power Supplies):
(V
ss
= 0V)
Item
Symbol
Limits
Unit
Power Supply Voltage
HV
DD
*3
LV
DD
*3
-0.3 to 4.0
-0.3 t0 3.0
V
V
Input Voltage
HV
I
LV
I
-0.3 to HV
DD
+ 0.5
*1
-0.3
toLV
DD
+ 0.5
*1
V
V
Output Voltage
HV
O
LV
O
-0.3 to HV
DD
+ 0.5
*1
-0.3 to LV
DD
+ 0.5
*1
V
V
Output Current/Pin
I
OUT
30 (+/- 50
*2
)
mA
Storage Temperature
T
STG
-65 to 150
C
*
*1: Possible to use from 0.3V to 4.0V of N channel open drain bi-directional buffers and input buffer.
*2. Possible to use 24mA of output buffer.
*3. HV
DD
>LV
DD
.
Recommended Operating Conditions (For Single Power Supplies: V
DD
= 2.5V)
Item
Symbol
Min
Typ
Max
Unit
Power Supply Voltage
V
DD
2.30
2.50
2.70
V
Input Voltage
V
I
V
SS
--
V
DD
*1
V
Ambient Temperature
T
a
0
-40
25
25
70
*2
85
*3
C
Normal Input for Rising Edge Input
t
ri
--
--
50
ns
Normal Input for Falling Edge Input
t
fi
--
--
50
ns
Schmitt Input for Rising Edge Input
t
ri
--
--
5
ms
Schmitt Input for Falling Edge Input
t
fi
--
--
5
ms
*1: Possible to use 3.6V of N channel open drain bi-directional buffers and input buffers
*2: The ambient temperature range is recommended for Tj = 0 to 85
o
C.
*3: The ambient temperature range is recommended for Tj = -40 to 125
o
C.
Recommended Operating Conditions (For Single Power Supplies):
Item
Symbol
Min
Typ
Max
Unit
Power Supply Voltage
V
DD
1.80
2.00
2.20
V
Input Voltage
V
I
V
SS
--
V
DD
*1
V
Ambient Temperature
T
a
0
-40
25
25
70
*2
85
*3
C
Normal Input for Rising Edge Input
t
ri
--
--
100
ns
Normal Input for Falling Edge Input
t
fi
--
--
100
ns
Schmitt Input for Rising Edge Input
t
ri
--
--
10
ms
Schmitt Input for Falling Edge Input
t
fi
--
--
10
ms
*1: Possible to use 3.6V of N channel open drain bi-directional buffers and input buffers
*2: The ambient temperature range is recommended for Tj = 0 to 85
o
C.
*3: The ambient temperature range is recommended for Tj = -40 to 125
o
C.
4
Epson Electronics America, Inc.
8
150 River Oaks Pkwy
8
San Jose, CA 95134
8
Tel: (408)922-0200
ASIC
S
1L60000 Series
DATA SHEET
Recommended Operating Conditions (For Dual Power Supplies):
Item
Symbol
Min
Typ
Max
Unit
Power Supply Voltage (High Voltage)
HV
DD
3.00
3.30
3.60
V
Power Supply Voltage (Low Voltage)
LV
DD
2.30
2.50
2.70
V
HV
I
V
SS
--
HV
DD
*1
Input Voltage
LV
I
V
SS
--
LV
DD
*1
V
Ambient Temperature
T
a
0
-40
25
25
70
*2
85
*3
C
Normal Input for Rising Edge Input
H
tri
--
--
50
ns
Normal Input for Falling Edge Input
H
tfi
--
--
50
ns
Schmitt Input for Rising Edge Input
H
tri
--
--
5
ms
Schmitt Input for Falling Edge Input
H
tfi
--
--
5
ms
*1: Possible to use 3.6V of N channel open drain bi-directional buffers and input buffers
*2: The ambient temperature range is recommended for Tj = 0 to 85
o
C
*3: The ambient temperature range is recommended to Tj = -40 to 125
o
C.
Recommended Operating Conditions (For Dual Power Supplies):
Item
Symbol
Min
Typ
Max
Unit
Power Supply Voltage (High Voltage)
HV
DD
3.00
3.30
3.60
V
Power Supply Voltage (Low Voltage)
LV
DD
1.80
2.00
2.20
V
HV
I
V
SS
--
HV
DD
*1
Input Voltage
LV
I
V
SS
--
LV
DD
*1
V
Ambient Temperature
T
a
0
-40
25
25
70
*2
85
*3
C
H
tri
--
--
50
Normal Input for Rising Edge Input
L
tri
--
--
100
ns
H
tfi
--
--
50
Normal Input for Falling Edge Input
L
tfi
--
--
100
ns
H
tri
--
--
5
Schmitt Input for Rising Edge Input
L
tri
--
--
10
ms
H
tfi
--
--
5
Schmitt Input for Falling Edge Input
L
tfi
--
--
10
ms
*1: Possible to use 3.6V of N channel open drain bi-directional buffers and input buffers
*2: The ambient temperature range is recommended for Tj = 0 to 85
o
C
*3: The ambient temperature range is recommended to Tj = -40 to 125
o
C.
5
DATA SHEET
ASIC
S
1L60000 Series
May 2000
Epson Electronics America, Inc.
8
150 River Oaks Pkwy
8
San Jose, CA 95134
8
Tel: (408)922-0200
8
Electrical Characteristics of the S
1L60000 Series:
(HV
DD
= 3.3V in common, V
SS
= OV, Ta = -40 to 85
o
C)
Item
Symbol
Conditions
Min
Typ
Max
Unit
Input Leakage Current
I
LI
--
-5
--
5
A
Off State Leakage Current
I
OZ
--
-5
--
5
A
High Level Output Voltage
V
OH
I
OH
= -0.1mA (Type S), -1mA (Type
M), -3mA (Type 1), -6mA (Type 2),
-12mA (Type 3), -24mA (Type 4)
HV
DD
= Min
HV
DD
-0.4
--
--
V
Low Level Output Voltage
V
OL
I
OL
= 0.1mA (Type S), 1mA (Type
M), 3mA (Type 1), 6mA (Type 2),
12mA (Type 3), 24mA (Type 4)
HV
DD
= Min
--
--
0.4
V
High Level Input Voltage
V
IH1
CMOS Level, HV
DD
= Max
2.2
--
--
V
Low Level Input Voltage
V
IL1
CMOS Level, HV
DD
= Min
--
--
0.8
V
Possitive Trigger Voltage
V
T1+
CMOS Schmitt
1.4
--
2.7
V
Negative Trigger Voltage
V
T1-
CMOS Schmitt
0.6
--
1.8
V
Hysteresis Voltage
V
H1
CMOS Schmitt
0.3
--
--
V
High Level Input Voltage
V
IH2
LVTTL Level, HV
DD
= Max
2.0
--
--
V
Low Level Input Voltage
V
IL2
LVTTL Level, HV
DD
= Min
--
--
0.8
V
Positive Trigger Voltage
V
T2+
LVTTL Schmitt
1.1
--
2.4
V
Negative Trigger Voltage
V
T2-
LVTTL Schmitt
0.6
--
1.8
V
Hysteresis Voltage
V
H2
LVTTL Schmitt
0.1
--
--
V
High Level Input Voltage
V
IH3
PCI Level, HV
DD
+ Max
1.8
--
--
V
Low Level Input Voltage
V
IL3
PCI Level, HV
DD
= Min
--
--
0.9
V
High Level Output Current
I
OH3
PCI Response,
V
OH
= 0.90V, HV
DD
= Min
V
OH
= 2.52V, HV
DD
= Max
-36
--
--
--
--
-115
mA
mA
Low Level Output Current
I
OL3
PCI Response
V
OH
= 1.80V, HV
DD
= Min
V
OL
= .065V, HV
DD
= Max
48
--
--
--
--
137
mA
mA
Type 1
30
60
(120)
144
Pull-up Resistance
R
UP
V
I
= 0V
Type 2
60
120
(240)
288
K
Type 1
30
60
(120)
144
Pull-down Resistance
R
PD
V
I
=HV
DD
Type 2
60
120
(240)
288
K
High Level Maintenance
Current
I
BHH
Bus Hold Response,
V
IN
= 2.0V, HV
DD
= Min
--
--
-20
A
Low Level Maintenance
Current
I
BHL
Bus Hold Response,
V
IN
= 0.8V, HV
DD
= Min
--
--
17
A
High Level Reversal Current
I
BHHO
Bus Hold Response,
V
IN
= 0.8V, HV
DD
= Max
-350
--
--
A
Low Level Reversal Current
I
BHLO
Bus Hold Response,
V
IN
= 2.0V, HV
DD
= Max
210
--
--
A
Input Terminal Capacitance
C
I
f = 1Mhz, V
DD
= 0V
--
--
8
pF
Output Terminal Capacitance
C
O
f = 1Mhz, V
DD
= 0V
--
--
10
pF
Input/Output Terminal
Capacitance
C
IO
f = 1Mhz, V
DD
= 0V
--
--
10
pF