Document Outline

• SED1355 TECHNICAL MANUAL
  • Customer Support Information
    • Comprehensive Support Tools
    • Evaluation / Demonstration Board
    • Chip Documentation
    • Software
    • Application Engineering Support
    • Table of Contents
• SED1355 EMBEDDED RAMDAC LCD/CRT CONTROLLER October...
  • DESCRIPTION
  • FEATURES
  • System Block Diagram
• Hardware Functional Specification
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
    • 1.1 Scope
    • 1.2 Overview Description
  • 2 Features
    • 2.1 Memory Interface
    • 2.2 CPU Interface
    • 2.3 Display Support
    • 2.4 Display Modes
    • 2.5 Display Features
    • 2.6 Clock Source
    • 2.7 Miscellaneous
  • 3 Typical System Implementation Diagrams
    • Figure 31: Typical System Diagram (SH-4 Bus)
    • Figure 32: Typical System Diagram (SH-3 Bus)
    • Figure 33: Typical System Diagram (MC68K Bus 1, 1...
    • Figure 34: Typical System Diagram (MC68K Bus 2, 3...
    • Figure 35: Typical System Diagram (Generic Bus)
    • Figure 36: Typical System Diagram (NEC VR41xx (MI...
    • Figure 37: Typical System Diagram (Philips PR3150...
    • Figure 38: Typical System Diagram (Toshiba TX3912...
    • Figure 39: Typical System Diagram (Power PC Bus)
    • Figure 310: Typical System Diagram (PC Card (PCMC...
  • 4 Internal Description
    • 4.1 Block Diagram Showing Datapaths
    • 4.2 Block Descriptions
      • 4.2.1 Register
      • 4.2.2 Host Interface
      • 4.2.3 CPU R/W
      • 4.2.4 Memory Controller
      • 4.2.5 Display FIFO
      • 4.2.6 Cursor FIFO
      • 4.2.7 Look-Up Tables
      • 4.2.8 CRTC
      • 4.2.9 LCD Interface
      • 4.2.10 DAC
      • 4.2.11 Power Save
      • 4.2.12 Clocks
  • 5 Pins
    • 5.1 Pinout Diagram
      • Figure 51: Pinout Diagram
    • 5.2 Pin Description
      • Key:
      • 5.2.1 Host Interface
        • Table 51: Host Interface Pin Descriptions (Contin...
      • 5.2.2 Memory Interface
        • Table 52: Memory Interface Pin Descriptions (Cont...
      • 5.2.3 LCD Interface
        • Table 52: LCD Interface Pin Descriptions 
      • 5.2.4 CRT Interface
        • Table 53: CRT Interface Pin Descriptions 
      • 5.2.5 Miscellaneous
        • Table 54: Miscellaneous Interface Pin Description...
    • 5.3 Summary of Configuration Options
      • Table 55: Summary of Power On/Reset Options
    • 5.4 Multiple Function Pin Mapping
      • Table 56: CPU Interface Pin Mapping
      • Table 57: Memory Interface Pin Mapping
      • Table 58: LCD Interface Pin Mapping
    • 5.5 CRT Interface
      • Figure 53: External Circuitry for CRT Interface
  • 6 D.C. Characteristics
    • Table 61: Absolute Maximum Ratings
    • Table 62: Recommended Operating Conditions
    • Table 63: Electrical Characteristics for VDD = 5....
    • Table 64: Electrical Characteristics for VDD = 3....
    • Table 65: Electrical Characteristics for VDD = 3....
  • 7 A.C. Characteristics
    • 7.1 CPU Interface Timing
      • 7.1.1 SH-4 Interface Timing
        • Figure 71: SH-4 Timing
        • Table 71: SH-4 Timing
      • 7.1.2 SH-3 Interface Timing
        • Figure 72: SH-3 Timing
        • Table 72: SH-3 Timing
      • 7.1.3 MC68K Bus 1 Interface Timing (e.g. MC68000)
        • Figure 73: MC68000 Timing
        • Table 73: MC68000 Timing
      • 7.1.4 MC68K Bus 2 Interface Timing (e.g. MC68030)
        • Figure 74: MC68030 Timing
        • Table 74: MC68030 Timing
      • 7.1.5 Generic Interface Timing (e.g. PC Card (PCMC...
        • Figure 75: Generic Timing
        • Table 75: Generic Timing
      • 7.1.6 MIPS/ISA Interface Timing
        • Figure 76: MIPS/ISA Timing
        • Table 76: MIPS/ISA Timing
      • 7.1.7 Philips Interface Timing (e.g. PR31500/PR317...
        • Figure 77: Philips Timing
        • Table 77: Philips Timing
        • Figure 78: Clock Input Requirement
        • Table 78: Clock Input Requirements for BUSCLK usi...
      • 7.1.8 Toshiba Interface Timing (e.g. TX3912)
        • Figure 79: Toshiba Timing
        • Table 79: Toshiba Timing
        • Figure 710: Clock Input Requirement
        • Table 710: Clock Input Requirements for BUSCLK us...
      • 7.1.9 Power PC Interface Timing (e.g. MPC8xx, MC68...
        • Figure 711: Power PC Timing
        • Table 711: Power PC Timing
    • 7.2 Clock Input Requirements
      • Figure 712: Clock Input Requirement
      • Table 712: Clock Input Requirements for CLKI divi...
      • Table 713: Clock Input Requirements for CLKI
    • 7.3 Memory Interface Timing
      • 7.3.1 EDO-DRAM Read/Write/Read-Write Timing
        • Figure 713: EDO-DRAM Read/Write Timing
        • Figure 714: EDO-DRAM Read-Write Timing
        • Table 714: EDO-DRAM Read/Write/Read-Write Timing
      • 7.3.2 EDO-DRAM CAS Before RAS Refresh Timing
        • Figure 715: EDO-DRAM CAS Before RAS Refresh Timin...
        • Table 715: EDO-DRAM CAS Before RAS Refresh Timing...
      • 7.3.3 EDO-DRAM Self-Refresh Timing
        • Figure 716: EDO-DRAM Self-Refresh Timing
        • Table 716: EDO-DRAM Self-Refresh Timing
      • 7.3.4 FPM-DRAM Read/Write/Read-Write Timing
        • Figure 717: FPM-DRAM Read/Write Timing
        • Figure 718: FPM-DRAM Read-Write Timing
        • Table 717: FPM-DRAM Read/Write/Read-Write Timing
      • 7.3.5 FPM-DRAM CAS Before RAS Refresh Timing
        • Figure 719: FPM-DRAM CAS Before RAS Refresh Timin...
        • Table 718: FPM-DRAM CAS Before RAS Refresh Timing...
      • 7.3.6 FPM-DRAM Self-Refresh Timing
        • Figure 720: FPM-DRAM Self-Refresh Timing
        • Table 719: FPM-DRAM CBR Self-Refresh Timing
    • 7.4 Power Sequencing
      • 7.4.1 LCD Power Sequencing
        • Figure 721: LCD Panel Power Off / Power On Timing...
        • Table 720: LCD Panel Power Off/ Power On
      • 7.4.2 Power Save Status
        • Figure 722: Power Save Status and Local Bus Memor...
        • Table 721: Power Save Status and Local Bus Memory...
    • 7.5 Display Interface
      • 7.5.1 4-Bit Single Monochrome Passive LCD Panel Ti...
        • Figure 723: 4-Bit Single Monochrome Passive LCD P...
        • Figure 724: 4-Bit Single Monochrome Passive LCD P...
        • Table 722: 4-Bit Single Monochrome Passive LCD Pa...
      • 7.5.2 8-Bit Single Monochrome Passive LCD Panel Ti...
        • Figure 725: 8-Bit Single Monochrome Passive LCD P...
        • Figure 726: 8-Bit Single Monochrome Passive LCD P...
        • Table 723: 8-Bit Single Monochrome Passive LCD Pa...
      • 7.5.3 4-Bit Single Color Passive LCD Panel Timing
        • Figure 727: 4-Bit Single Color Passive LCD Panel ...
        • Figure 728: 4-Bit Single Color Passive LCD Panel ...
        • Table 724: 4-Bit Single Color Passive LCD Panel A...
      • 7.5.4 8-Bit Single Color Passive LCD Panel Timing ...
        • Figure 729: 8-Bit Single Color Passive LCD Panel ...
        • Figure 730: 8-Bit Single Color Passive LCD Panel ...
        • Table 725: 8-Bit Single Color Passive LCD Panel A...
      • 7.5.5 8-Bit Single Color Passive LCD Panel Timing ...
        • Figure 731: 8-Bit Single Color Passive LCD Panel ...
        • Figure 732: 8-Bit Single Color Passive LCD Panel ...
        • Table 726: 8-Bit Single Color Passive LCD Panel A...
      • 7.5.6 16-Bit Single Color Passive LCD Panel Timing...
        • Figure 733: 16-Bit Single Color Passive LCD Panel...
        • Figure 734: 16-Bit Single Color Passive LCD Panel...
        • Table 727: 16-Bit Single Color Passive LCD Panel ...
      • 7.5.7 8-Bit Dual Monochrome Passive LCD Panel Timi...
        • Figure 735: 8-Bit Dual Monochrome Passive LCD Pan...
        • Figure 736: 8-Bit Dual Monochrome Passive LCD Pan...
        • Table 728: 8-Bit Dual Monochrome Passive LCD Pane...
      • 7.5.8 8-Bit Dual Color Passive LCD Panel Timing
        • Figure 737: 8-Bit Dual Color Passive LCD Panel Ti...
        • Figure 738: 8-Bit Dual Color Passive LCD Panel A....
        • Table 729: 8-Bit Dual Color Passive LCD Panel A.C...
      • 7.5.9 16-Bit Dual Color Passive LCD Panel Timing
        • Figure 739: 16-Bit Dual Color Passive LCD Panel T...
        • Figure 740: 16-Bit Dual Color Passive LCD Panel A...
        • Table 730: 16-Bit Dual Color Passive LCD Panel A....
      • 7.5.10 16-Bit TFT/D-TFD Panel Timing
        • Figure 741: 16-Bit TFT/D-TFD Panel Timing
        • Figure 742: TFT/D-TFD A.C. Timing
        • Table 731: TFT/D-TFD A.C. Timing
      • 7.5.11 CRT Timing
        • Figure 743: CRT Timing
        • Figure 744: CRT A.C. Timing
  • 8 Registers
    • 8.1 Register Mapping
      • Table 81: SED1355 Addressing
    • 8.2 Register Descriptions
      • 8.2.1 Revision Code Register
      • 8.2.2 Memory Configuration Registers
        • Table 82: DRAM Refresh Rate Selection
      • 8.2.3 Panel/Monitor Configuration Registers
        • Table 83: Panel Data Width Selection
        • Table 84: FPLINE Polarity Selection
        • Table 85: FPFRAME Polarity Selection
      • 8.2.4 Display Configuration Registers
        • Table 86: Simultaneous Display Option Selection
        • Table 87: Bit-per-pixel Selection
        • Table 88: Pixel Panning Selection
      • 8.2.5 Clock Configuration Register
        • Table 89: PCLK Divide Selection
      • 8.2.6 Power Save Configuration Registers
        • Table 810: Suspend Refresh Selection
      • 8.2.7 Miscellaneous Registers
        • Table 811: MA/GPIO Pin Functionality
        • Table 812: Minimum Memory Timing Selection
        • Table 813: RAS#-to-CAS# Delay Timing Select
        • Table 814: RAS Precharge Timing Select
        • Table 815: Optimal NRC, NRP, and NRCD values at m...
        • Table 816: Minimum Memory Timing Selection
      • 8.2.8 Look-Up Table Registers
      • 8.2.9 Ink/Cursor Registers
        • Table 817: Ink/Cursor Selection
        • Table 818: Ink/Cursor Start Address Encoding
        • Table 819: Recommended Alternate FRM Scheme
  • 9 Display Buffer
    • Table 91: SED1355 Addressing
    • Figure 91: Display Buffer Addressing
    • 9.1 Image Buffer
    • 9.2 Ink/Cursor Buffers
    • 9.3 Half Frame Buffer
  • 10 Display Configuration
    • 10.1 Display Mode Data Format
      • Figure 101: 1/2/4/8 Bit-per-pixel Format Memory O...
      • Figure 102: 15/16 Bit-per-pixel Format Memory Org...
    • 10.2 Image Manipulation
      • Figure 103: Image Manipulation
  • 11 Look-Up Table Architecture
    • 11.1 Monochrome Modes
      • 1 Bit-per-pixel Monochrome mode
        • Figure 111: 1 Bit-per-pixel Monochrome Mode Data ...
      • 2 Bit-per-pixel Monochrome Mode
        • Figure 112: 2 Bit-per-pixel Monochrome Mode Data ...
      • 4 Bit-per-pixel Monochrome Mode
        • Figure 113: 4 Bit-per-pixel Monochrome Mode Data ...
    • 11.2 Color Modes
      • 1 Bit-per-pixel Color Mode
        • Figure 114: 1 Bit-per-pixel Color Mode Data Outpu...
      • 2 Bit-per-pixel Color Mode
        • Figure 115: 2 Bit-per-pixel Color Mode Data Outpu...
      • 4 Bit-per-pixel Color Mode
        • Figure 116: 4 Bit-per-pixel Color Mode Data Outpu...
      • 8 Bit-per-pixel Color Mode
        • Figure 117: 8 Bit-per-pixel Color Mode Data Outpu...
      • 15/16 Bit-per-pixel Color Modes
  • 12 Ink/Cursor Architecture
    • 12.1 Ink/Cursor Buffers
      • Table 121: Ink/Cursor Start Address Encoding
    • 12.2 Ink/Cursor Data Format
      • Figure 121: Ink/Cursor Data Format
      • Table 122: Ink/Cursor Color Select
    • 12.3 Ink/Cursor Image Manipulation
      • 12.3.1 Ink Image
      • 12.3.2 Cursor Image
        • Figure 122: Cursor Positioning
  • 13 Hardware Portrait Mode
    • 13.1 Concept
      • Figure 131: Relationship Between The Screen Image...
    • 13.2 Image Manipulation in Hardware Portrait Mode
    • 13.3 Physical Memory Requirement
      • Table 132 Minimum DRAM Size Required for Hardware...
    • 13.4 Limitations
  • 14 Clocking
    • 14.1 Maximum MCLK: PCLK Ratios
      • Table 141: Maximum PCLK Frequency with EDO-DRAM
      • Table 142: Maximum PCLK Frequency with FPM-DRAM
    • 14.2 Frame Rate Calculation
      • Table 143: Example Frame Rates with Ink Disabled ...
    • 14.3 Bandwidth Calculation
      • Bandwidth during non display period
      • Bandwidth during display period
        • Table 144: Number of MCLKs required for various m...
        • Table 145: Total # MCLKs taken for Display refres...
      • Average Bandwidth
        • Table 146: Theoretical Maximum Bandwidth M byte/s...
  • 15 Power Save Modes
    • Table 151: Power Save Mode Function Summary
    • Table 152: Pin States in Power-save Modes
  • 16 Mechanical Data
    • Figure 161: Mechanical Drawing QFP15
• Programming Notes and Examples
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Initialization
    • Table 21: SED1355 Initialization Sequence (Contin...
    • 2.1 Miscellaneous
      • Display FIFO Threshold
      • Memory Address Offset
      • Half Frame Buffer Disable
  • 3 Memory Models
    • 3.1 Display Buffer Location
      • 3.1.1 Memory Organization for One Bit-Per-Pixel (2...
        • Figure 31: Pixel Storage for 1 Bpp (2 Colors/Gray...
      • 3.1.2 Memory Organization for Two Bit-Per-Pixel (4...
        • Figure 32: Pixel Storage for 2 Bpp (4 Colors/Gray...
      • 3.1.3 Memory Organization for Four Bit-Per-Pixel (...
        • Figure 33: Pixel Storage for 4 Bpp (16 Colors/Gra...
      • 3.1.4 Memory Organization for Eight Bit-Per-Pixel ...
        • Figure 34: Pixel Storage for 8 Bpp (256 Colors/16...
      • 3.1.5 Memory Organization for Fifteen Bit-Per-Pixe...
        • Figure 35: Pixel Storage for 15 Bpp (32768 Colors...
      • 3.1.6 Memory Organization for Sixteen Bit-Per-Pixe...
        • Figure 36: Pixel Storage for 16 Bpp (65536 Colors...
  • 4 Look-Up Table (LUT)
    • 4.1 Look-Up Table Registers
    • 4.2 Look-Up Table Organization
      • Table 41: Look-Up Table Configurations
      • Color Modes
        • Table 42: Recommended LUT Values for 1 Bpp Color ...
        • Table 43: Example LUT Values for 2 Bpp Color Mode...
        • Table 44: Suggested LUT Values to Simulate VGA De...
        • Table 45: Suggested LUT Values to Simulate VGA De...
      • Gray Shade Modes
        • Table 46: Recommended LUT Values for 1 Bpp Gray S...
        • Table 47: Suggested Values for 2 Bpp Gray Shade
        • Table 48: Suggested LUT Values for 4 Bpp Gray Sha...
  • 5 Advanced Techniques
    • 5.1 Virtual Display
      • Figure 51: Viewport Inside a Virtual Display
      • 5.1.1 Registers
        • Figure 52: Memory Address Offset Registers
      • 5.1.2 Examples
    • 5.2 Panning and Scrolling
      • 5.2.1 Registers
        • Figure 53: Screen 1 Start Address Registers
        • Table 51: Number of Pixels Panned Using Start Add...
        • Figure 54: Pixel Panning Register
        • Table 52: Active Pixel Pan Bits
      • 5.2.2 Examples
    • 5.3 Split Screen
      • Figure 55: 320x240 Single Panel For Split Screen
      • 5.3.1 Registers
        • Figure 56: Screen 1 Line Compare
        • Figure 57: Screen 2 Display Start Address
      • 5.3.2 Examples
  • 6 LCD Power Sequencing and Power Save Modes
    • 6.1 Introduction to LCD Power Sequencing
    • 6.2 Registers
    • 6.3 LCD Enable/Disable
      • Power On/Enable Sequence
      • Power Off/Disable Sequence
  • 7 Hardware Cursor
    • 7.1 Introduction
    • 7.2 Registers
      • Table 71: Ink/Cursor Mode
      • Table 72: Cursor/Ink Start Address Encoding
    • 7.3 Limitations
      • 7.3.1 Updating Hardware Cursor Addresses
      • 7.3.2 Reg[29h] And Reg[2Bh]
      • 7.3.3 Reg [30h]
      • 7.3.4 No Top/Left Clipping on Hardware Cursor
    • 7.4 Examples
  • 8 Hardware Rotation
    • 8.1 Introduction To Hardware Rotation
    • 8.2 SED1355 Hardware Rotation
    • 8.3 Registers
    • 8.4 Limitations
    • 8.5 Examples
  • 9 CRT Considerations
    • 9.1 Introduction
      • 9.1.1 CRT Only
      • 9.1.2 Simultaneous Display
  • 10 Identifying the SED1355
  • 11 Hardware Abstraction Layer (HAL)
    • 11.1 Introduction
    • 11.2 Contents of the HAL_STRUCT
    • 11.3 Using the HAL library
    • 11.4 API for 1355HAL
      • Table 111: HAL Functions (Continued)
    • 11.5 Initialization
      • 11.5.1 General HAL Support
      • 11.5.2 Advanced HAL Functions
      • 11.5.3 Register / Memory Access
      • 11.5.4 Color Manipulation
      • 11.5.5 Drawing
      • 11.5.6 Hardware Cursor
      • 11.5.7 Ink Layer
      • 11.5.8 Power Save
    • 11.6 Porting LIBSE to a new target platform
      • Figure 111: Components needed to build 1355 HAL a...
      • 11.6.1 Building the LIBSE library for SH3 target e...
      • 11.6.2 Building the HAL library for the target exa...
      • 11.6.3 Building a complete application for the tar...
  • 12 Sample Code
    • 12.1 Introduction
      • 12.1.1 Sample code using the SED1355 HAL API
      • 12.1.2 Sample code without using the SED1355 HAL A...
      • 12.1.3 Header Files
  • Appendix A Supported Panel Values
    • Table 121: Passive Single Panel @ 320x240 with 40...
    • Table 122: Passive Single Panel @ 640x480 with 40...
    • Table 123: Passive Dual Panel @ 640x480 with 40MH...
    • Table 124: TFT Single Panel @ 640x480 with 25.175...
• SED1355F0A Register Summary
  • REG[00h] Revision Code Register 1 (For SED1355: Pr...
  • REG[01h] Memory Configuration Register 1/0 RW
  • REG[02h] Panel Type Register 1/0 RW
  • REG[03h] Mod Rate Register RW
  • REG[04h] Horizontal Display Width Register RW
  • REG[05h] Horizontal Non-Display Period Register RW...
  • REG[06h] HRTC/FPLINE Start Position Register RW
  • REG[07h] HRTC/FPLINE Pulse Width Register RW
  • REG[08h] Vertical Display Height Register 0 RW
  • REG[09h] Vertical Display Height Register 1 RW
  • REG[0Ah] Vertical Non-Display Period Register RW
  • REG[0Bh] VRTC/FPFRAME Start Position Register RW
  • REG[0Ch] VRTC/FPFRAME Pulse Width Register RW
  • REG[0Dh] Display Mode Register RW
  • REG[0Eh] Screen 1 Line Compare Register 0 RW
  • REG[0Fh] Screen 1 Line Compare Register 1 RW
  • REG[10h] Screen 1 Display Start Address Register 0...
  • REG[11h] Screen 1 Display Start Address Register 1...
  • REG[12h] Screen 1 Display Start Address Register 2...
  • REG[13h] Screen 2 Display Start Address Register 0...
  • REG[14h] Screen 2 Display Start Address Register 1...
  • REG[15h] Screen 2 Display Start Address Register 2...
  • REG[16h] Memory Address Offset Register 0 RW
  • REG[17h] Memory Address Offset Register 1 RW
  • REG[18h] Pixel Panning Register RW
  • REG[19h] Clock Configuration Register RW
  • REG[1Ah] Power Save Configuration Register RW
  • REG[1Bh] Miscellanious Register RW
  • REG[1Ch] MD Configuration Readback Register 0 RO
  • REG[1Dh] MD Configuration Readback Register 1 RO
  • REG[1Eh] General IO Pins Configuration Register 0 ...
  • REG[1Fh] General IO Pins Configuration Register 1 ...
  • REG[20h] General IO Pins Control Register 0 RW
  • REG[21h] General IO Pins Control Register 1 RW
  • REG[22h] Performance Enhancement Register 0 RW
  • REG[23h] Performance Enhancement Register 1 RW
  • REG[24h] Look-Up Table Address Register RW
  • REG[26h] Look-Up Table Data Register RW
  • REG[27h] Ink/Cursor Control Register RW
  • REG[28h] Cursor X Position Register 0 RW
  • REG[29h] Cursor X Position Register 1 RW
  • REG[2Ah] Cursor Y Position Register 0 RW
  • REG[2Bh] Cursor Y Position Register 1 RW
  • REG[2Ch] Ink/Cursor Color 0 Register 0 RW
  • REG[2Dh] Ink/Cursor Color 0 Register 1 RW
  • REG[2Eh] Ink/Cursor Color 1 Register 0 RW
  • REG[2Fh] Ink/Cursor Color 1 Register 1 RW
  • REG[30h] Ink/Cursor Start Address Select Register ...
  • REG[31h] Alternate FRM Register RW
• 1355CFG Configuration Program
  • Table of Contents
  • List of Figures
  • 1355CFG
    • SED1355 Supported Evaluation Platforms
    • Installation
    • Usage
  • 1355CFG Configuration Pages
    • General Page
      • Figure 1: General Page
    • Memory Page
      • Figure 2: Memory Page
    • Panel Page
      • Figure 3: Panel Page
    • CRT Page
      • Figure 4: CRT Page
    • Initial Page
      • Figure 5: Default Page
    • Open Dialog Box
    • Save As Dialog Box
    • Example
    • Comments
    • Sample Program Messages
• 1355SHOW Demonstration Program
  • 1355SHOW
    • SED1355 Supported Evaluation Platforms
    • Installation
    • Usage
    • 1355SHOW Examples
      • Using 1355SHOW For Demonstration
      • Using 1355SHOW For Testing
    • Comments
    • Program Messages
• 1355SPLT Display Utility
  • 1355SPLT
    • SED1355 Supported Evaluation Platforms
    • Installation
    • Usage
    • 1355SPLT Example
    • Comments
    • Program Messages
• 1355VIRT Display Utility
  • 1355VIRT
    • SED1355 Supported Evaluation Platforms
    • Installation
    • Usage
    • 1355VIRT Example
    • Comments
    • Program Messages
• 1355PLAY Diagnostic Utility
  • 1355PLAY
    • SED1355 Supported Evaluation Platforms
    • Installation
    • Usage
    • 1355PLAY Example
    • Scripting
    • Comments
    • Program Messages
• 1355BMP Demonstration Program
  • 1355BMP
    • SED1355 Supported Evaluation Platforms
    • Installation
    • Usage
    • Hardware Cursor/Ink Layer
    • 1355BMP Examples
    • Comments
    • Program Messages
• 1355PWR Software Suspend Power Sequencing Utility
  • 1355PWR
    • SED1355 Supported Evaluation Platforms
    • Installation
    • Usage
    • 1355PWR Examples
    • Comments
    • Program Messages
• Windows� CE Display Drivers
  • WINDOWS� CE DISPLAY DRIVERS
    • Program Requirements
    • Example Driver Builds
      • Build for the Hitachi D9000 and ETMA ODO Evaluatio...
        • 1. Install Microsoft Windows NT v4.0.
        • 2. Install Microsoft Visual C/C++ v5.0.
        • 3. Install the Microsoft Windows CE Embedded Toolk...
        • 4. Create a new project by following the procedure...
        • 5. Create a sub-directory named SED1355 under \win...
        • 6. Copy the source code to the SED1355 subdirector...
        • 7. Add an entry for the SED1355 in the file \wince...
        • 8. Modify the file PLATFORM.BIB (using any text ed...
        • 9. Edit the file MODE.H (located in X:\wince\platf...
        • 10. Edit the file PLATFORM.REG to set the same scr...
        • 11. Generate the proper building environment by do...
        • 12. Type BLDDEMO at the DOS prompt of the ...
      • Build For CEPC (X86)
        • 1. Install Microsoft Windows NT v4.0.
        • 2. Install Microsoft Visual C/C++ v5.0.
        • 3. Install the Microsoft Windows CE Embedded Toolk...
        • 4. Create a new project by following the procedure...
        • 5. Create a sub-directory named SED1355 under \win...
        • 6. Copy the source code to the SED1355 subdirector...
        • 7. Add an entry for the SED1355 in the file \wince...
        • 8. Modify the file CONFIG.BIB (using any text edit...
        • 9. Edit the file PLATFORM.BIB (located in X:\wince...
        • 10. Edit the file MODE.H (located in X:\wince\plat...
        • 11. Edit the file PLATFORM.REG to set the same scr...
        • 12. Generate the proper building environment by do...
        • 13. Type BLDDEMO at the DOS prompt of the ...
    • Example Installation
      • Installation for Hitachi D9000 and ETMA ODO
        • 1. Download SEIKO EPSON�s common interface FPGA co...
        • 2. Download the Windows CE binary ROM image (NK.BI...
      • Installation for CEPC Environment
        • 1. To load CEPC from a floppy drive:
          • a. Create a DOS bootable floppy disk.
          • b. Edit CONFIG.SYS on the floppy disk to contain t...
          • c. Edit AUTOEXEC.BAT on the floppy disk to contain...
          • d. Copy LOADCEPC.EXE from c:\wince\public\common\o...
          • e. Confirm that NK.BIN is located in c:\wince\rele...
          • f. Reboot the system from the bootable floppy disk...
        • 2. To load CEPC from a hard drive:
          • a. Copy LOADCEPC.EXE to the root directory of the ...
          • b. Edit CONFIG.SYS on the hard drive to contain th...
          • c. Edit AUTOEXEC.BAT on the hard drive to contain ...
          • d. Confirm that NK.BIN is located in c:\wince\rele...
          • e. Reboot the system from the hard drive.
    • Comments
• SDU1355B0C Rev. 1.0 ISA Bus Evaluation Board User ...
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
    • 1.1 Features
  • 2 Installation and Configuration
    • Table 21: Configuration DIP Switch Settings
    • Table 22: Host Bus Selection
    • Table 23: Jumper Settings
  • 3 LCD Interface Pin Mapping
    • Table 31: LCD Signal Connector (J6)
  • 4 CPU/Bus Interface Connector Pinouts
    • Table 41: CPU/BUS Connector (H1) Pinout
    • Table 42: CPU/BUS Connector (H2) Pinout
  • 5 Host Bus Interface Pin Mapping
    • Table 51: CPU Interface Pin Mapping
  • 6 Technical Description
    • 6.1 ISA Bus Support
    • 6.2 Non-ISA Bus Support
    • 6.3 DRAM Support
    • 6.4 Decode Logic
    • 6.5 Clock Input Support
    • 6.6 Monochrome LCD Panel Support
    • 6.7 Color Passive LCD Panel Support
    • 6.8 Color TFT/D-TFD LCD Panel Support
    • 6.9 CRT Support
    • 6.10 Power Save Modes
    • 6.11 Adjustable LCD Panel Negative Power Supply
    • 6.12 Adjustable LCD Panel Positive Power Supply
    • 6.13 CPU/Bus Interface Header Strips
    • 6.14 Schematic Notes
  • 7 Parts List
  • 8 Schematic Diagrams
    • Figure 1: SED1355B0C Schematic Diagram (1 of 4)
    • Figure 2: SED1355B0C Schematic Diagram (2 of 4)
    • Figure 3: SED1355B0C Schematic Diagram (3 of 4)
    • Figure 4: SED1355B0C Schematic Diagram (4 of 4)
• SDU1355-D9000 Evaluation Board User Manual
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
    • Reference
  • 2 Features
    • 2.1 SED1355 Embedded RAMDAC LCD/CRT Controller
      • 2.1.1 Display Buffer
      • 2.1.2 LCD Display Support
        • Table 21: LCD Connector Pinout
      • 2.1.3 Touchscreen Support
        • Table 22: Touchscreen Header (TS1) Pinout
      • 2.1.4 CRT Support
      • 2.1.5 Jumper Selection
        • Table 23: Touchscreen Header Pinout
      • 2.1.6 Adjustable LCD BIAS Power Supply
  • 3 D9000 Specifics
    • 3.1 Interface Signals
      • 3.1.1 Connector Pinout for Channel A6 and A7
        • Table 31: Connectors Pinout for Channel A7 (Conti...
        • Table 32: Connectors Pinout for Channel A6 (Conti...
      • 3.1.2 Memory Address (CS#, M/R#) Decoding
    • 3.2 FPGA Code Functionality
    • 3.3 Board Dimensions
  • 4 Parts List
  • 5 Schematic Diagrams
    • Figure 51: SDU1355-D9000 Schematic Diagram (1 of ...
    • Figure 52: SDU1355-D9000 Schematic Diagram (2 of ...
    • Figure 53: SDU1355-D9000 Schematic Diagram (3 of ...
  • 6 Component Placement
    • Figure 61: Component Placement
• Power Consumption
  • 1 SED1355 Power Consumption
    • 1.1 Conditions
      • Table 11: SED1355 Total Power Consumption
  • 2 Summary
• Interfacing to the Philips MIPS PR31500/PR31700 Pr...
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the PR31500/PR31700
  • 3 SED1355 Host Bus Interface
    • 3.1 PR31500/PR31700 Host Bus Interface Pin Mapping...
      • Table 31: PR31500/PR31700 Host Bus Interface Pin ...
    • 3.2 PR31500/PR31700 Host Bus Interface Signals
  • 4 Direct Connection to the Philips PR31500/PR31700...
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of Direct Conne...
    • 4.2 SED1355 Configuration
      • Table 41: SED1355 Configuration for Direct Connec...
    • 4.3 Memory Mapping and Aliasing
      • Table 42: PR31500/PR31700 to PC Card Slots Addres...
  • 5 System Design Using the IT8368E PC Card Buffer
    • 5.1 Hardware Description
      • Figure 51: IT8368E Implementation Block Diagram
    • 5.2 IT8368E Configuration
    • 5.3 SED1355 Configuration
  • 6 Software
  • 7 References
    • 7.1 Documents
    • 7.2 Document Sources
  • 8 Technical Support
    • 8.1 EPSON LCD/CRT Controllers (SED1355)
    • 8.2 Philips MIPS PR31500/PR31700 Processor
    • 8.3 ITE IT8368E
• Interfacing to the PC Card Bus
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the PC Card Bus
    • 2.1 The PC Card System Bus
      • 2.1.1 PC Card Overview
      • 2.1.2 Memory Access Cycles
        • Figure 21: PC Card Read Cycle
        • Figure 22: PC Card Write Cycle
  • 3 SED1355 Host Bus Interface
    • 3.1 PC Card Host Bus Interface Pin Mapping
      • Table 31: PC Card Host Bus Interface Pin Mapping
    • 3.2 PC Card Host Bus Interface Signals
  • 4 PC Card to SED1355 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of PC Card to S...
    • 4.2 SED1355 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Options
    • 4.3 Performance
    • 4.4 Register/Memory Mapping
      • Table 42: Register/Memory Mapping for Typical Imp...
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 Epson LCD/CRT Controllers (SED1355)
    • 7.2 PC Card Standard
• Interfacing to the NEC VR4102/VR4111� Microprocess...
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the VR4102/VR4111
    • 2.1 The NEC VR4102/VR4111 System Bus
      • 2.1.1 Overview
      • 2.1.2 LCD Memory Access Cycles
        • Figure 21: NEC VR4102/VR4111 Read/Write Cycles
  • 3 SED1355 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signals Descriptions
  • 4 VR4102/VR4111 to SED1355 Interface
    • 4.1 Hardware Description
      • Figure 41: NEC VR4102/VR4111 to SED1355 Configura...
    • 4.2 SED1355 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Options
    • 4.3 NEC VR4102/VR4111 Configuration
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (SED1355)
    • 7.2 NEC Electronics Inc. (VR4102/VR4111).
• Interfacing to the Motorola MPC821 Microprocessor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the MPC821
    • 2.1 The MPC8xx System Bus
    • 2.2 MPC821 Bus Overview
      • 2.2.1 Normal (Non-Burst) Bus Transactions
        • Figure 21: Power PC Memory Read Cycle
        • Figure 22: Power PC Memory Write Cycle
    • 2.3 Memory Controller Module
      • 2.3.1 General-Purpose Chip Select Module (GPCM)
      • 2.3.2 User-Programmable Machine (UPM)
  • 3 SED1355 Host Bus Interface
    • 3.1 PowerPC Host Bus Interface Pin Mapping
      • Table 31: PowerPC Host Bus Interface Pin Mapping
    • 3.2 PowerPC Host Bus Interface Signals
  • 4 MPC821 to SED1355 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of MPC821 to SE...
    • 4.2 Hardware Connections
      • Table 41: List of Connections from MPC821ADS to S...
    • 4.3 SED1355 Hardware Configuration
      • Table 42: Summary of Power-On/Reset Options
    • 4.4 Register/Memory Mapping
    • 4.5 MPC821 Chip Select Configuration
    • 4.6 Test Software
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (SED1355)
    • 7.2 Motorola MPC821 Processor
• Interfacing to the Toshiba MIPS TX3912 Processor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the TX3912
  • 3 SED1355 Host Bus Interface
    • 3.1 TX3912 Host Bus Interface Pin Mapping
      • Table 31: TX3912 Host Bus Interface Pin Mapping
    • 3.2 TX3912 Host Bus Interface Signals
  • 4 Direct Connection to the Toshiba TX3912
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of Direct Conne...
    • 4.2 SED1355 Configuration
      • Table 41: SED1355 Configuration for Direct Connec...
    • 4.3 Memory Mapping and Aliasing
      • Table 42: TX3912 to PC Card Slots Address Remappi...
  • 5 System Design Using the IT8368E PC Card Buffer
    • 5.1 Hardware Description
      • Figure 51: IT8368E Implementation Block Diagram
    • 5.2 IT8368E Configuration
    • 5.3 SED1355 Configuration
  • 6 Software
  • 7 References
    • 7.1 Documents
    • 7.2 Document Sources
  • 8 Technical Support
    • 8.1 EPSON LCD/CRT Controllers (SED1355)
    • 8.2 Toshiba MIPS TX3912 Processor
    • 8.3 ITE IT8368E
• Interfacing to the NEC VR4121� Microprocessor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the NEC VR4121
    • 2.1 The NEC VR4121 System Bus
      • 2.1.1 Overview
      • 2.1.2 LCD Memory Access Cycles
        • Figure 21: NEC VR4121 Read/Write Cycles
  • 3 SED1355 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signal Descriptions
  • 4 VR4121 to SED1355 Interface
    • 4.1 Hardware Description
      • Figure 41: NEC VR4121 to SED1355 Configuration Sc...
    • 4.2 SED1355 Configuration
      • Table 41: Summary of Power-On-Reset Options
    • 4.3 NEC VR4121 Configuration
    • 4.4 Memory Mapping and Aliasing
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 Epson LCD/CRT Controllers (SED1355)
    • 7.2 NEC Electronics Inc. (VR4121).
• Interfacing to the NEC V832� Microprocessor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the NEC V832
    • 2.1 The NEC V832 System Bus
      • 2.1.1 Overview
      • 2.1.2 Access Cycles
        • Figure 21: NEC V832 Read/Write Cycles
  • 3 SED1355 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signal Descriptions
  • 4 V832 to SED1355 Interface
    • 4.1 Hardware Description
      • Figure 41: NEC V832 to SED1355 Configuration Sche...
    • 4.2 SED1355 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Options
    • 4.3 NEC V832 Configuration
      • Table 42: NEC V832 Wait States vs. Bus Clock Freq...
    • 4.4 Memory Mapping and Aliasing
      • Table 43: NEC V832 IO Address Range For Each CSn ...
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 Epson LCD/CRT Controllers (SED1355)
    • 7.2 NEC Electronics Inc. (V832).