PBD 3517/1
Stepper Motor
Drive Circuit
Figure 1. Block diagram.
February 1999
16-pin plastic DIP
16-pin SO (wide body)
RC
STEP
DIR
HSM
INH
O
A
O
B
L
A
L
B
P
B2
P
B1
P
A2
P
A1
GND
V
CC
V
SS
PBD 3517/1
PQR
Mono
F - F
Phase
Logic
P
A
P
B
Description
PBD 3517/1 is a bipolar, monolithic, integrated circuit, intended to drive a stepper motor
in a unipolar, bilevel way.
One PBD 3517/1 and a minimum of external components form a complete control
and drive unit for LS-TTL- or microprocessor-controlled stepper motor system for
currents up to 500mA. The driver is suited for applications requiring least-posssible RFI.
Motor performance can be increased by operating in a bilevel drive mode. This
means that a high voltage pulse is applied to the motor winding at the beginning of a
step, in order to give a rapid rise of current.
Key Features
Complete driver and phase logic on
chip
2 x 350 mA continuous-output current
Half- and full-step mode generation
LS-TTL-compatible inputs
Bilevel drive mode for high step rates
Voltage-doubling drive possibilities
Half-step position-indication output
Minimal RFI
16-pin plastic DIP package or 16 pin
small outline wide body
PBD 3517/1
PBD 3517/1
1
PBD 3517/1
2
Maximum Ratings
Parameter
Pin No.
Symbol
Min
Max
Unit
Voltage
Logic supply
16
V
CC
0
7
V
Second supply
15
V
SS
0
45
V
Logic input
6, 7, 10, 11
VI
-0.3
6
V
Current
Phase output
1, 2, 4, 5
I
P
0
500
mA
Second-level output
13, 14
I
L
-500
0
mA
Logic input
6, 7, 10, 11
I
I
-10
mA
The zero output
8, 9
I
6
mA
Temperature
Operating junction temperature
T
J
-40
+150
C
Storage temperature
T
S
-55
+150
C
Power Dissipation (Package Data)
Power dissipation at TA = 25
C, DIP package. Note 2.
P
D
1.6
W
Power dissipation, SO package. Note 3.
P
D
1.3
W
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Logic supply voltage
V
CC
4.75
5
5.25
V
Second-level supply voltage
V
SS
10
40
V
Phase output current
I
P
0
350
mA
Second-level output current
I
L
-350
0
mA
Operating junction temperature
T
J
-20
+125
C
Set-up time
t
s
400
ns
Step-pulse duration
t
p
800
ns
Figure 2. Definition of symbols.
HSM
or
DIR
V
I
STEP
I
P
t
t
t
t
r
t
f
t
s
t
p
t
d
Figure 3. Timing diagram
.
RC 12
STEP 7
DIR 6
HSM 10
INH 11
O
A
9
O
B
8
13 L
A
14 L
B
1 P
B2
2 P
B1
5 P
A2
4 P
A1
3 GND
V
CC
16
V
SS
15
PBD 3517/1
PQR
Mono
F - F
Phase
Logic
P
A
P
B
V
CC
V
SS
V
I
V
IH
V
IL
V
OCE Sat
V
LCE Sat
V
L
V
PCE Sat
V
P
I
P
I
PL
I
LL
I
L
I
I
I
IL
I
IH
I
SS
I
CC
PBD 3517/1
3
Electrical Characteristics
Electrical characteristics at T
A
= +25
C, V
CC
= +5.0 V, V
MM
= +40 V, V
SS
= +40 V unless otherwise specified.
Ref.
Parameter
Symbol
Fig.
Conditions
Min
Typ
Max
Unit
Supply current
I
CC
2
INH = LOW
45
60
mA
2
INH = HIGH
12
mA
Phase outputs
Saturation voltage
V
PCE Sat
4
I
P
= 350 mA
0.85
V
Leakage current
I
PL
2
V
P
= 0 V
500
A
Turn on, turn off
t
d
3
+70
C
3
s
t
d
3
+125
C
6
s
Second-level outputs
Saturation voltage
V
LCE Sat
4
I
L
= -350 mA
2.0
V
Leakage current
I
LL
2
V
L
= 0 V
-500
A
On time
t
On
11
(note 4)
220
260
300
s
Logic inputs
Voltage level, HIGH
V
IH
2
2.0
V
Voltage level, LOW
V
IL
2
0.8
V
Input current, low
I
IL
2
V
I
= 0.4 V
-400
A
Input current, high
I
IH
2
V
I
= 2.4 V
20
A
Logic outputs
Saturation voltage
V
CE Sat
5
I
= 1.6 mA
0.4
V
Notes
1. All voltages are with respect to ground. Current are positive into, negative out of specified terminal.
2 Derates at 12,8 mW/
C above +25
C.
3. Derates at 10.4 mW/
C above +25
C.
4. R
T
= 47 k
, C
T
= 10 nF.
Figure 5. Typical second level saturation
voltage vs output current.
Figure 4. Typical phase output saturation
voltage vs. output current.
Figure
2.5
2.0
1.5
1.0
0,5
0
0
0.1
0.2
0.5
0.4
0.3
V
LCE
sat [V]
I
L
[A]
T
A
= +25
C
2.5
2.0
1.5
1.0
0,5
0
0
50
100
150
Allowable power dissipation [W]
Ambient temrature [
C]
0.5
0.4
0.3
0.2
0.1
0
0
0.2
0.4
1.0
0.8
0.6
Output Current [A]
Output Voltage [V]
T
A
= +25
C
PBD 3517/1
4
Diagrams
How to use the diagrams:
1.
What is the maximum motor current
in the application?
The ambient temperature sets the
maximum allowable power
dissipation in the IC, which
relates to the motor currents and
the duty cycle of the bilevel
function. For PBD 3517/1, without
any measures taken to reduce
the chip temperature via
heatsinks, the power dissipation
vs. temperature follows the curve
in figure 4.
Figures 9 and 10 give the
relationship between motor
currents and their dissipations.
The sum of these power dissipa-
tions must never exceed the
previously-established value, or
life expectancy will be drastically
shortened.
When no bilevel or voltage
doubling is utilized, the maximum
motor current can be found
directly in figure 9.
2.
How to choose timing components.
Figure 7 shows the relationship
between C
T
, R
T
, and t
On
. Care
must be taken to keep the t
On
time
short, otherwise the current in the
winding will rise to a value many
times the rated current, causing
an overheated IC or motor.
3.
What is the maximum t
On
pulse-width
at a given frequency?
Figure 8 shows the relationship
between duty cycle, pulse width,
and step frequency. Check
specifications for the valid
operating area.
4.
Figures 4, 5 and 6 show typical
saturation voltages vs. output current
levels for different output transistors.
5.
Shaded areas represent operating
conditions outside the safe operating
area.
Figure 7. Typical I
vs. V
CE Sat
. "Zero
output" saturation.
Figure 8. Typical t
On
vs. C
T
/R
T
. Output
pulse width vs. capacitance/resistance.
Figure 9. Typical t
On
vs. f
s
/dc. Output pulse
width vs. step frequency/duty cycle
.
Figure 10. Typical P
DP
vs. I
P
. Power
dissipation without second-level supply
(includes 2 active outputs = FULL STEP)
.
Figure 11. Typical P
DI
vs. I
I
. Power
dissipation in the bilevel pulse when
raising to the I
I
value. One active output.
Figure 12 . Motor Current 1
p
.
T
A
= +25
C
10
8
6
4
2
0
0
0.2
0.4
1.0
0.8
0.6
Output Current [A]
Output Voltage [V]
1
10
-1
10
-6
0.01
0.1
1
1000
100
10
Output Pulse Width [s]
Ct Capacitance [nF]
10
-2
10
-3
10
-4
10
-5
T
A
= +25
C
Rt = 10M Rt = 100k
Rt = 10k
Rt = 1k
1
10
-1
10
-6
0.001
0.01
0.1
100
10
1
Output Pulse Width [s]
fs Step frequency [kHz]
10
-2
10
-3
10
-4
10
-5
T
A
= +25
C
50%
25%
Dutycykle
100%
0.1%
1%
10%
0.5
0.4
0.3
0.2
0.1
0
0
0.2
0.4
1.0
0.8
0.6
Output Current [A]
Power Dissipation [W]
T
A
= +25
C
(II = 0)
-0.5
-0.4
-0.3
-0.2
-0.1
0
0
0.2
0.4
1.0
0.8
0.6
Output Current [A]
Power Dissipation [W]
T
A
= +25
C
(Ip = 0)
10%
50%
100%
350
Motor Current [mA]
t
ON
Time
Normal
Bilevel
Bilevel without
time limit
PBD 3517/1
5
Pin Description
DIP
SO-pack.
Symbol
Description
1
1
P
B2
Phase output 2, phase B. Open collector output capable of sinking max 500 mA.
2
2
P
B1
Phase output 1, phase B. Open collector output capable of sinking max 500 mA.
3
3
GND
Ground and negative supply for both V
CC
and V
SS
.
4
4
P
A1
Phase output 1, phase A.
5
5
P
A2
Phase output 2, phase A.
6
6
DIR
Direction input. Determines in which rotational direction steps will be taken.
7
7
STEP
Stepping pulse. One step is generated for each negative edge of the step signal.
8
8
B
Zero current half step position indication output for phase B.
9
9
A
Zero current half step position indication output for phase A.
10
10
HSM
Half-step mode. Determines whether the motor will be operated in half or full-step
mot. When pulled low, one step pulse will correspond to a half step of the motor.
11
11
INH
A high level on the inhibit input turns all phase output off.
12
12
RC
Bilevel pulse timing pin. Pulse time is approximately t
on
= 0.55 R
T
C
T
13
13
LA
Second level (bilevel) output, phase A.
14
14
LB
Second level (bilevel) output, Phase B.
15
15
V
SS
Second level supply voltage, +10 to +40 V.
16
16
V
CC
Logic supply voltage, nominally +5 V.
Figure 13. Pin configuration.
B2
B1
GND
A1
A2
DIR
STEP
B
V
V
L
L
R
INH
HSM
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P
P
P
P
A
C
A
B
SS
CC
B2
B1
GND
A1
A2
DIR
STEP
B
V
V
L
L
R
INH
HSM
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P
P
P
P
A
C
A
B
SS
CC
PBD
3517/1N
PBD
3517/1SO
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