ESMT
Preliminary M24L16161A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2003
Revision : 0.2
1/15
4SRAM
1M x 16 Bit
PSEUDO SRAM
Features
1T SRAM Memory Cell
Operating voltage: 2.7V to 3.3V
Access times: 70 / 85 ns (max.)
1Mx16 bit Organization
Wide operating temperature range :
- Standard grade : -25
C to + 85C
- Industrial grade : -40
C to + 85C
Data mask function by /LB, /HB
Common I/O using three-state output
Available in 48-ball 6x8mm Mini-BGA packages
All inputs and outputs are directly TTL-compatible
Ordering Information
48-ball 6x8mm Mini-BGA
Product No.
Operating
Voltage
Operating
Temperature
Operating Current
Icc1 (max.)
Standby Current
Isb1 ( max.)
Packing Type
M24L16161A 70B
M24L16161A 85B
-25
C ~ +85C
M24L16161A 70BI
M24L16161A 85BI
+2.7V ~ +3.3V
-40
C ~ +85C
25 mA
100 uA
6 x 8 mm Mini-BGA
General Description
The M24L16161A is a low operating current 16,777,216-
bit static random access memory organized as 1,048,576
words by 16 bits and operates on low power voltage from
2.7V to 3.3V. It is built using high performance CMOS
process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
The chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Pin Configurations
Mini-BGA 48-ball Top View
I/O
9
I/O
10
GND
VCC
I/O
15
I/O
16
A18
A8
A19
A9
A12
A10
A11
DNU
A13
A14
A15
I/O
8
I/O
7
I/O
3
I/O
1
GND
VCC
A0
A3
A5
A6
A4
A1
A2
CE2
6
5
4
3
2
1
A
B
C
D
E
F
G
H
I/O
14
I/O
13
I/O
12
I/O
11
A17
DNU
A7
A16
I/O
2
I/O
4
I/O
5
I/O
6
LB
HB
WE
OE
CE1
Note : DNU pins are to be connected to Vss or left open.
ESMT
Preliminary M24L16161A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2003
Revision : 0.2
2/15
Block Diagram
Pin Description
Symbol
Description
Symbol
Description
A0 - A19
Address Inputs
HB
Higher Byte Enable Input
(I/O
9
- I/O
16
)
CE1
Chip Enable
OE
Output Enable
CE2
Deep Power Down
V
CC
Power Supply
I/O
1
- I/O
16
Data Input / Output
GND
Ground
WE
Write Enable Input
DNU
Do Not Use
LB
Low Byte Enable Input
(I/O
1
I/O
8
)
-
-
DECODER
1M x 16
MEMORY ARRAY
COLUMN I/O
INPUT
DATA
CIRCUIT
CONTROL
CIRCUIT
VCC
GND
I/O
8
I/O
1
A19
A18
A0
INPUT
DATA
CIRCUIT
I/O
9
I/O
16
CE2
1
CE
LB
HB
OE
WE
ESMT
Preliminary M24L16161A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2003
Revision : 0.2
3/15
Truth Table
1
CE
CE2
OE
WE
LB
HB
I/O1 to I/O8
I/O9 to
I/O16
Mode
Power
H
H
X
X
X
X
High Z
High Z
Deselect
Standby
X
L
X
X
X
X
High Z
High Z
Deselect
Deep Power Down
L
H
X
X
H
H
High Z
High Z
Deselect
Standby
L
H
H
H
L
X
High Z
High Z
Output Disable
Active
L
H
H
H
X
L
High Z
High Z
Output Disable
Active
L
H
L
H
L
H
D-out
High Z
Lower byte Read
Active
L
H
L
H
H
L
High Z
D-out
Upper Byte Read
Active
L
H
L
H
L
L
D-out
D-out
Word Read
Active
L
H
X
L
L
H
D-in
High Z
Lower Byte Write
Active
L
H
X
L
H
L
High Z
D-in
Upper Byte Write
Active
L
H
X
L
L
L
D-in
D-in
Word Write
Active
Note: X = H or L
Recommended DC Operating Conditions
(T
A
= -25
C to + 85C (Standard), T
A
= -40
C to + 85C (Industrial))
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
2.7
3
3.3
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
-
V
CC
+ 0.2
V
V
IL
Input Low Voltage
-0.2
-
+0.6
V
Capacitance ( T
A
= 25
C, f = 1.0MHz )
Symbol
Parameter
Conditions
Min.
Max.
Unit
C
IN
*
Input Capacitance
V
IN
= 0V
-
8
pF
C
I/O
*
Input / Output Capacitance
V
I/O
= 0V
-
10
pF
* These parameters are sampled and not 100% tested.
ESMT
Preliminary M24L16161A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2003
Revision : 0.2
4/15
Absolute Maximum Ratings*
V
CC
to GND ........................................................-0.2V to +3.3V
IN, IN/OUT Volt to GND............................. -0.2V to V
CC
+ 0.3V
Operating Temperature, Topr .........-25
C to +85C (Standard)
Operating Temperature, Topr .........-40
C to +85C (Industrial)
Storage Temperature, Tstg.............................-65
C to +125C
Power Dissipation, P
T.......................................................................................
1W
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are
stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the
operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for
extended periods may affect device reliability.
DC Electrical Characteristics :
(T
A
= -25
C to + 85C (Standard), T
A
= -40
C to + 85C (Industrial), V
CC
= 2.7V to 3.3V)
M24L16161A-70/85
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
I
LI
Input Leakage Current
V
IN
= GND to V
CC
-1
-
1
A
I
LO
Output Leakage Current
CE1 = V
IH
OE = V
IH
or WE = V
IH
V
I/O
= GND to V
CC
-1
-
1
A
I
CC1
Min. Cycle, Duty = 100%,
V
IN
= V
IL
or V
IH
, CE1 = V
IL
,
CE2 = V
IH
, I
I/O
= 0mA, V
DD
= 3.3V
-
-
25
mA
I
CC2
Operating Current
f = 1MHz, Duty = 100%,
V
IN
V
CC
-0.2 or V
IN
0.2V,
CE1 = V
IL
, CE2 = V
IH
,
I
I/O
= 0 mA
-
-
5
mA
I
SB1
CMOS Standby Current
CE1
V
CC
0.2V, V
IN
0V
-
-
100
I
SBD
Deep Power Down
CE2 0.2V, Other inputs = V
SS
~V
CC
-
-
10
A
V
OL
Output Low Voltage
I
OL
= 2 mA
-
-
0.4
V
V
OH
Output High Voltage
I
OH
= -1.0 mA
2.4
-
-
V
ESMT
Preliminary M24L16161A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2003
Revision : 0.2
5/15
AC Characteristics
(T
A
= -25
C to + 85C (Standard), T
A
= -40
C to + 85C (Industrial), V
CC
= 2.7V to 3.3V)
M24L16161A-70
M24L16161A-85
Unit
Symbol
Parameter
Min.
Min.
Max.
Max.
READ CYCLE
T
RC
Read Cycle Time
70
-
85
-
ns
T
AA
Address Access Time
-
70
-
85
ns
T
ACE1
Chip Enable ( CE1) Access Time
-
70
-
85
ns
T
ACE2
Chip Enable (CE2) Access Time
-
70
-
85
ns
T
OE
Output Enable to Output Valid
-
35
-
40
ns
T
BE
Byte Enable Access Time
-
70
85
ns
T
CLZ
Chip Enable to Output in Low Z
10
-
10
-
ns
T
OLZ
Output Enable to Output in Low Z
5
-
5
-
ns
T
BLZ
Byte Enable to Output in Low Z
10
-
10
ns
T
HZ
Chip Disable to Output in High Z
-
25
-
35
ns
T
OHZ
Output Disable to Output in High Z
-
25
-
35
ns
T
BHZ
Byte Disable to Output in High Z
-
25
-
35
ns
T
OH
Output Hold from Address Change
10
-
10
-
ns
WRITE CYCLE
T
WC
Write Cycle Time
70
-
85
ns
T
WP
Write Pulse Width
50
-
60
-
ns
T
AW
Address Valid to End of Write
60
-
70
-
ns
T
CW
Chip Enable to End of Write
60
-
70
-
ns
T
BW
Byte Enable to End of Write
60
-
70
-
ns
T
AS
Address Setup Time
0
-
0
-
ns
T
WR
Write Recovery Time
0
-
0
-
ns
T
WHZ
Write to Output in High Z
-
20
-
30
ns
T
OW
Output Active to End of Write
5
-
5
-
ns
T
DW
Data to Write Time Overlap
30
-
30
-
ns
T
DH
Data Hold from Write Time
0
-
0
-
ns
Note: T
HZ
, T
OHZ
and T
BHZ
and T
WHZ
are defined as the time at which the outputs achieve the open circuit
Condition and are not referred to output voltage levels.
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