ESS Technology, Inc.
SAM0392-061302
1
ESS Technology, Inc.
ES2846/ES2851
HomePNA/LAN/ V.90/V.92 HSP Solution
Product Brief
DESCRIPTION
The ES2846/ES2851 SuperLink
-MLP16 solution provides
true simultaneous, concurrent, triple-technology connectivity:
16-Mbps Home Phoneline Networking Alliance (HomePNA 2.0),
10/100 IEEE 802.3 Fast Ethernet LAN, and V.90/V.92 56k HSP
modem. This triple-technology solution enables end users to
enjoy the increased flexibility needed in today's complex world of
communications.
The ES2846 device combines a HomePNA 2.0-compliant
MAC/PHY transceiver, a 10/100 IEEE 802.3 MAC device, and a
V.90/V.92 56k HSP modem with an analog telephone line
interface and a PCI 2.2-compliant bus interface designed into the
device architecture. This advanced high-level dual-MAC device
integration allows the use of the ES2846 for desktop and laptop
systems as a host-based modem solution, a 10/100 Ethernet
connection, or a home network connection that complies with the
HomePNA 2.0 specification, either individually or concurrently.
The ES2851 is the analog front end device for the SuperLink
MLP16 solution, and provides the HomePNA 2.0 line interface
functionality. Only minimal additional components, such as
resistive hybrids and assorted magnetics, are required to
implement the HomePNA 2.0 line interface functionality.
The ES2846 is available in an industry-standard 128-pin low-
profile quad flat pack (LQFP) package. The ES2851 is available
in an industry-standard 48-pin LQFP package.
HomePNA FEATURES
Fully compliant with HomePNA 2.0 collision resolution
specification for packet buffering, collision detection, and
retransmission logic.
Adaptive equalizer for robust packet filtering over time and
impaired channels.
Address filtering.
Highly integrated MAC/PHY, supporting both HomePNA 2.0
and HomePNA 1.1:
ES2846 HomePNA/LAN/Modem.
ES2851 HomePNA AFE.
Compliant with HomePNA 10M8 (HomePNA 2.0) and 1M8
(HomePNA 1.1) Interface Specifications:
Automatic mode configuration switches between
HomePNA 2.0/1.1 modulation and protocol, based on
capabilities of destination station on the network.
Automatic rate adaptation (HomePNA 2.0 4-Mbps to
16-Mbps).
Quality-of-service (QoS) support:
Eight-level packet priority.
Dynamic priority remapping.
Distributed fair priority queuing (DFPQ) MAC extension
for low-latency multimedia packets.
Compatible with existing telephone services:
Basic telephony (POTS).
G.992.1 (G.dmt) full-rate and G.992.2 (G.lite) ADSL.
ISDN voice and data services.
Integrated crystal oscillator circuitry.
10-bit current steering DAC.
12-bit ADC.
Variable gain amplifiers.
Line drivers.
LAN FEATURES
Highly integrated MAC supporting dual-speed 10/100-Mbps
Fast Ethernet LAN.
Wake-on-LAN and RJ-45 Ethernet connections.
Integrated Media Independent Interface (MII) and Reduced
Media Independent Interface (RMII) for connecting to external
10/100-Mbps PHY transceiver.
Full-duplex operation support in both MII/RMII ports with
independent TX and RX channels.
MODEM FEATURES
V.90/V.92-Data/Fax/TAM.
Integrated AC-Link to interface to modem AFE (ES2828).
Complaint with PC2001 system design guidelines.
Wake-on-ring, caller ID and RJ-11 tip-and-ring connections.
Worldwide homologation and ITU V.250, V.251, and V.253.
16-bit ADC and DAC with built-in anti-aliasing, digital
interpolation, decimation, reconstruction, and analog output
low-pass filters.
POWER MANAGEMENT
ACPI 2.0 and PCI PM 1.1 compliant.
PCI 2.2 bus interface supports both 3.3V and 5.0V signaling.
Separate 1.5V and 3.3V digital power supplies utilized.
Link integrity functions.
2
SAM0392-061302
ESS Technology, Inc.
ES2846/ES2851 PRODUCT BRIEF
ES2846 PINOUT
DRIVER SOFTWARE SUPPORT (HomePNA 2.0
and LAN)
Windows 98SE/ME/2000/XP.
NDIS 5.0.
DRIVER SOFTWARE SUPPORT (Modem)
Windows 98SE/ME/2000/XP.
ES2846 PINOUT
Figure 1 depicts the device pinout for the ES2846.
Figure 1 ES2846 Device Pinout
1
96
97
64
33
32
128
65
ES2846S
128-Pin LQFP
AD2
4
CB
E3
#
I
D
SEL
V
D
D_C
O
RE
AD2
3
AD
22
AD2
1
AD2
0
AD1
9
AD1
8
AD1
7
AD1
6
GND
CB
E2
#
FR
AM
E#
IRD
Y
#
TR
DY
#
D
E
VSE
L#
ST
OP
#
PA
R
CB
E1
#
V
DD_
I
O
AD
13
AD1
4
AD1
5
AD
12
AD
1
1
GN
D
SERR#
AD10
AD9
AD8
CBE0#
VDD_IO
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VAUX_IO
PWR_RST#
RST_PHY#
ECS
RXER/RX_ER
RXDV/CRS_DV
COL/SPEED10
CRS
RXCLK
GND
RXD0
RXD1
RXD2
RXD3
GND
IRQ#
EDIN
VAUX_CORE
EC
LK
ED
OUT
VA
U
X
_
I
O
MDI
O
MD
C/
RMI
I
_
MOD
E
TX
CLK
/
RE
FC
LK
GN
D
GN
D
TX
D2
TX
D1
TX
D0
TX
D3
L
I
N
K
_ST1
SL_P
WD
N
VA
U
X
_
C
O
R
E
VA
U
X
_
C
O
R
E
SL_RX5
SL_R
X4
SL_R
X3
S
L_RX
0
S
L_RX
1
SL_R
X2
SL_C
LK
V
A
UX
_PLL
GN
D_P
L
L
S
L_TX4
S
L_TX0
SL_T
X1
SL_TX
2
S
L_TX3
SL_R
S
T
#
T
XEN
SL_MODE0
SL_MODE1
GND
116
117
118
119
120
121
122
123
124
125
126
127
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
95 94 93
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
92 91 90
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
45
44
34
35
36
37
38
39
43
42
41
40
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
2 3 4 5 6 7 8 9 10 11 12 13 14 15
46
47
AD
2
5
AD
2
6
AD
2
7
AD
2
8
GND
PME#
LINK_LED#
ACT_LED#/GPIO0
VAUX_CORE
SDATA_IN
WOL/VAUXP
GND
GND
OSCI
OSCO
VAUX_IO
DSPK
SYNC
BIT_CLK
SDATA_OUT
VDD_IO
VDD_IO
CLKRUN#
INTA#
PCIRST#
PCICLK
GND
GND
PCIGNT#
PCIREQ#
AD31
AD30
AD29
ESS Technology, Inc.
SAM0392-061302
3
ES2846/ES2851 PRODUCT BRIEF
ES2846 PIN DESCRIPTION
ES2846 PIN DESCRIPTION
The ES2846 pin descriptions are listed in Table 1.
Table 1 ES2846 Pin Description
Names
Pin Numbers
I/O
Definitions
AD[31:0]
1:5, 9:16, 27:31,
34:36, 39:46,
126:128
I/O
Address and data lines from the PCI bus.
CBE[3:0]#
6, 18, 25, 37
I/O
PCI command/byte enable. During address phase of a transaction, these pins
define the bus command. During data phase, these pins define the byte enable.
IDSEL
7
I
ID select.
VDD_CORE
8
P
1.5V VDD core power supply.
GND
17, 32, 56, 57, 71, 72,
99, 100, 107, 108,
122, 123
G
Ground.
FRAME#
19
I/O
Cycle frame.
IRDY#
20
I/O
Initiator ready.
TRDY#
21
I/O
Target ready.
DEVSEL#
22
I/O
Device select .
STOP#
23
I/O
Stop transaction.
PAR
24
I/O
Parity.
VDD_IO
26, 38, 116, 117
P
3.3V VDD I/O power supply.
SERR#
33
O
System bus error.
VAUX_IO
47, 67, 111
P
3.3V V
AUX
I/O power supply.
PWR_RST#
48
I
Power-on reset. This is an active-low input signal when a power-on-reset event
occurs.
ECS
49
O
EEPROM chip select output for Ethernet/HomePNA.
RST_PHY#
50
O
Reset Ethernet PHY.
RXER
51
I
Receive error input for MII mode. Indicates that external Ethernet PHY transceiver
has detected coding errors in receive data frame currently being transmitted to
RXD[3:0]. RXER is ignored while RXDV is deasserted.
RX_ER
I
Receive error input for RMII mode. Indicates that external Ethernet PHY transceiver
has detected coding errors in receive data frame currently being transmitted to
RXD[1:0]. RX_ER is ignored while RX_DV is deasserted.
RXDV
52
I
Receive data valid from external Ethernet PHY. When selected as RXDV input,
indicates valid received data is being presented to RXD[3:0] and that RXCLK is
synchronous to the receive data. Asserted before rising edge of RXCLK and
remains asserted until after rising edge of RXCLK.
CRS_DV
I
Carrier sense/receive data valid. Asserted asynchronously by the external Ethernet
PHY when the receive medium is nonidle. In 10Base-T mode, carrier is detected
when squelch is passed in RMII mode.
4
SAM0392-061302
ESS Technology, Inc.
ES2846/ES2851 PRODUCT BRIEF
ES2846 PIN DESCRIPTION
COL
53
I
Collision. When selected as COL, asserted by external Ethernet PHY whenever a
collision is detected.
SPEED10
I
Speed select. Acts as toggle for 10-Mbps and 100-Mbps operation for external
Ethernet PHY transceiver in RMII mode.
CRS
54
I
Carrier sense input from external Ethernet PHY.
RXCLK
55
I
Receive clock input. Provides nibble rate clock timing reference for output transfer
of RXDV, RXD[3:0], and RXER signals in MII mode.
Provides nibble rate clock
timing reference for the output transfer of CRS_DV, RXD[1:0] and RX_ER
in RMII mode.
Operates at 2.5 MHz in 10 Mbps (10Base-T) mode and 25 MHz in
100 Mbps (100Base-T) mode.
IRQ#
58
I
Interrupt request from external Ethernet PHY.
RXD[3:0]
59:62
I
Receive data input pins from external Ethernet PHY. In RMII mode, only RXD[1:0]
are defined.
VAUX_CORE
63, 80, 81, 104
P
1.5V V
AUX
core power supply.
EDIN
64
I
EEPROM data input for both Ethernet and HomePNA functions.
ECLK
65
O
EEPROM clock output for both Ethernet and HomePNA functions.
EDOUT
66
O
EEPROM data output for Ethernet and HomePNA functions.
MDIO
68
I/O
Functions as the MII management data input/output from external Ethernet PHY.
Acts as an output during the header portion of management frame transfers and
during the data portion of write operations. Also acts as an input during the data
portion of read operations.
MDC
69
O
MII Management Data Clock output to external Ethernet PHY.
RMII_MODE
I
RMII_MODE enable. Strap option pin latched at power-on reset. The ES2846
supports both the MII and RMII modes of operation. When the RMII_MODE signal
is high, the RMII mode of operation is supported. When the RMII_MODE signal is
low at power-on reset, the MII mode of operation is supported.
TXCLK
70
I
Transmit clock input from external Ethernet PHY. When selected as TXCLK,
provides timing reference for transfer of the transmitted data in MII mode. Operates
at 2.5 MHz in 10 Mbps (10Base-T) mode and at 25 MHz in 100 Mbps (100Base-T)
mode.
REFCLK
I
Reference clock input. When selected as REFCLK, provides continuous clock
timing reference from MAC engine for CRS_DV, RXD[1:0], TXEN, TXD[1:0], and
RX_ER in RMII mode. Operates at 50 MHz 50 ppm, with a duty cycle between
35% and 65% in RMII mode.
TXEN
73
O
Transmit enable pin to external Ethernet PHY. Indicates that ES2846 is presenting
valid data on TXD[3:0].
TXD[3:0]
74:77
O
Transmit data output pins to external Ethernet PHY. In RMII mode, only TXD[1:0]
are defined.
LINK_ST1
78
I
Link status Interface input from external Ethernet PHY.
SL_PWDN
79
O
Power down control output pin to ES2851.
SL_RX[5:0]
82:87
I
Receive data input pins from ES2851.
SL_CLK
88
I
Crystal clock input from ES2851, operated at 64 MHz.
Table 1 ES2846 Pin Description (Continued)
Names
Pin Numbers
I/O
Definitions
ESS Technology, Inc.
SAM0392-061302
5
ES2846/ES2851 PRODUCT BRIEF
ES2846 PIN DESCRIPTION
VAUX_PLL
89
P
1.5V V
AUX
PLL power supply.
GND_PLL
90
G
Ground for internal PLL.
SL_TX[4:0]
91:95
O
Transmit data output to ES2851.
SL_RST#
96
O
Reset output to ES2851.
SL_MODE
[1:0]
97, 98
O
Mode select output to ES2851.
PME#
101
O
Power management enable interrupt output to wake up the system.
LINK_LED#
102
OD
Open drain; indicator of good link for HomePNA PHY operation.
ACT_LED#
103
OD
Open drain pin; link activity indicator at transmit or receive data.
GPIO0
I/O
General purpose I/O pin GPIO0 when selected.
SDATA_IN
105
I
Serial data input from AC-Link interface.
VAUXP
106
I
V
AUX
support detection. V
AUXP
is driven high at reset to indicate that ACPI is
supported with D3
cold
state. No support when driven low.
WOL
O
Wake-on-LAN signal output. The ES2846 asserts this signal when a change is
detected in link status, Magic Packet
TM
or sample frame events.
OSCI
109
I
Crystal clock input operates at 24.576 MHz.
OSCO
110
O
Crystal clock output.
DSPK
112
O
Modem speaker digital output.
SYNC
113
O
AC-Link serial data frame sync output.
BIT_CLK
114
I/O
AC-Link 12.288 MHz serial data clock.
SDATA_OUT
115
O
AC-Link serial data output.
CLKRUN#
118
I/O
Input/output for PCI clock status and output to start or accelerate clock function.
INTA#
119
OD
Interrupt A request output. INTA# is the level triggered interrupt pin dedicated to
servicing internal device interrupt requests.
PCIRST#
120
I
PCI bus reset.
PCICLK
121
I
PCI bus clock input.
PCIGNT#
124
I
PCI grant input.
PCIREQ#
125
O
PCI request output.
Table 1 ES2846 Pin Description (Continued)
Names
Pin Numbers
I/O
Definitions
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