512K x 8
Radiation Hardened
Static RAM 3.3 V
212A625
BAE SYSTEMS 9300 Wellington Road Manassas, Virginia 20110-4122
Product Description
Radiation
Fabricated with RHCMOS5XL 0.35 m Process for
Strategic rad hard or R25 0.25 m Commercial
process for rad hard
Radiation Hardened Total Dose hardness through
1x10
6
rad(Si)
Commercial Space Total Dose hardness of 100Krads
Neutron Hardness through 1x10
14
N/cm
2
Dynamic and Static Transient Upset Hardness
through 1x10
9
rad(Si)/s
Soft Error Rate of < 1x10
-11
Upsets/Bit-Day
Dose Rate Survivability through 1x10
12
rad(Si)/s
Latchup Free
Features
Other
Read/Write Cycle Times
30 ns and 40 ns (-55C to
125C)
Read/Write Cycle Time 55ns (limited temperature
range)
SMD Number TBD
Asynchronous Operation
CMOS Compatible I/O
Single 3.3 V 5% Power Supply
Low Operating Power
Packaging Options
40-Lead Flat Pack (1.130" x 1.065)
General Description
The 512K x 8 radiation hardened static RAM is
composed of one 512K x 8 SRAM memory die
assembled in a single, ceramic substrate.
Each die is a high performance 524,288 word x
8-bit static random access memory with
industry-standard functionality. It is fabricated
with BAE SYSTEMS' radiation hardened
technology and is designed for use in systems
operating in strategic radiation environments; It
is fabricated using commercial 0.25 m
technology for commercial space applications.
The RAM operates over the full military
temperature range and requires a single 3.3 V
5% power supply. The RAM is available with
CMOS compatible I/O. Power consumption is
typically less than 25mW/MHz in operation, and
less than 15 mW in the low power disabled
mode. The RAM read operation is fully
asynchronous, with an associated typical
access time of 30 nanoseconds.
BAE SYSTEMS' enhanced bulk CMOS
technology is radiation hardened through the
use of advanced and proprietary design, layout,
and process hardening techniques.
2
Functional Diagram
Signal Definitions
A: 0-18
DQ: 0-7
S
Address input pins that select a particular
eight-bit word within the memory array.
Bi-directional data pins that serve as data
outputs during a read operation and as data
inputs during a write operation.
Negative chip select, when at a low level,
allows normal read or write operation. When at
a high level, S forces the SRAM to a
precharge condition, holds the data output
drivers in a high impedance state and disables
the data input buffers only. If this signal is not
used, it must be connected to GND.
Negative write enable, when at a low level, activates a
write operation and holds the data output drivers in a
high impedance state. When at a high level, W allows
normal read operation.
Negative output enable, when at a high level holds the
data output drivers in a high impedance state. When at
a low level, the data output driver state is defined by S,
W, and E. If this signal is not used it must be connected
to GND.
Chip enable, when at a high level allows normal
operation. When at a low level, E forces the SRAM to a
precharge condition, holds the data output drivers in a
high impedance state and disables all the input buffers
except the S input buffer. If this signal is not used, it
must be connected to V
DD
.
W
G
E
Notes:
1) V
IN
for don't care (X) inputs = V
IL
or V
IH
.
2) When G = high, I/O is high-Z.
3) To dissipate the minimum amount of
standby power when in standby mode:
S = V
DD
and E = GND. All other input
levels may float.
Truth Table
A16 - A18
A13 - A15
A0 - A7
W
G
S
E
DQ0-DQ7
A8-A12
Block Address Decoder
Sub Array Decoder
Row Address Decoder
((256 x 32) x 8 x 8) x 8
Memory Cell Array
8 Bit Word Input/Output
Column Address Decoder
Mode
Inputs
(1),(2)
E
High
High
X
Low
W
Low
High
X
X
G
X
Low
X
X
I/O
Data-In
Data-Out
High-Z
High-Z
Power
Active
Active
Standby
Standby
Write
Read
Standby
Standby
(3)
S
Low
Low
High
X
3
Notes:
Note:
1)All voltages referenced to GND.
Power shall be applied to the device only in the following
sequences to prevent damage due to excessive currents:
Power-Up Sequence: GND, V
DD
, Inputs
Power-Down Sequence: Inputs, V
DD
, GND
Absolute Maximum Ratings
Recommended Operating Conditions
Power Sequencing
Minimum
+3.14
0.0
-55
0.0
+2.0
Units
Volt
Volt
Celsius
Volt
Volt
Supply Voltage
Parameters
(1)
Supply Voltage Reference
Case Temperature
Input Logic "Low" -
Input Logic "High"
Symbol
V
DD
GND
T
C
V
IL
V
IH
Maximum
+3.46
0.0
+125
+1.0
V
DD
Minimum
-65C
-55C
-0.5 V
-0.5 V
-0.5 V
(Class 1)
Storage Temperature Range (Ambient)
Applied Conditions
(1)
Operating Temperature Range (T
case
)
Positive Supply Voltage
Input Voltage
(2)
Output Voltage
(2)
Power Dissipation
(3)
Lead Temperature (Soldering 5 sec)
Electrostatic Discharge Sensitivity
(4)
Maximum
+150C
+125C
+5.5 V
V
DD
+ 0.5 V
1 W @ 20MHz
+250C
V
DD
+ 0.5 V
1) Stresses above the absolute maximum rating may cause permanent
damage to the device. Extended operation at the maximum levels may
degrade performance and affect reliability. All voltages are with
reference to the module ground leads.
2) Maximum applied voltage shall not exceed +5.5 V.
3) Not tested.
4) Class as defined in MIL-STD-883, Method 3015.
4
167
10%
1.73V
50 pF 10%
Output Load Circuit
DC Electrical Characteristics
1) Typical operating conditions: -55C
T
case
+125C; 3.14 V
V
DD
3.46 V; unless otherwise specified.
Notes:
Device Type
Limits
All
All
All
All
All
All
All
Minimum
2.4
Vdd - 0.1
1.5
-5.0
-10
2.0
Test
Supply Current
(Cycling Selected)
Supply Current
(Cycling De-Selected)
Supply Current
(Standby)
Data Retention Current
Data Retention Voltage
Input Leakage
Output Leakage
C
in
C
out
High Level Output Voltage
Low Level Output Voltage
High Level Input Voltage
Low Level Input Voltage
Symbol
I
DD1
V
OH
I
DD2
I
DD3
I
DR
V
OL
V
DR
V
IH
V
IL
I
ILK
I
OLK
All
All
All
All
All
Maximum
0.05
5.0
10
0.8
10
10
0.4
1.0
2.0
2.0
Units
V
A
A
V
V
V
V
pF
pF
mA
mA
mA
mA
S = V
IL
= GND
Test Conditions
(1)
V
DD
= 1.5 V
V
DD
= V
DR
0 V
V
IN
3.46 V
By Design/
Verified By
Characterization
I
OH
= -4 mA
I
OH
= -200 A
I
OL
= 200A
0 V
V
OUT
3.46 V
By Design/
Verified By
Characterization
I
OL
= 8 mA
F = 0 MHz =1/t
AVAV(min)
E = V
IL
= GND
S= V
DD
= V
DD
F = F
MAX
1/t
AVAV(min)
E = V
IL
=GND
S = V
IH
= V
DD
F = F
MAX
= 1/t
AVAV(min)
E = V
ih
=V
DD
No Output Load
x3x
x4x
x5x
250
180
145
5
Read Cycle AC Timing Characteristics
(1)
Notes:
Device Type
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test
Read Cycle Time
Chip Select to Output Active
Output Enable to Output Active
Chip Enable to Output Active
Address Access Time
Chip Select Access Time
Chip Enable Access Time
Chip Select to Output Disable
Output Hold After Address Change
Output Enable Access Time
Minimum or
Maximum
Minimum
Minimum
Minimum
Minimum
Maximum
Maximum
Maximum
Maximum
Minimum
Maximum
X3X
X3X
X3X
X3X
X3X/X4X
X3X
X5X
X4X
X3X
X5X
X5X
X5X
X5X
X4X
X4X
X4X
X4X
X5X
X4X
X3X
X5X
All
All
All
Limits
30
30
30
30
12/15
12
15
15
55
55
55
55
40
40
40
40
24
15
12
15
0
0
0
0
All
Symbol
t
AVAV
t
AVQV
t
SLQV
t
EHQV
t
GLQV
t
SLQX
t
EHQX
t
GLQX
t
SHQZ
t
AHQX
t
ELQZ
t
GHQZ
1) Typical operating conditions: V
DD
=5.0V; TA = 25 C , pre-radiation.
Test Conditions: -55 C
T
case
+125C; 3.14 V
V
DD
3.46 V; unless otherwise specified.
12
ns
X5X
X4X
15
15
Maximum
Output Enable to Output Disable
Chip Disable to output Disable
Maximum
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