Revision 1.1
Jan. 2004
1
R0201-
STC62WV12816
Very Low Power/Voltage CMOS SRAM
128K X 16 bit
Wide Vcc operation voltage : 2.4V ~ 5.5V
Very low power consumption :
Vcc = 3.0V C-grade: 29mA (@55ns) operating current
I -grade: 30mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
0.3uA(Typ.) CMOS standby current
Vcc = 5.0V C-grade: 60mA (@55ns) operating current
I -grade: 62mA (@55ns) operating current
C-grade: 53mA (@70ns) operating current
I -grade: 55mA (@70ns) operating current
1.0uA(Typ.) CMOS standby current
High speed access time :
-55 55ns
-70 70ns
Automatic power down when chip is deselected
Three state outputs and TTL compatible
The
STC62WV12816 is a high performance , very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.3uA at 3.0V /25
o
C and maximum access time of 55ns at 3.0V/ 85
o
C.
Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable(OE) and three-state output drivers.
The
STC62WV12816 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The
STC62WV12816 is available in DICE form , JEDEC standard 44-pin
TSOP Type II package and 48-ball BGA package.
DESCRIPTION
FEATURES
BLOCK DIAGRAM
PRODUCT FAMILY
PIN CONFIGURATIONS
STC International Limited
. reserves the right to modify document contents without notice.
STC62WV12816
SPEED
( ns )
STANDBY
( I
CCSB1
, Max )
Operating
( I
CC
, Max )
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
Vcc=3.0V
Vcc=3.0V
PKG TYPE
STC62WV12816DC DICE
STC62WV12816EC TSOP2-44
STC62WV12816AC
+0
O
C to +70
O
C
2.4V ~5.5V
55/70
3.0uA
53mA
BGA-48-0608
STC62WV12816DI DICE
STC62WV12816EI TSOP2-44
STC62WV12816AI
-40
O
C to +85
O
C
2.4V ~ 5.5V
55/70
5.0uA
25mA
BGA-48-0608
STC
Row
Decoder
Memory Array
1024 x 2048
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A3 A2 A1
Data
Buffer
Input
Control
Gnd
Vcc
OE
WE
CE
DQ15
DQ0
A16
A5
A6
A7
A15
A13
16
16
16
16
14
128
2048
1024
20
A14
A12
A9
A4
A0
A11
A8
Address
Input
Buffer
A10
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
G
H
F
E
D
C
B
A
1
2
3
4
5
6
D15
D14
VSS
D9
D8
LB
VCC
N.C.
A8
A9
D13
A12
A14
D12
D11
D10
A5
UB
OE
A3
A0
A11
A10
A13
A15
WE
D5
A16
A7
A6
D4
D3
D1
D7
D6
D2
A4
A1
A2
D0
N.C.
VSS
VCC
N.C.
CE
N.C.
N.C.
N.C.
I/O Configuration x8/x16 selectable by LB and UB pin
24mA
55mA
70ns
70ns
POWER DISSIPATION
55ns: 3.0~5.5V
70ns: 2.7~5.5V
Easy expansion with CE and OE options
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
62WV12816EC
62WV12816EI
Data retention supply voltage as low as 1.5V
Fully static operation
Vcc=5.0V
Vcc=5.0V
10uA
30uA
Revision 1.1
Jan. 2004
2
R0201-
STC62WV12816
PIN DESCRIPTIONS
STC
STC62WV12816
Name
Function
A0-A16 Address Input
These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.
CE Chip Enable Input
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins.
DQ0 - DQ15 Data Input/Output
Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
TRUTH TABLE
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
MODE
CE
WE
OE
LB
UB
D0~D7
D8~D15
Vcc CURRENT
H
X
X
X
X
High Z
High Z
I
CCSB
, I
CCSB1
Not selected
(Power Down)
X
X
X
H
H
High Z
High Z
I
CCSB
, I
CCSB1
Output Disabled
L
H
H
X
X
High Z
High Z
I
CC
L
L
Dout
Dout
I
CC
H
L
High Z
Dout
I
CC
Read
L
H
L
L
H
Dout
High Z
I
CC
L
L
Din
Din
I
CC
H
L
X
Din
I
CC
Write
L
L
X
L
H
Din
X
I
CC
L
X
X
H
H
High Z
High Z
I
CC
Revision 1.1
Jan. 2004
3
R0201-
STC62WV12816
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
DR
Vcc for Data Retention
CE Vcc - 0.2V
V
IN
Vcc - 0.2V or V
IN
0.2V
1.5 -- --
V
I
CCDR
Data Retention Current
CE Vcc - 0.2V
V
IN
Vcc - 0.2V or V
IN
0.2V
-- 0.1 1.0
uA
t
CDR
Chip Deselect to Data
Retention Time
0 -- --
ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
-- --
ns
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
C
IN
Input
Capacitance
V
IN
=0V
6
pF
C
DQ
Input/Output
Capacitance
V
I/O
=0V
8
pF
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0
O
C to +70
O
C
2.4V ~ 5.5V
Industrial
-40
O
C to +85
O
C
2.4V ~ 5.5V
1. Typical characteristics are at T
A
= 25
o
C. 2. Fmax = 1/t
RC
.
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4.I
ccs
B1_Max.
is 3uA/ 10uA at Vcc=3V/ 5V and T
A
=70
o
C. 5. Icc
_Max.
is 30mA(@3V) / 62mA(@5V) under 55ns operation.
DATA RETENTION CHARACTERISTICS
( TA = -40 to + 85
o
C )
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
3. Icc
DR_MAX.
is 0.7uA at T
A
=70
o
C.
ABSOLUTE MAXIMUM RATINGS
(1)
OPERATING RANGE
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
1. This parameter is guaranteed and not 100% tested.
DC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
SYMBOL
PARAMETER
RATING
UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
V
T
BIAS
Temperature Under Bias
-40 to +85
O
C
T
STG
Storage Temperature
-60 to +150
O
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
20
mA
STC
STC62WV12816
(3)
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
Vcc =3.0V
V
IL
Guaranteed Input Low
Voltage
(3)
Vcc =5.0V
-0.5 -- 0.8 V
Vcc =3.0V
2.0
V
IH
Guaranteed Input High
Voltage
(3)
Vcc =5.0V
2.2
-- V
cc
+0.3
V
I
IL
Input Leakage Current
Vcc = Max, V
IN
= 0V to Vcc
-- -- 1 uA
I
LO
Output
Leakage
Current
Vcc = Max,CE = V
IH
or OE = V
IH
,
V
I/O
= 0V to Vcc
-- -- 1 uA
Vcc =3.0V
V
OL
Output Low Voltage
Vcc = Max, I
OL
= 2.0mA
Vcc =5.0V
-- -- 0.4 V
Vcc =3.0V
V
OH
Output High Voltage
Vcc = Min, I
OH
= -1.0mA
Vcc =5.0V
2.4 -- -- V
Vcc =3V
70ns
25
I
CC
(5)
Operating Power Supply
Current
CE = V
IL
,
I
DQ
= 0mA, F = Fmax
(2)
Vcc =5V
70ns
-- --
55
mA
Vcc =3.0V
0.5
I
CCSB
Standby
Current-TTL
CE=V
IH
I
DQ
= 0mA
Vcc =5.0V
-- --
1.0
mA
Vcc =3.0V
0.3
5
I
CCSB1
(4)
Standby
Current-CMOS
CE
V
cc
-0.2
V
,
V
IN
V
cc
-0.2
V
or
V
IN
0.2
V
Vcc =5.0V
--
1.0 30
uA
Revision 1.1
Jan. 2004
4
R0201-
STC62WV12816
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
CYCLE TIME : 55ns
(Vcc = 3.0~5.5V)
(Vcc = 2.7~5.5V)
UNIT
t
AVAX
t
RC
Read Cycle Time
55
--
--
70
--
--
ns
t
AVQV
t
AA
Address Access Time
--
--
55
--
--
70
ns
t
ELQV
t
ACS
Chip Select Access Time
(CE)
--
--
55
--
--
70
ns
t
BA
t
BA
Data Byte Control Access Time
(LB,UB)
--
--
30
--
--
35
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
--
30
--
--
35
ns
t
E1LQX
t
CLZ
Chip Select to Output Low Z
(CE)
10
--
--
10
--
--
ns
t
BE
t
BE
Data Byte Control to Output Low Z
(LB,UB)
10
--
--
10
--
--
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
5
--
--
5
--
--
ns
t
EHQZ
t
CHZ
Chip Deselect to Output in High Z
(CE)
--
--
30
--
--
35
ns
t
BDO
t
BDO
Data Byte Control to Output High Z
(LB,UB)
--
--
30
--
--
35
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
--
--
25
--
--
30
ns
t
AXOX
t
OH
Data Hold from Address Change
10
--
--
10
--
--
ns
AC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
READ CYCLE
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
LOW V
CC
DATA RETENTION WAVEFORM ( CE Controlled )
CE
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.5V
CE Vcc - 0.2V
STC
STC62WV12816
(1)
1. t
BA
is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; t
BA
is 55ns/70ns (@speed=55ns/70ns) without address toggle.
NOTE :
MIN. TYP. MAX.
MIN. TYP. MAX.
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output
Timing Reference Level
0.5Vcc
Output Load
C
L
= 100pF+1TTL
C
L
= 30pF+1TTL
CYCLE TIME : 70ns
Revision 1.1
Jan. 2004
5
R0201-
STC62WV12816
STC
STC62WV12816
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
RC
t
OH
t
AA
D
OUT
ADDRESS
t
OH
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = V
IL
.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. The parameter is guaranteed but not 100% tested.
t
OH
READ CYCLE3
(1,4)
t
RC
t
OE
D
OUT
LB,UB
CE
OE
ADDRESS
t
CLZ
(5)
t
ACS
t
CHZ
(1,5)
t
OHZ
(5)
t
OLZ
t
AA
READ CYCLE2
(1,3,4)
t
CLZ
t
CHZ
(5)
D
OUT
LB,UB
CE
(5)
t
BA
t
ACS
t
BE
t
BDO
t
BDO
t
BA
t
BE
PDF 
ZIP