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SC-601
Speech And Music Processor
Data sheet
2002 Sensory Inc.
P/N 80-0207-A
1
Features
Advanced, integrated speech synthesizer for
high-quality sound.
Operates up to 12.32 MHz (Performs up to 12
MIPS)
Single chip solution for up to 24 Minutes of
speech (using 1.57 Mb of onboard program +
data ROM)
Supports high-quality synthesis algorithms
Such as MX, CX, Simple CX, LX, ADPCM, and
Polyphonic Music
Simultaneous speech plus music capabilities
Very low-power operation, ideal for handheld
devices
Low-voltage operation, sustainable by three
batteries
Reduced power stand-by modes, less than 10
A in deep-sleep mode
640-Word RAM
32 I/O Pins consisting of: 24 general purpose
bit configurable I/O, 8 inputs with programmable
pullup resistor and a dedicated interrupt (Key-
Scan)
Direct Speaker Driver, 32
(PDM)
One-bit comparator with edge-detection
interrupt service
Resistor-trimmed oscillator or 32.768kHz crystal
reference oscillator
Serial scan port for in-circuit emulation and
diagnostics
The SC-601 is sold in die form or 100-pin LQFP
package.
An emulator device is available in a ceramic
package for development (SC-614-P).
Description
The SC-601 is a low-cost, mixed-signal
processor that combines a speech synthesizer,
general-I/O, onboard ROM, and direct speaker
drive in a single package. The computational
unit utilizes a powerful DSP which gives the SC-
601 unprecedented speed and computational
flexibility compared with previous devices of its
type. The SC-601 supports a variety of speech
and audio coding algorithms, providing range of
options for speech duration and sound quality.
The device consists of a micro-DSP core,
embedded program, and data memory, and a
self-contained generation system. General-
purpose periphery is comprised of 32 bits of partially configurable I/O.
The core processor is a general-purpose 16-bit microcontroller with DSP capability. The basic core includes
computational unit (CU), data address unit, program address unit, two timers, eight level interrupt processor,
and several system and control registers. The core processor gives the SC-601 break-capability in emulation.
The processor is Harvard type for efficient DSP algorithm execution. It requires separate program and memory
blocks to permit simultaneous access. The ROM has a protection scheme to prevent third-party pirating. It is
configured in 32K 17-bit words.
The total ROM space is divided into three areas:
1. The lower 2K words are reserved by Sensory a built-in self-test
2. The upper 30K words are for user program/data
3. An additional 1 Mb data ROM provides for up to 24 minutes of speech.
SC-601 Block Diagram
16-Bit
Microprocessor
640-words
RAM
192 KBytes
ROM
TIMER 1
TIMER 2
PLLM
10-Bit
DAC
32 I/O
COMPARATOR
SC-601
Data sheet
2
P/N 80-0207-A
2002 Sensory Inc.
The data memory is internal static RAM. The RAM is configured in 640 17-bit words. All memories are designed
to consume minimum power at a given system clock and algorithm acquisition frequency.
A flexible clock generation system enables the software to control the clock over a wide frequency range. The
implementation uses a phase-locked loop (PLL) circuit that drives the processor clock at a selectable frequency
between the minimum and maximum achievable. Selectable frequencies for the processor clock are spaced
apart in 65.536 kHz steps. The PLL clock-reference is also selectable; either a resistor-trimmed oscillator or a
crystal-referenced oscillator may be used. Internal and external clock sources are controlled separately to
provide different levels of power management.
The periphery consists of three 8-bit wide general-purpose I/O ports and one 8-bit wide dedicated input port.
The bidirectional I/O can be configured under software control as either high-impedance inputs or as totem-pole
outputs. They are controlled via addressable I/O registers. The input-only port has a programmable pullup
option (70-k
minimum resistance) and a dedicated service interrupt. These features make the input port
especially useful as a key-scan interface.
A simple one-bit comparator is also included in the periphery. The comparator is enabled by a control register,
and its pin access is shared with two pins in one of the general-purpose I/O ports. Rounding out the SC-601
periphery is a built-in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive
capability. The functional block diagram gives an overview of the SC-601 functionality.
Functional Block Diagram
Data Sheet
SC-601
2002 Sensory Inc.
P/N 80-0207-A
3
Pin/Pad Assignment
SC-601
(top view of the die)
19
20
32
33
52
1
SC-601
(100-lead LQFP)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
75
74
73
72
71
70
69
68
67
66
65
60
59
58
57
56
NC
NC
NC
55
54
53
NC
64
NC
NC
NC
63
62
61
NC
52
NC
51
26
27
28
29
30
31
32
33
41
42
43
44
45
NC
NC
NC
NC
NC
VDD
VDD
SCANO
U
T
PE
5
PE
4
PE
3
PE
2
PE
1
34
35
36
37
38
39
40
TE
S
T
SYNC
S
Y
NCL
K
SCANI
N
RESET
_
PE
7
PE
6
46
47
48
49
50
PE
0
PL
L
OS
C
I
N
OSCO
UT
VSS
10
0
99
98
97
96
95
94
93
92
91
90
89
81
VSS
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
VDD
VSS
PC0
NC
88
87
86
85
84
83
82
PC1
PC2
PC3
PC4
PC5
PC6
PC7
80
79
78
77
76
NC
NC
NC
NC
NC
NC
NC
NC
NC
DACM
VDD
DAVP
VDD
PF7
PF6
PF5
PF4
NC
1
2
3
4
5
6
7
8
9
10
11
12
20
PF3
PF2
PF1
PF0
VSS
NC
NC
13
14
15
16
17
18
19
NC
NC
NC
NC
NC
21
22
23
24
25
NAME
PIN NO.
PAD NO.
I/O DESCRIPTION
PC0 PC7
89 82
8 1
I/O Port C general-purpose I/O (1 Byte)
PD0 PD7
99 92
18 11
I/O Port D general-purpose I/O (1 Byte)
PE0 PE7
46 39
48 41
I/O Port E general-purpose I/O (1 Byte)
PF0 PF7
16 9
31 24
I/O Port F general-purpose I/O (1 Byte)
Pins PD4 and PD4 may be dedicated to the comparator function, if the comparator enable bit is set.
Scan Port Control Signals
SCANIN
37
39
I Scan port data input
SCANOUT
33
35
O Scan port data output
SCANCLK
36
38
I Scan port clock
SYNC
35
37
I Scan port synchronization
TEST
34
36
I SC-601: test modes
The scan port pins must be bonded out on any SC-601 production board.
Reference Oscillator Signals
OSCOUT
49
51
O Resistor/crystal reference out
OSCIN
48
50
I Resistor/crystal reference in
PLL 47 49
O
Phase-lock-loop
filter
Digital-to-Analog Sound Output (DAC)
DACP
7
22
O Digital-to-analog plus output (+)
DACM
5
20
O Digital-to-analog minus output ()
Initialization
RESET_ 38
40 I
Initialization
Power Signals
V
SS
17, 50, 90, 100
32, 52, 9, 19
-
Ground
V
DD
6
, 8, 31, 32, 91 21
, 23, 33, 34, 10
- Processor power (+)
The V
SS
and V
DD
connections service the DAC circuitry. Their pins tend to sustain a higher current draw. A dedicated decoupling capacitor
across these pins is therefore required.
SC-601
Data sheet
4
P/N 80-0207-A
2002 Sensory Inc.
Absolute Maximum Ratings
Absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
DD
(see Note 1)
0.3 to 7 V
Supply current, I
DD
(see Note 2)
35 mA
Input voltage range, V
I
(see Note 1)
0.3 to VDD + 0.3 V
Output voltage range, V
O
(see Note 1)
0.3 to VDD + 0.3 V
Storage temperature range, T
A
30C to 125C
WARNING:
Stressing the SC-601 beyond the "Absolute Maximum
Ratings" may cause permanent damage. These are
stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended
exposure beyond the "Operating Conditions" may
affect device reliability.
NOTES: 1. Unless otherwise noted, all voltages are measured with respect to V
SS
.
2. The total supply current includes the current out of all the I/O pins as well as the operating current of the device.
Recommended Operating Conditions
MIN
MAX
UNIT
Supply voltage (with respect to V
SS
), V
DD
3
5.2
V
CPU clock rate (as programmed), f
(CPU)
64
12,320
kHz
Load resistance between DAC
P
and DAC
M
,
R
(DAC)
32
Operating free-air temperature, T
A
Device
functionality
0
70
C
Timing Requirements
MIN
MAX
UNIT
t
(RESET)
Reset low pulse width, while V
DD
is within specified limits
100
ns
t1
(WIDTH)
Pulse width required prior to a negative transition at pin PD3, PD5, or PF0 PF7
2
1/F
CPU
t2
(WIDTH)
Pulse width required prior to a positive transition at pin PD2 or PD4
2
1/F
CPU
While these pins are being used as interrupt inputs.
t
(RESET)
t
(RESET)
Figure 1: Initialization Timing Diagram
t1
(WIDTH)
t2
(WIDTH)
t1
(WIDTH (PD3, PD5, or F port))
t2
(WIDTH (PD2, or PD4))
Figure 2: External Interrupt Pin Pulse Width Requirements t1WIDTH and t2WIDTH
Data Sheet
SC-601
2002 Sensory Inc.
P/N 80-0207-A
5
DC Electrical Characteristics, TA = 0 to 70
C
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
Positive going threshold
2.4
Negative going threshold
1.8
V
DD
= 3 V
Hysteresis
0.6
V
Positive going threshold
3.3
Negative going threshold
2.9
RESET_ Threshold
changes
V
DD
= 5.2 V
Hysteresis
0.4
V
V
DD
= 3 V
2
3
V
DD
= 4.5 V
3
4.5
V
IH
High-level input voltage
V
DD
= 5.2 V
3.5
5.2
V
V
DD
= 3 V
0
1
V
DD
= 4.5 V
0
1.5
V
IL
Low-level
input
voltage
V
DD
= 5.2 V
0
1.7
V
I
OH
High-level output current per pin of I/O port
V
OH
= 4 V
2
mA
I
OL
Low-level output current per pin of I/O port
V
OL
= 0.5 V
5
mA
I
OH (DAC)
High-level output DAC current
V
OH
= 4 V
10
mA
I
OL (DAC)
Low-level output DAC current
V
DD
= 4.5 V
V
OL
= 0.5 V
20
mA
I
lkg
Input leakage current
Excludes OSC
IN
1
A
I
(STANDBY)
Standby current
RESET is low
0.05
10
A
I
DD
Operating current
V
DD
= 4.5 V, F
CLOCK
= 12.32 MHz
15
mA
I
(SLEEP-deep)
V
DD
= 4.5 V, DAC off, ARM set, OSC disabled
0.05
10
I
(SLEEP-mid)
V
DD
= 4.5 V, DAC off, ARM set, OSC enabled
40
60
I
(SLEEP-light)
Supply current
V
DD
= 4.5 V, DAC off, ARM clear, OSC enabled
60
100
A
V
IO
Input offset voltage
V
DD
= 4.5 V, V
ref
= 1 to 4.25 V
25
50
mV
R
(PULLUP)
F port pullup resistance
V
DD
= 5 V
70
150
K
f
(RTO-trim)
Trim
deviation
R
RTO
= 470 K
, V
DD
= 4.5 V, T
A
= 25C,
f
RTO
= 8.192 MHz (PLL setting = 7 Ch)
1%
3%
f
(RTO-volt)
Voltage
deviation
R
RTO
= 470 K
, V
DD
= 3.5 to 5.2 V, T
A
= 25C,
f
RTO
= 8.192 MHz (PLL setting = 7 Ch)
1.5%
f
(RTO-temp)
Temperature deviation
R
RTO
= 470 K
, V
DD
= 4.5 V, T
A
= 0 to 70C,
f
RTO
= 8.192 MHz (PLL setting = 7 Ch)
0.03
%/C
f
(RTO-res)
Resistance
deviation
V
DD
= 4.5 V, T
A
= 25C, R
(OSC)
= 470 K
at 1%,
f
RTO
= 8.192 MHz (PLL setting = 7 Ch)
1%
Operating current assumes all inputs are tied to either V
SS
or V
DD
with no input currents due to programmed pullup resistors. The DAC
output and other outputs are open circuited.
The best trim value is selected at nominal temperature and voltage but the deviation due to the trim error is ignored.
Typical voltage and current measurement taken at 25
C
Cannot exceed 15 mA total per internal V
DD
pin. Port A, B share 1 internal V
DD
pin; Port C, D share 1 internal V
DD
External Component Absolute Values
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
R
(RTO)
RTO external resistance
T
A
= 25C, 1% tolerance
470
K
C
(PLL)
PLL external capacitance
T
A
= 25C, 10% tolerance
3300
pF
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