Integrated Telecom Express, Inc.

I90135

Product Data Sheet

Version 1.2 (June 1999)

I90135-ADSL Digital Chip

Features

ANSI T1.413 Issue 2 standard DMT

modem with embedded, bypassable,
ATM framer

Byte interface or standard Utopia level 1

and level 2 ATM interfaces

Main functions include:

Receive Direction:
-

Rotor and adaptive frequency domain
equalizing

Demapping of DMT carriers into a
digital bitstream, including 4D trellis
coding

Error and noise monitoring on
individual carriers and pilot tones

Reed-Solomon decoding and

deinterleaving

ADSL deframing

ATM cell-specific deframing (can be
bypassed)

144-pin PQFP package

Power consumption 1 watt at 3.3V

Transmit Direction:
-

ATM cell-specific framing

ADSL framing

Reed-Solomon encoding

Mapping of digital bitstream onto DMT
carriers

Rotor and frequency domain gain

correction

General Description

ITeX's I90135 is the DMT modem and ATM

Framer of the Apollo series rate adaptive
ADSL chipset. The I90135 is intended to be
used in combination with I80134 analog

front end. In addition, the control function
of the chipset can be performed on a
dedicated external controller (see figure

1.1) or on host/control software eliminating
the need for a microcontroller (see figure
1.2).

The I90135 may be used in both ATU-C
(central office) and ATU-R (remote)

applications. The chip provides both a cell-
based UTOPIA level 1 and 2 ATM data
interface to the host and a non-ATM

synchronous bit stream.

The I90135 performs the DMT modulation,
demodulation, Reed-Solomon encoding, bit
interleaving, and 4D trellis coding.

The I90135 is in a 144-pin PQFP package.

Integrated Telecom Express, Inc.

I90135

Product Data Sheet

Version 1.2 (June 1999)

Block Diagram

Introduction

The following essential describes the
sequence of actions for the receive
direction, corresponding functions for the

transmit direction are readily derived.

DSP Front End

The DSP front end contains four parts in
the receive direction: the input selector, the
analog front end interface, the decimator

and the time equalizer. The input selector

is used internally to enable test loopbacks
inside the chip. The analog front end
interface transfers 16-bit word, multiplexed

on four input/output signals. As a result,
four dock cycles are needed to transfer one
word. The decimator receives the 16-bit

samples at 8.8 MHz (as sent by the analog
front end chip) and reduces this rate to 2.2
MHz.

Test

Module

Data Symbol Timing Unit

VCXO

DSP

Front-end

FFT/
IFFT

Rotor

Trellis

Coding

Mapper/

Demapper

Generic

Reed/

Solomon

ATM

Specific

Reset

Controller Interface

Interface Module

Clock

Test Signals

AFE

Interface

SLAP

Utopia

Reset

Controller Bus

General Purpose I/Os

Figure 2: I90135 Block Diagram

Integrated Telecom Express, Inc.

I90135

Product Data Sheet

Version 1.2 (June 1999)

The Tme Equalizer (TEQ) module is an FIR

filter with programmable coefficients. Its
main purpose is to reduce the effect of
Inter-Symbol Interferences (ISI) by

shortening the channel impulse response.
Both the decimator and TEQ can be
bypassed.

In the transmit direction, the DSP front end

includes: sidelobe filtering, clipping, delay
equalization, and interpolation. The
sidelobe filtering and delay equalization are

implemented by IIR filters, reducing the
effect of echo in FDM systems.

Clipping is a statistical process limiting the
amplitude of the output signal, optimizing
the dynamic range of the AFE.

The interpolator receives data at 2.2 MHz
and generates samples at a rate of 8.8 MHz.

DMT Modem

This computational module is a
programmable DSP unit. Its instruction set

enables functions like FFT, IFFT, scaling,
rotor, and Frequency Equalization (FEQ).
This block implements the core of the DMT

algorithm as specified in ANSI T1.413.

In the RX path, the 51 2-point FFT
transforms the time domain DMT symbol
into a frequency domain representation,

which can be further decoded by the
subsequent demapping stages. After the
first stage time domain equalization and

FFT block an essentially ICI (InterCarrier
Interferences)-free carrier information
stream has been obtained. This stream is

still affected by carrier-specific channel
distortion resulting in an attenuation of the
signal amplitude and a rotation of the signal

phase. To compensate for these effects,

the FFT is followed by a Frequency Domain

Equalizer (FEQ) and a rotor (phase shifter).

In the TX path, the IFFT transforms the

DMT symbol generated in the frequency
domain by the mapper into a time domain
representation. The IFFT block is proceed

by a fne tune gain and a rotor stage,
allowing for a compensation of the possible

frequency mismatch between the master
clock frequency and the transmitter clock
frequency (which may be locked to another

reference). The FFT module is a slave DSP
engine controlled by the transceiver
controller. It works off line and

communicates with the other blocks via
buffers controlled by the DSTU block. The
DSP executes a program stored in a RAM

area, a very

flexible implementation open

for future enhancements.

DPLL

The Digital PLL module receives a metric for
the phase error of the pilot tone. In

general, the clock frequencies at the
transmitter and receiver do not match
exactly. The phase error is filtered and

integrated by a low pass filter, yielding an
estimation of the frequency offset. Various

processes can use this estimate to deal with

the frequency mismatch. In particular,

small accumulated phase error can be
compensated in the frequency domain by a
rotation of the received code constellation

(Rotor). Larger errors are compensated in
the time domain by inserting or deleting
clock cycles in the sample input sequence.

Integrated Telecom Express, Inc.

I90135

Product Data Sheet

Version 1.2 (June 1999)

Mapper/Demapper, Monitor, Trellis

Coding, FEQ Update

The demapper converts the constellation
points computed by the FFT to a block of

bits. This essentially consists in identifying
a point in a 2D QAM constellation plane.
The demapper supports trellis coded

demodulation and provides a Viterbi
maximum likelihood estimator. When the
trellis is active, the demapper receives an

indication for the most likely constellation
subset to be used. In the transmit

direction, the mapper performs the inverse
operation, mapping a block of bits into one

constellation point (in a complex x+jy

representation) which is passed to the IFFT
block. The Trellis Encoder generates
redundant bits to improve the robustness of

the transmission, using a 4-Dimensional
Trellis Coded Modulation scheme. The
Monitor computes error parameters for

carriers specified in the Demapper process.
Those parameters can be used for updates

of adaptive filters coefficient, clock phase
adjustments, error detection, etc. A series
of values is constantly monitored, such as

signal power, pilot phase deviations, symbol
erasures generation, loss of frame, etc.

Pin Diagram

VSS

AD_0

AD_1

AD_2

VDD

AD_3

AD_4

VSS

AD_5

AD_6

VDD

AD_7

AD_8

AD_9

VSS

AD_10

AD_11

VDD

AD_12

VSS

PCLK

VDD

AD_13

AD_14

AD_15

VSS

BE1

ALE

VDD

CSB

WR_RDB

RDYB

OBC_TYPE

INTB

RESETB

VSS

108

VDD

107

SLT_REQ_F

106

SLT_DAT_S0

105

SLT_DAT_S1

104

SLT_DAT_F0

103

SLT_DAT_F1

102

VSS

101 SLT_FRAME_F
100 SLAP_CLOCK
99

SLR_VAL_F

SLR_DAT_F0

SLR_DAT_F1

SLR_VAL_S

VDD

SLR_DAT_S0

SLR_DAT_S1

92 SLR_FRAME_S
91

VSS

90 SLR_FRAME_F
89 U_TX_ADDR_0
88 U_TX_ADDR_1
87 U_TX_ADDR_2
86

VDD

85 U_TX_ADDR_3
84 U_TX_ADDR_4
83

U_TX_DATA_0

U_TX_DATA_1

VDD

U_TX_DATA_2

U_TX_DATA_3

U_TX_DATA_4

U_TX_DATA_5

VDD

U_TX_DATA_6

U_TX_DATA_7

VSS

VD
D

1
4

FTX

_
3

1
4

FTX

_
2

1
4

VS
S

1
4

FTX

_
1

1
4

FTX

_
0

1
3

I
DDQ

13
8

VD
D

1
3

13
6

13
5

VS
S

1
3

13
3

13
2

VD
D

1
3

CT
RLD

13
0

12
9

CL
WD

12
8

VS
S

1
2

RX
D_
3

1
2

RX
D_
2

1
2

RX
D_
1

1
2

RX
D_
0

1
2

VD
D

1
2

PD
O

1
2

GP
_OU

12
0

ST
SE

1
1

TR
S

1
1

VS
S

1
1

TC
K

1
1

VD
D

1
1

TMS

1
1

TD
O

1
1

TD
I

1
1

L
T_
FR
A

1
1

SL
T

_
S

1
1

VS
S

1
0

U_
RX
DA
T

U_
RX
_A
DDR

GP
_I

N_
0

GP
_I

N_
1

U_
T

_RE

U_
RX
_R
E

U_
RX
CL
K

U_
RX
S

U_
RX
_C
LA
V

U_
RX
E

U_
T

CLK

U_
T

_CL

7
1

EN
BB

AFE

TEST

SLAP

UTOPIA

OBC

Figure 3: Pinout (Topside View)

Электронный компонент: I90135

Document Outline