ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

1/28

SDRAM

512K x 16Bit x 2Banks

Synchronous

DRAM

FEATURES

2.5V power supply

LVCMOS compatible with multiplexed address

Dual banks operation

MRS cycle with address key programs
-

CAS Latency (1, 2 & 3 )

Burst Length (1, 2, 4, 8 & full page)

Burst Type (Sequential & Interleave)

EMRS cycle with address key programs.

All inputs are sampled at the positive going edge of the

system clock

Burst Read Single-bit Write operation

Special Function Support.
-

PASR (Partial Array Self Refresh )

TCSR (Temperature compensated Self Refresh)

DS (Driver Strength)

DQM for masking

Auto & self refresh

32ms refresh period (2K cycle)

GENERAL DESCRIPTION

The M12S16161A is 16,777,216 bits synchronous high
data rate Dynamic RAM organized as 2 x 524,288 words by
16 bits, fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.

ORDERING INFORMATION

Part NO.

MAX

Freq.

Interface Package Comments

M12S16161A-10T 100MHz

Non-Pb-free

M12S16161A-15T 66MHz

Non-Pb-free

M12S16161A-10TG

100MHz

Pb-free

M12S16161A-15TG

66MHz

LVCMOS

TSOP(II)

Pb-free

PIN CONFIGURATION (TOP VIEW)

DQ0
DQ1
V

SSQ

DQ2
DQ3
V

DDQ

DQ4
DQ5
V

SSQ

DQ6
DQ7
V

DDQ

LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

DQ15
DQ14
V

SSQ

DQ13
DQ12
V

DDQ

DQ11
DQ10
V

SSQ

DQ9
DQ8
V

DDQ

N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
V

50PIN TSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH)

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

2/28

FUNCTIONAL BLOCK DIAGRAM

PIN FUNCTION DESCRIPTION

Pin

Name

Input Function

CLK

System Clock

Active on the positive going edge to sample all inputs.

Chip Select

Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.

CKE

Clock Enable

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.

A0 ~ A10/AP

Address

Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7

Bank Select Address

Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.

RAS

Row Address Strobe

Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

CAS

Column Address Strobe

Latches column addresses on the positive going edge of the CLK with

CAS low.

Enables column access.

Write Enable

Enables write operation and row precharge.
Latches data in starting from CAS , WE active.

L(U)DQM

Data Input / Output Mask

Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.

Bank Select

Data Input Register

Column Decoder

Latency & Burst Length

Programming Register

512K x 16

Timing Register

CLK

CKE

RAS

CAS

L(U)DQM

LDQM

LWCBR

DQi

LDQM

LWE

LRAS

LCBR

LWE

LCAS

CLK

ADD

LCKE

Ad
dr

s
R

e
gi

s
t
er

o
w

u
ff

e
r

Ref
r
es

h
Co

unt
er

Ro
w

e
c
o
d
e
r

Sen

s
e A
M

Col
.
Buf

f
er

LRAS

LC
BR

I/
O

Con

t
r
o
l

Outpu

t
B

u
f
f
er

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

3/28

DQ0 ~ 15

Data Input / Output

Data inputs/outputs are multiplexed on the same pins.

VDD/VSS

Power Supply/Ground

Power and ground for the input buffers and the core logic.

VDDQ/VSSQ Data Output Power/Ground

Isolated power supply and ground for the output buffers to provide improved
noise immunity.

N.C/RFU

No Connection/
Reserved for Future Use

This pin is recommended to be left No Connection on the device.

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to V

OUT

-1.0 ~ 4.6

Voltage on V

supply relative to V

DDQ

-1.0 ~ 4.6

Storage temperature

STG

-55 ~ + 150

�

Power dissipation

0.7

Short circuit current

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to V

= 0V, T

= 0

�

~ 70

�

)

Parameter

Symbol

Min

Typ

Max

Unit

Note

2.3 2.5 2.7 V

Supply voltage

DDQ

1.65 - 2.7 V 1

Input logic high voltage

0.8 x V

DDQ

- V

DDQ

+0.3 V

Input logic low voltage

-0.3 0 0.3 V 2

Output logic high voltage

DDQ

� 0.2

=-0.1mA

Output logic low voltage

- - 0.2

= 0.1mA

Input leakage current

-10 - 10

Output leakage current

-10 - 10

uA 4

Note : 1. ESMT can support VDDQ 2.5V (in general case) and 1.8V (in specific case) for VDD 2.5V products. Please contact

to sales. Dept. when condisering the use fo VDDQ 1.8V (min 1.65V).

2.V

(max) = 4.6V AC for pulse width

3ns acceptable.

3.V

(min) = -1.0V AC for pulse width

3ns acceptable.

4.Any input 0V

DDQ

, all other pins are not under test = 0V.

5.Dout is disabled, 0V

OUT

DDQ

CAPACITANCE (V

= 2.5V, T

= 25

�

, f = 1MHz)

Pin

Symbol

Min

Max

Unit

CLOCK C

CLK

- 4.0 pF

RAS , CAS , WE , CS , CKE, LDQM,

UDQM

- 4.0 pF

ADDRESS C

ADD

- 4.0 pF

DQ0 ~DQ15

OUT

- 6.0 pF

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

4/28

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, T

= 0

�

~ 70

�

)

Version

Parameter

Symbol

Test Condition

CAS

Latency

-10

-15

Unit Note

Operating Current
(One Bank Active)

CC1

Burst Length = 1
t

(min), t

(min), I

= 0mA

mA 1

CC2P

CKE

(max), t

=15ns

Precharge Standby
Current in power-down
mode

CC2PS

CKE

(max), CLK

(max), t

0.2

CC2N

CKE

(min), CS

(min), t

=15ns

Input signals are changed one time during 30ns

- mA

Precharge Standby
Current in non
power-down mode

CC2NS

CKE

(min), CLK

(max), t

Input signals are stable

- mA

CC3P

CKE

(max), t

=15ns

Active Standby Current
in power-down mode

CC3PS

CKE

(max), CLK

(max), t

CC3N

CKE

(min), CS

(min), t

=15ns

Input signals are changed one time during 30ns

15 mA

Active Standby Current
in non power-down
mode
(One Bank Active)

CC3NS

CKE

(min), CLK

(max), t

Input signals are stable

- mA

Operating Current
(Burst Mode)

CC4

= 0Ma, Page Burst

All Band Activated, tCCD = tCCD (min)

35 25

Refresh Current

CC5

(min)

35 25

TCSR range

�

2 Banks

100

120

1 Bank

110

1/2 Bank

100

Self Refresh Current

CC6

CKE

0.2V

1/4 Bank

Deep Power Down
Current

CC7

CKE

0.2V 10

Note: 1.Measured with outputs open. Addresses are changed only one time during t

(min).

2.Refresh period is 32ms. Addresses are changed only one time during t

(min).

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

5/28

AC OPERATING TEST CONDITIONS (V

=2.5V

�

0.2V,T

= 0 C

� ~ 70 C

� )

Parameter

Value

Unit

Input levels (Vih/Vil)

0.9 x V

DDQ

/ 0.2

Input timing measurement reference level

0.5 x V

DDQ

Input rise and fall time

tr / tf = 1 / 1

Output timing measurement reference level

0.5 x V

DDQ

Output load condition

See Fig.2

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

-10

-15

Unit

Note

Row active to row active delay

RRD

(min) 20

30 ns

RAS to CAS delay

RCD

(min) 30

30 ns

Row precharge time

(min) 20

30 ns

RAS

(min) 50

60 ns

Row active time

RAS

(max) 100 us

Row cycle time

(min) 70

90 ns

Last data in to new col. Address delay

CDL

(min) 1 CLK

Last data in to row precharge

RDL

(min) 2 CLK

Last data in to burst stop

BDL

(min) 1 CLK

Col. Address to col. Address delay

CCD

(min) 1 CLK

CAS latency=3

CAS latency=2

Number of valid output data

CAS latency=1

ea 4

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

Minimum delay is required to complete write.

3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.

The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.

500

Z0=50

VDDQ

Output

(Fig.2) AC Output Load Circuit

20 pF

Vtt =0.5x VDDQ

VOH(DC) = VDDQ-0.2V, IOH = -0.1mA

VOL(DC) = 0.2V, IOL = 0.1mA

30 pF

Output

(Fig.1) DC Output Load circuit

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

6/28

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

-10

-15

Parameter

Symbol

Min

Max

Min

Max

Unit

Note

CAS Latency =3

CLK cycle time

CAS Latency =2

1000

ns 1

CAS Latency =3

- 9 - 12

CLK to valid
output delay

CAS Latency =2

SAC

- 12 - 12

ns 1

Output data hold time

2.5 2.5

ns 2

CLK high pulse width

3 3

ns 3

CLK low pulse width

3 3

ns 3

Input setup time

3 4

ns 3

Input hold time

1 2

ns 3

CLK to output in Low-Z

SLZ

1 1

ns 2

CAS Latency =3

- 7 - 9

CAS Latency =2

- 8 - 9

CLK to output in
Hi-Z

CAS Latency =1

SHZ

- - - 24

*All AC parameters are measured from half to half.

Note: 1.Parameters depend on programmed CAS latency.

2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.

3.Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the
parameter.

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

7/28

Mode Register

BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

Address

bus

x x 1 0 0 LTMODE

WT BL

Burst Read and Single Write (for Write

Through

Cache)

0 0 0 0 0

LTMODE

WT BL

Mode Register Set x =Don't care

A2-A0 WT=0 WT=1

000 1 1
001 2 2
010 4 4

011 8 8

100 R R
101 R R

110 R R

Burst length

111 Full

page

Sequential

Wrap type

Interleave

A6-A4

CAS Latency

000 R
001 R
010 2

011 3

100 R
101 R

110 R

Latency mode

111 R

Mode Register Write Timing

Remark R : Reserved

Mode Register W rite

CLOCK

CKE

RAS

A0-A11

CAS

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

8/28

Extended Mode Register
BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

Address

bus

1 0 0 0 0

PASR

Extended Mode Register Set x =Don't care

A2-A0 WT=0

000 2

Banks

001

1 Bank (Bank 0, BA=0)

010

1/2 Bank (BA=A10=0)

011 R

100 R
101

1/4 Bank (BA=A10=A9=0)

110 R

PASR

111 R

A6-A5 Driver

Strength

00 Full

Strength

01 1/2

Strength

10 1/4

Strength

11 R

Remark R : Reserved

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

9/28

Burst Length and Sequence

(Burst of Two)

Starting Address
(column address A0 binary)

Sequential Addressing

Sequence (decimal)

Interleave Addressing

Sequence (decimal)

0 0 , 1

0 , 1

1 1 , 0

1 , 0

(Burst of Four)

Starting Address

(column address A1-A0, binary)

Sequential Addressing

Sequence (decimal)

Interleave Addressing

Sequence (decimal)

0 0 0 , 1 , 2, 3

0 , 1 , 2, 3

0 1 1 , 2 , 3, 0

1 , 0 , 3, 2

1 0 2 , 3 , 0, 1

2 , 3 , 0, 1

11 3 , 0 , 1, 2

3 , 2 , 1, 0

(Burst of Eight)

Starting Address

(column address A2-A0, binary)

Sequential Addressing

Sequence (decimal)

Interleave Addressing

Sequence (decimal)

0 00 0,1,2, 3,4, 5 ,6,7

0 , 1 , 2, 3 , 4, 5 , 6 , 7

0 01 1,2,3, 4,5, 6 ,7,0

1 , 0 , 3, 2 , 5, 4 , 7 , 6

0 10 2,3,4, 5,6, 7 ,0,1

2 , 3 , 0, 1 , 6, 7 , 4 , 5

011 3,4,5, 6,7, 0,1, 2 3 , 2 , 1, 0 , 7, 6 , 5 , 4

1 00 4,5,6, 7,0, 1 ,2,3

4 , 5 , 6, 7 , 0, 1 , 2 , 3

1 01 5,6,7, 0,1, 2 ,3,4

5 , 4 , 7, 6 , 1, 0 , 3 , 2

110 6,7,0, 1,2, 3,4, 5 6 , 7 , 4, 5 , 2, 3 , 0 , 1

111 7 , 0 , 1, 2 , 3, 4 , 5 , 6 7 , 6 , 5, 4 , 3, 2 , 1 , 0

Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 1Mx16 divice.

POWER UP SEQUENCE

1.Apply power and start clock, attempt to maintain CKE= "H", L(U)DQM = "H" and the other pin are NOP condition at the inputs.
2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3.Issue precharge commands for all banks of the devices.

4.Issue 2 or more auto-refresh commands.

5.Issue mode register set command to initialize the mode register.

Cf.)Sequence of 4 & 5 is regardless of the order.

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

10/28

SIMPLIFIED TRUTH TABLE

COMMAND

CKEn-1 CKEn CS

RAS

CAS

DQM BA A10/AP A9~A0 Note

Mode

Set

H X L L L L X

CODE 1,2

Extended Mode Register
Set

H X L L L L X

CODE 1,2

Auto Refresh

Entry

L L L H X

L H H H

Refresh

Self Refresh

Exit

X X X X X 3

Bank Active & Row Addr.

Row Address

Auto Precharge Disable

Read &
Column Address Auto Precharge Enable

H X

Column

Address
(A0~A7)

4,5

Auto Precharge Disable

L 4

Write & Column
Address

Auto Precharge Enable

H X

L L

Column

Address
(A0~A7)

4,5

Burst Stop

Bank Selection

Precharge

Both Banks

H X

X H X

X X X

Entry

L V V V X

Clock Suspend or
Active Power Down

Exit

L H X

X X X X

X X X

Entry

L H H H X

X X X

Precharge Power Down Mode

Exit

L V V V X

DQM H

X X X

No Operation Command

L H H H

Entry H L

Deep Power Down Mode

Exit

L H X

X X X X

(V= Valid, X= Don't Care, H= Logic High , L = Logic Low)

Note:

1. OP Code: Operation Code

A0~ A10/AP, BA: Program keys.(@MRS). BA=0 for MRS and BA=1 for EMRS.

2. MRS/EMRS can be issued only at both banks precharge state.

A new command can be issued after 2 clock cycle of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".
Auto / self refresh can be issued only at both banks idle state.

4. BA: Bank select address.

If "Low": at read, write, row active and precharge, bank A is selected.
If "High": at read, write, row active and precharge, bank B is selected.
If A10/AP is "High" at row precharge, BA ignored and both banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read /write command can be issued after the end of burst.
New row active of the associated bank can be issued at t

after the end of burst.

6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but

makes
Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

11/28

Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3, Burst Length=1

: D o n ' t C a r e

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

C L O C K

C K E

C S

R A S

C A S

A D D R

W E

D Q

D Q M

A 1 0 / A P

C H

C L

C C

R o w A c t i v e

B A

*Note1

H I G H

R C D

S S

S H

S S

S H

S S

S H

S S

S H

R a

C a

C b

C c

R b

B S

R a

Q a

D b

Q c

R b

R e a d

W r i t e

R e a d

P r e c h a r g e

R o w A c t i v e

R C

R A S

R P

C C D

R A C

*Note2

*Note2,3

*Note4

*Note2

*Note2,3

*Note 3

*Note2,3

S H

S L Z

S A C

O H

S H

S S

*Note4

*Note 3

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

12/28

*Note: 1. All inputs expect CKE & DQM can be don't care when CS is high at the CLK high going edge.

2. Bank active & read/write are controlled by BA.

Active & Read/Write

0 Bank

1 Bank

3.Enable and disable auto precharge function are controlled by A10/AP in read/write command.

A10/AP

Operation

Disable auto precharge, leave bank A active at end of burst.

Disable auto precharge, leave bank B active at end of burst.

Enable auto precharge, precharge bank A at end of burst.

Enable auto precharge, precharge bank B at end of burst.

4.A10/AP and BA control bank precharge when precharge command is asserted.

A10/AP BA

precharge

0 0 Bank

0 1 Bank

1 X

Both

Banks

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

13/28

Power Up Sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

C L O C K

C K E

A D D R

D Q

D Q M

A 1 0 / A P

R P

K e y

R A a

P r e c h a r g e
A l l B a n k s

A u t o R e f r e s h

M o d e R e g i s t e r S e t

( A - B a n k )
R o w A c t i v e

: D o n ' t c a r e

R C

H i g h l e v e l i s n e c e s s a r y

H i g h l e v e l i s n e c e s s a r y

H i g h - Z

RAS

CAS

K e y

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

14/28

Read & Write Cycle at Same Bank @Burst Length = 4

*Note: 1.Minimum row cycle times is required to complete internal DRAM operation.

2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row

precharge. Last valid output will be Hi-Z(t

SHZ

) after the clock.

3.Access time from Row active command. tcc*(t

RCD

+CAS latency-1)+t

SAC

4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst)

Burst can't end in Full Page Mode.

RCD

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

RAS

CAS

ADDR

DQM

CL=2

CL=3

Cb0

O H

S AC

S H Z

RDL

Read

Row Active

Precharge

(A-Bank)

Precharge

(A-Bank)

W rite

(A-Bank)

Row Active

(A-Bank)

*Note3

*Note4

: Don't care

*Note1

Qa0

Qa1

Qa2

Qa3

Db0

Db3

Db1

Db2

Qa0

Qa1

Qa2

Qa3

Db0

Db3

Db1

Db2

R AC

RAC

RDL

Ca0

A10/AP

HIGH

*Note2

O H

S AC

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

15/28

Page Read & Write Cycle at Same Bank @ Burst Length=4

*Note :1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus

contention.

2.Row precharge will interrupt writing. Last data input, t

RDL

before Row precharge, will be written.

3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.

Input data after Row precharge cycle will be masked internally.

CLOCK

CKE

RAS

CAS

ADDR

A10/AP

CL=2

CL=3

DQM

HIGH

RCD

*Note2

Ca0

Cb0

Cc0

Cd0

Qa0

Qa1

Qb0

Qb1

Qb2

Dc0

Dc1

Dd0

Dd1

Qa0

Qa1

Qb0

Qb1

Dc0

Dc1

Dd0

Dd2

CDL

*Note1

Row Active

(A-Bank)

Read
(A-Bank)

Write
(A-Bank)

Precharge
(A-Bank)

: Don't care

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

RDL

*Note3

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

16/28

Page Read Cycle at Different Bank @ Burst Length=4

*Note: 1. CS can be don't cared when RAS , CAS and WE are high at the clock high going dege.

2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.

CLOCK

CKE

RAS

CAS

ADDR

A10/AP

CL=2

CL=3

DQM

HIGH

*Note2

RAa

CAa

RBb

RAa

Read
(A-Bank)

Row Active

Row Active
(B-Bank)

(A-Bank)

Read
(A-Bank)

Read
(B-Bank)

Read
(A-Bank)

Read
(B-Bank)

Precharge
(A-Bank)

: Don't care

CBb

CAc

CBd

CAe

QAa0

*Note1

RBb

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1

QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1

ESMT

M12S16161A

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Publication Date : Jun. 2005

Revision : 1.0

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Page Write Cycle at Different Bank @Burst Length = 4

*Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.

2.To interrupt burst write by row precharge, both the write and the precharge banks must be the same.

CLOCK

CKE

RAS

CAS

ADDR

A10/AP

DQM

HIGH

Row Active

(A-Bank)

Row Active
(B-Bank)

Write
(A-Bank)

Precharge
(Both Banks)

: Don't care

Write
(A-Bank)

Write
(B-Bank)

DAa0

DAa1 DAa2

DAa3

DBb0

DBb1

DBb2 DBb3

DAc0

DAc1

DBd0

DBd1

RAa

RBb

RAa

CAa

RBb

CBb

CAc

CBd

*Note2

CDL

RDL

*Note1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

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Read & Write Cycle with auto Precharge @ Burst Length =4

*Note: 1.t

CDL

Should be controlled to meet minimum t

RAS

before internal precharge start

(In the case of Burst Length=1 & 2 and BRSW mode)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

C L O C K

C K E

C A S

A D D R

W E

D Q

D Q M

A1 0 / A P

B A

C L = 2

C L = 3

Row Active
( A - Bank )

Row Active
( B - Bank )

Read with
Auto Precharge
( A - Bank )

A u t o P r e c h a r g e
S t a r t P o i n t
( B - B a n k )

: D o n ' t C a r e

Q a1 Q a2

Q a3

D b 1

D b 2

D b 3

D b 0

Q a0

R a

C b

R a

C a

R b

Q a1

Q a2

Q a3

D b 1

D b 2

D b 3

D b 0

Q a0

W r i t e w i t h
A u t o P r e c h a r g e
( B - B a n k )

H I G H

Auto Precharge
Start Point
( A - Bank)

C S

R A S

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M12S16161A

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Publication Date : Jun. 2005

Revision : 1.0

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Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4

*Note:1.DQM is needed to prevent bus contention.

C L O C K

C K E

A D D R

D Q

D Q M

A 1 0 / A P

R a

C a

C b

C c

R a

Q a0

Q a1

Q a2

Q a3

S H Z

Q b1

Q b0

S H Z

D c 0

D c 2

* N o t e 1

R o w A c t i v e

R e a d

C l o c k
S u s p e n s i o n

R e a d

R e a d D Q M

W r i t e

W r i t e
D Q M

C l o c k
S u s p e n s i o n

W r i t e
D Q M

: D o n ' t C a r e

C S

R A S

C A S

W E

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

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M12S16161A

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Publication Date : Jun. 2005

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Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length =Full page

*Note: 1.Burst can't end in full page mode, so auto precharge can't issue.

2.About the valid DQs after burst stop, it is same as the case of RAS interrupt.

Both cases are illustrated above timing diagram. See the label 1,2 on them.

But at burst write, burst stop and RAS interrupt should be compared carefully.

Refer the timing diagram of "Full page write burst stop cycle".

3.Burst stop is valid at every burst length.

C L O C K

C K E

A D D R

D Q

D Q M

A 1 0 / A P

B A

R A a

C A a

C A b

R A a

Q A a 0 Q Aa 1

Q A b 1

Q A b 0

Q A b 2

* N o t e 1

R o w A c t i v e
( A - B a n k )

R e a d
( A - B a n k )

B u r s t S t o p

R e a d
( A - B a n k )

: D o n ' t C a r e

H I G H

C L = 2

C L = 3

Q A a 2 Q Aa 3 Q Aa 4

Q Ab 3 Q A b 4 Q A b 5

Q A a 0 Q Aa 1

Q A b 1

Q A b 0

Q A b 2

Q A a 2 Q A a 3 Q A a 4

Q A b 3 Q A b 4 Q A b 5

P r e c h a r g e
( A - B a n k )

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

RAS

CAS

*Note2

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

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Write Interrupted by Precharge Command & Write Burst stop Cycle @ Burst Length =Full page

*Note: 1. Burst can't end in full page mode, so auto precharge can't issue.

2.Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by

AC parameter of t

RDL

DQM at write interrupted by precharge command is needed to prevent invalid write.

Input data after Row precharge cycle will be masked internally.

3.Burst stop is valid at every burst length.

C L O C K

C K E

A D D R

D Q

D Q M

A 1 0 / A P

R A a

C A a

C A b

R A a

D A a 0 D A a 1

D A b 1

D A b 0

D A b 2

R o w A c t i v e
( A - B a n k )

W r i t e
( A - B a n k )

B u r s t S t o p

W r i t e
( A - B a n k )

: D o n ' t C a r e

H I G H

D A a 2 D A a 3 D A a 4

D A b 3 D A b 4 D A b 5

P r e c h a r g e
( A - B a n k )

B D L

R D L

* N o t e 2

C S

R A S

C A S

W E

B A

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

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M12S16161A

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Publication Date : Jun. 2005

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Burst Read Single bit Write Cycle @Burst Length=2

*Note:1.BRSW modes is enabled by setting A9 "High" at MRS(Mode Register Set).

At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length.

2.When BRSW write command with auto precharge is executed, keep it in mind that t

RAS

should not be violated.

Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge

command will be issued after two clock cycles.

C L O C K

C K E

A D D R

C L = 2

D Q M

A 1 0 / A P

B A

R A a

R A c

R A a

Q A b 0

R o w A c t i v e
( A - B a n k )

W r i t e
( A - B a n k )

: D o n ' t C a r e

H I G H

Q A b 1

P r e c h a r g e
( A - B a n k )

C A a

R B b

C A b

C B c

C A d

R A c

D B c 0

D Q

D A a 0

Q A b 0

D B c 0

Q A b 1

C L = 3

Row Active
(B-Bank)

R o w A c t i v e
( A - B a n k )

W r i t e w i t h
A u t o P r e c h a r g e
( B - B a n k )

R e a d
( A - B a n k )

D A a 0

Q A d 0 Q A d 1

* N o t e 1

C S

R A S

C A S

W E

R B b

* N o t e 2

Read with
Auto Precharge
(A-Bank)

ESMT

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2005

Revision : 1.0

24/28

Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4

*Note :1.Both banks should be in idle state prior to entering precharge power down mode.

2.CKE should be set high at least 1CLK+tss prior to Row active command.

3.Can not violate minimum refresh specification. (32ms)

C L O C K

C K E

A D D R

D Q

D Q M

A1 0 / A P

Active
Power-down
Exit

P r e c h a r g e

: D o n ' t c a r e

* N o t e 3

* N o t e 2

* N o t e 1

S S

R a

Q a0

Q a1

Q a2

S H Z

P r e c h a r g e
P o w e r - D o w n
E n t r y

Precharge
Power-Down
Exit

Row Active

Active
Power-down
Entry

Read

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

C a

B A

R A S

C A S

C S

W E

S S

ESMT

M12S16161A

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Publication Date : Jun. 2005

Revision : 1.0

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Self Refresh Entry & Exit Cycle

*Note: TO ENTER SELF REFRESH MODE

1. CS , RAS & CAS with CKE should be low at the same clock cycle.

2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.

3. The device remains in self refresh mode as long as CKE stays "Low".

cf.) Once the device enters self refresh mode, minimum t

RAS

is required before exit from self refresh.

TO EXIT SELF REFRESH MODE

4. System clock restart and be stable before returning CKE high.

5. CS Starts from high.

6. Minimum t

is required after CKE going high to complete self refresh exit.

7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst

refresh.

C L O C K

C K E

A D D R

D Q

D Q M

A 1 0 / A P

S e l f R e f r e s h E n t r y

A u t o R e f r e s h

: D o n ' t c a r e

S e l f R e f r e s h E x i t

H i - Z

W E

B A

C A S

R A S

C S

* N o t e 2

* N o t e 1

* N o t e 4

R C m i n

* N o t e 6

* N o t e 5

* N o t e 7

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

S S

*Note3

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M12S16161A

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Publication Date : Jun. 2005

Revision : 1.0

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Mode Register Set Cycle

Auto Refresh Cycle

*Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.

MODE REGISTER SET CYCLE

*Note: 1. CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register.

2.Minimum 2 clock cycles should be met before new RAS activation.

3.Please refer to Mode Register Set table.

C L O C K

C K E

A D D R

Key

: D o n ' t C a r e

H I G H

C S

R A S

C A S

H I G H

* N o t e 3

R a

* N o t e 1

D Q

H i - Z

D Q M

1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 1 0

H i - Z

* N o t e 2

R C

M R S

N e w C o m m a n d

A u t o R e f r e s h

N e w C o m m a n d

W E

ESMT

M12S16161A

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Publication Date : Jun. 2005

Revision : 1.0

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PACKAGE DIMENSIONS
50-LEAD TSOP(II) SDRAM(400mil)

Dimension in mm

Dimension in inch

Symbol

Min Nom Max Min Nom Max

- -

1.20

- -

0.047

0.051 0.127 0.203

0.002

0.005 0.008

0.95 1.00 1.05 0.037 0.039 0.041

0.30 - 0.45

0.012 - 0.018

0.30 0.35 0.40 0.012 0.014 0.016

0.12 - 0.21

0.005 - 0.008

C1 0.10

0.127

0.16 0.004 0.005 0.006

20.82 20.95 21.08 0.820 0.825 0.830

11.56 11.76 11.96 0.455 0.463 0.471

10.03 10.16 10.29 0.394 0.400 0.405

0.40 0.50 0.60 0.016 0.020 0.024

0.80 REF

0.031 REF

0.80 BSC

0.031 BSC

0 - 8 0 - 8

ESMT

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Publication Date : Jun. 2005

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Important Notice

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any means without the prior permission of ESMT.

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time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.

The information contained herein is presented only as a guide or examples
for the application of our products. No responsibility is assumed by ESMT for
any infringement of patents, copyrights, or other intellectual property rights of
third parties which may result from its use. No license, either express ,
implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of ESMT or others.

Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure,
should be provided by the customer when making application designs.

ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.

Электронный компонент: M12S16161A