P-Channel Logic Level Enhancement
Mode Field Effect Transistor
P06P03LDG
TO-252
Lead-Free
NIKO-SEM
1
AUG-17-2004
ABSOLUTE MAXIMUM RATINGS (T
C
= 25 C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
LIMITS
UNITS
Drain-Source Voltage
V
DS
-30
V
Gate-Source Voltage
V
GS
20
V
T
C
= 25 C
-12
Continuous Drain Current
T
C
= 70 C
I
D
-10
Pulsed Drain Current
1
I
DM
-30
A
T
C
= 25 C
48
Power Dissipation
T
C
= 70 C
P
D
20
W
Operating Junction & Storage Temperature Range
T
j
, T
stg
-55 to 150
C
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
SYMBOL
TYPICAL
MAXIMUM
UNITS
Junction-to-Case
R
J
c
3
C / W
Junction-to-Ambient R
JA
75
C / W
1
Pulse width limited by maximum junction temperature.
2
Duty cycle
1
%
ELECTRICAL CHARACTERISTICS (T
C
= 25 C, Unless Otherwise Noted)
LIMITS
PARAMETER SYMBOL
TEST
CONDITIONS
MIN TYP MAX
UNIT
STATIC
Drain-Source Breakdown Voltage
V
(BR)DSS
V
GS
= 0V, I
D
= -250
A
-30
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
= -250
A
-1 -1.5 -3.0
V
Gate-Body Leakage
I
GSS
V
DS
= 0V, V
GS
= 20V
250 nA
V
DS
= -24V, V
GS
= 0V
1
Zero Gate Voltage Drain Current
I
DSS
V
DS
= -20V, V
GS
= 0V, T
J
= 125 C
10
A
On-State Drain Current
1
I
D(ON)
V
DS
= -5V, V
GS
= -10V
-30
A
V
GS
= -4.5V, I
D
=- 10A
60
75
Drain-Source On-State
Resistance
1
R
DS(ON)
V
GS
= -10V, I
D
= -12A
37
45
m
Forward Transconductance
1
g
fs
V
DS
= -10V, I
D
= -12A
16
S
PRODUCT SUMMARY
V
(BR)DSS
R
DS(ON)
I
D
-30
45m
-12A
G
S
D
1. GATE
2. DRAIN
3. SOURCE
P-Channel Logic Level Enhancement
Mode Field Effect Transistor
P06P03LDG
TO-252
Lead-Free
NIKO-SEM
2
AUG-17-2004
DYNAMIC
Input Capacitance
C
iss
530
Output Capacitance
C
oss
135
Reverse Transfer Capacitance
C
rss
V
GS
= 0V, V
DS
= -15V, f = 1MHz
70
pF
Total Gate Charge
2
Q
g
10
14
Gate-Source Charge
2
Q
gs
2.2
Gate-Drain Charge
2
Q
gd
V
DS
= 0.5V
(BR)DSS
, V
GS
= -10V,
I
D
= -12A
2
nC
Turn-On Delay Time
2
t
d(on)
5.7
Rise Time
2
t
r
V
DS
= -15V, R
L
= 1
10
Turn-Off Delay Time
2
t
d(off)
I
D
-1A, V
GS
= -10V, R
GS
= 6
18
Fall Time
2
t
f
5
nS
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (T
C
= 25 C)
Continuous Current
I
S
-12
Pulsed Current
3
I
SM
-30
A
Forward Voltage
1
V
SD
I
F
= -1A, V
GS
= 0V
-1.2
V
Reverse Recovery Time
t
rr
I
F
= -5A, dl
F
/dt = 100A /
S
15.5 nS
Reverse Recovery Charge
Q
rr
7.9 nC
1
Pulse test : Pulse Width
300
sec, Duty Cycle
2
.
2
Independent of operating temperature.
3
Pulse width limited by maximum junction temperature.
REMARK: THE PRODUCT MARKED WITH "P06P03LDG", DATE CODE or LOT #
Orders for parts with Lead-Free plating can be placed using the PXXXXXXXG parts name
P-Channel Logic Level Enhancement
Mode Field Effect Transistor
P06P03LDG
TO-252
Lead-Free
NIKO-SEM
5
AUG-17-2004
TO-252 (DPAK) MECHANICAL DATA
mm
mm
Dimension
Min. Typ. Max.
Dimension
Min. Typ. Max.
A 9.35 10.4 H 0.89 2.03
B 2.2 2.4 I 6.35 6.80
C
0.45 0.6 J 5.2 5.5
D 0.89 1.5 K 0.6 1
E 0.45 0.69 L 0.5 0.9
F 0.03 0.23 M 3.96 4.57 5.18
G 5.2 6.2 N
G
A
H
J
I
B
C
M
L
K
D
E
F
13
2