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Электронный компонент: P4C1024-17J4C

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Document # SRAM124 REV A
Revised October 2005
P4C1024
HIGH SPEED 128K x 8
DUAL CHIP ENABLE
CMOS STATIC RAM
The P4C1024 device provides asynchronous opera-
tions with matching access and cycle times. Memory
locations are specified on address pins A
0
to A
16
.
Reading is accomplished by device selection (CE
1
low
and CE
2
high) and output enabling (OE) while write
enable (WE) remains HIGH. By presenting the ad-
dress under these conditions, the data in the ad-
dressed memory location is presented on the data
input/output pins. The input/output pins stay in the
HIGH Z state when either CE
1
or OE is HIGH or WE
or CE
2
is LOW.
The P4C1024 is a 1,048,576-bit high-speed CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V10% tolerance power
supply.
Access times of 15 nanoseconds permit greatly en-
hanced system operating speeds. CMOS is utilized to
reduce power consumption to a low level. The P4C1024
is a member of a family of PACE RAMTM products offer-
ing fast access times.
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
--32-Pin 300 mil DIP and SOJ
--32-Pin 400 mil SOJ
--32-Pin 600 mil Ceramic DIP
--32-Pin 400 mil Ceramic DIP
--32-Pin Solder Seal Flatpack
--32-Pin LCC (450 x 500 mil)
--32-Pin Ceramic SOJ
High Speed (Equal Access and Cycle Times)
-- 15/20/25/35 ns (Commercial)
-- 20/25/35/45 ns (Industrial)
-- 20/25/35/45/55/70/85/100/120 ns (Military)
Single 5 Volts 10% Power Supply
Easy Memory Expansion Using
CE
CE
CE
CE
CE
1,
CE
2
and OE
OE
OE
OE
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DESCRIPTION
FEATURES
DIP (P300, C10, C11),
SOJ (J300, J400, CJ1),
SOLDER SEAL
FLATPACK (FS-3) SIMILAR
LCC (L6)
P4C1024
Page 2 of 14
Document # SRAM124 REV A
MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
CC
Power Supply Pin with
0.5 to +7
V
Respect to GND
Terminal Voltage with
0.5 to
V
TERM
Respect to GND
V
CC
+0.5
V
(up to 7.0V)
T
A
Operating Temperature
55 to +125
C
Symbol
Parameter
Value
Unit
T
BIAS
Temperature Under
55 to +125
C
Bias
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
50
mA
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
I
SB
Standby Power Supply
Current (TTL Input Levels)
CE
1
V
IH
or Mil.
CE
2
V
IL
, Ind./Com'l.
V
CC
= Max,
f = Max., Outputs Open
___
___
35
30
___
___
___
___
25
20
25
n/a
2
n/a
mA
mA
___
___
CE
1
V
HC
or Mil.
CE
2
V
LC
, Ind./Com'l.
V
CC
= Max,
f = 0, Outputs Open
V
IN
V
LC
or V
IN
V
HC
Standby Power Supply
Current
(CMOS Input Levels)
I
SB1
Grade
(2)
Ambient
Temperature
GND
V
CC
0V
0V
5.0V 10%
5.0V 10%
0V
5.0V 10%
55C to +125C
Military
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
8
10
Unit
pF
pF
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25C, f = 1.0MHz
Symbol
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
Output Leakage Current
Test Conditions
V
CC
= Min., I
IN
= 18 mA
I
OL
= +8 mA, V
CC
= Min.
I
OH
= 4 mA, V
CC
= Min.
V
CC
= Max. Mil.
V
IN
= GND to V
CC
Ind./Com'l.
V
CC
= Max., CE = V
IH
, Mil.
V
OUT
= GND to V
CC
Ind./Com'l.
P4C1024
Min
2.2
0.5
(3)
V
CC
0.2
0.5
(3)
2.4
10
5
10
5
Max
V
CC
+0.5
0.8
V
CC
+0.5
0.2
1.2
0.4
+10
+5
+10
+5
P4C1024L
Min
Max
2.2
0.5
(3)
V
CC
0.2
0.5
(3)
2.4
5
n/a
5
n/a
V
CC
+0.5
0.8
V
CC
+0.5
0.2
0.4
1.2
+5
n/a
+5
n/a
Unit
V
V
V
V
V
V
V
A
A
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than 3.0V and
100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Typ.
Industrial
Commercial
40C to +85C
0C to +70C
P4C1024
Page 3 of 14
Document # SRAM124 REV A
DATA RETENTION CHARACTERISTICS (P4C1024L, Military Temperature Only)
Typ.*
Max
Symbol
Parameter
Test Condition
Min
V
CC
=
V
CC
=
Unit
2.0V
3.0V
2.0V
3.0V
V
DR
V
CC
for Data Retention
2.0
V
I
CCDR
Data Retention Current
50
200
400
600
A
t
CDR
Chip Deselect to
ns
Data Retention Time
t
R
Operation Recovery Time
t
RC
ns
*
T
A
= +25C
t
RC
= Read Cycle Time
This parameter is guaranteed but not tested.
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE
1
= V
IL
, CE
2
= V
IH
, OE = V
IH
POWER DISSIPATION CHARACTERISTICS VS. SPEED
DATA RETENTION WAVEFORM
CE
1
V
CC
0.2V or
CE
2
0.2V, V
IN
V
CC
0.2V
or V
IN
0.2V
Symbol
Parameter
Temperature
Range
-15
-20
-25
-35
-45
-55
-70
-85 -100 -120
Unit
Commercial
190 160 150 145 N/A N/A N/A N/A N/A N/A
mA
Industrial
N/A 175 165 160 155 N/A N/A N/A N/A N/A
mA
Military
N/A 150 140 135 130 125 115 110 105 100
mA
Dynamic Operating Current*
I
CC
P4C1024
Page 4 of 14
Document # SRAM124 REV A
AC ELECTRICAL CHARACTERISTICS--READ CYCLE
(V
CC
= 5V 10%, All Temperature Ranges)
(2)
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
t
RC
Read Cycle
Time
15
20
25
35
45
55
70
85
100
120
ns
t
AA
Address
Access Time
15
20
25
35
45
55
70
85
100
120 ns
t
AC
Chip Enable
Access Time
15
20
25
35
45
55
70
85
100
120 ns
t
OH
Output Hold
from Address
Change
3
3
3
3
3
3
3
3
3
3
ns
t
LZ
Chip Enable to
Output in Low Z
3
3
3
3
3
3
3
3
3
3
ns
t
HZ
Chip Disable
to Output in
High Z
8
9
11
15
20
25
30
35
40
50
ns
t
OE
Output Enable
Low to Data
Valid
7
9
11
15
20
25
30
35
40
50
ns
t
OLZ
Output Enable
Low to Low Z
0
0
0
0
0
0
0
0
0
0
ns
t
OHZ
Output Enable
High to High Z
7
9
11
15
20
25
30
35
40
50
ns
t
PU
Chip Enable to
Power Up
Time
0
0
0
0
0
0
0
0
0
0
ns
t
PD
Chip Disable
to Power Down
Time
12
20
20
20
25
30
35
40
45
50
ns
Symbol
Parameter
-15
-20
-25
-35
-45
Unit
-55
-70
-85
-100
-120
Notes:
5. WE is HIGH for READ cycle.
6. CE
1
is LOW, CE
2
is HIGH and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE
1
transition
LOW and CE
2
transition HIGH.
8. Transition is measured 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE
OE
OE
OE
OE CONTROLLED)
(5)
P4C1024
Page 5 of 14
Document # SRAM124 REV A
TIMINIG WAVERFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE
CE
CE
CE
CE
1
, CE
2
CONTROLLED)
(5,7,10)
Notes:
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays
irrespective of whether CE
1
or CE
2
causes them.