EtronTech
EM638165
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
4Mega x 16 Synchronous DRAM (SDRAM)
Preliminary (Rev 0.6, 2/2001)
Features
Fast access time from clock: 5/6/6/6/7 ns
Fast clock rate: 166/143/133/125/100 MHz
Fully synchronous operation
Internal pipelined architecture
1M word x 16-bit x 4-bank
Programmable Mode registers
- CAS# Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V
0.3V power supply
Interface: LVTTL
54-pin 400 mil plastic TSOP II package
Overview
The EM638165 SDRAM is a high-speed CMOS
synchronous DRAM containing 64 Mbits. It is internally
configured as 4 Banks of 1M word x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Read and write
accesses to the SDRAM are burst oriented; accesses
start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of a
BankActivate command which is then followed by a
Read or Write command.
The EM638165 provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy
to use.
By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth and particularly well suited to high
performance PC applications.
Pin Assignment (Top View)
Key Specifications
EM638165
-
6/7/7.5/8/10
t
CK3
Clock Cycle time(min.)
6/7/7.5/8/10 ns
t
AC3
Access time from CLK(max.)
5/5.4/5.4/6/7 ns
t
RAS
Row Active time(max.)
42/45/45/48/50 ns
t
RC
Row Cycle time(min.)
60/63/68/70/80 ns
Ordering Information
Part Number
Frequency
Package
EM638165TS-6
166MHz
TSOP II
EM638165TS-7
143MHz
TSOP II
EM638165TS-7.5
133MHz
TSOP II
EM638165TS-8
125MHz
TSOP II
EM638165TS-10
100MHz
TSOP II
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE#
CAS#
RAS#
CS#
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC/RFU
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
EtronTech
EM638165
Preliminary
3
Rev 0.6 Feb. 2001
Pin Descriptions
Table 1. Pin Details of EM638165
Symbol
Type
Description
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counter and controls the output registers.
CKE
Input
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If
CKE goes low synchronously with clock(set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state
of output and burst address is frozen as long as the CKE remains low. When all
banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes. CKE is synchronous except after the device
enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK,
are disabled during Power Down and Self Refresh modes, providing low
standby power.
Bank Select: BA0,BA1 input select the bank for operation.
BA1
BA0
Select Bank
0
0
BANK #A
0
1
BANK #B
1
0
BANK #C
BA0,BA1
Input
1
1
BANK #D
A0-A11
Input
Address Inputs: A0-A11 are sampled during the BankActivate command (row
address A0-A11) and Read/Write command (column address A0-A7 with A10
defining Auto Precharge) to select one location out of the 2M available in the
respective bank. During a Precharge command, A10 is sampled to determine if
all banks are to be precharged (A10 = HIGH). The address inputs also provide
the op-code during a Mode Register Set command.
CS#
Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH.
CS# provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
RAS#
Input
Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted
"HIGH," either the BankActivate command or the Precharge command is
selected by the WE# signal. When the WE# is asserted "HIGH," the
BankActivate command is selected and the bank designated by BS is turned on
to the active state. When the WE# is asserted "LOW," the Precharge command
is selected and the bank designated by BS is switched to the idle state after the
precharge operation.
CAS#
Input
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column
access is started by asserting CAS# "LOW." Then, the Read or Write command
is selected by asserting WE# "LOW" or "HIGH."
EtronTech
EM638165
Preliminary
4
Rev 0.6 Feb. 2001
WE#
Input
Write Enable: The WE# signal defines the operation commands in conjunction
with the RAS# and CAS# signals and is latched at the positive edges of CLK.
The WE# input is used to select the BankActivate or Precharge command and
Read or Write command.
LDQM,
UDQM
Input
Data Input/Output Mask: Controls output buffers in read mode and masks
Input data in write mode.
DQ0-DQ15
Input /
Output
Data I/O: The DQ0-15 input and output data are synchronized with the positive
edges of CLK. The I/Os are maskable during Reads and Writes.
NC/RFU
-
No Connect: These pins should be left unconnected.
V
DDQ
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
( 3.3V
0.3V )
V
SSQ
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
( 0 V )
V
DD
Supply Power Supply: +3.3V
0.3V
V
SS
Supply Ground
EtronTech
EM638165
Preliminary
5
Rev 0.6 Feb. 2001
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
State CKE
n-1
CKE
n
DQM
BA
0,1
A
10
A
0-9,11
CS#
RAS#
CAS# WE#
BankActivate
Idle
(3)
H
X
X
V Row address L
L
H
H
BankPrecharge
Any
H
X
X
V
L
X
L
L
H
L
PrechargeAll
Any
H
X
X
X
H
X
L
L
H
L
Write
Active
(3)
H
X
X
V
L
L
H
L
L
Write and AutoPrecharge
Active
(3)
H
X
X
V
H
Column
address
(A0 ~ A7)
L
H
L
L
Read
Active
(3)
H
X
X
V
L
L
H
L
H
Read and Autoprecharge
Active
(3)
H
X
X
V
H
Column
address
(A0 ~ A7)
L
H
L
H
Mode Register Set
Idle
H
X
X
OP code
L
L
L
L
No-Operation
Any
H
X
X
X
X
X
L
H
H
H
Burst Stop
Active
(4)
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
AutoRefresh
Idle
H
H
X
X
X
X
L
L
L
H
SelfRefresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
SelfRefresh Exit
Idle
L
H
X
X
X
X
H
X
X
X
(SelfRefresh)
L
H
H
H
Clock Suspend Mode Entry
Active
H
L
X
X
X
X
X
X
X
X
Power Down Mode Entry
Any
(5)
H
L
X
X
X
X
H
X
X
X
L
H
H
H
Clock Suspend Mode Exit
Active
L
H
X
X
X
X
X
X
X
X
Power Down Mode Exit
Any
L
H
X
X
X
X
H
X
X
X
(PowerDown)
L
H
H
H
Data Write/Output Enable
Active
H
X
L
X
X
X
X
X
X
X
Data Mask/Output Disable
Active
H
X
H
X
X
X
X
X
X
X
Note: 1. V=Valid X=Don't Care L=Low level H=High level
2. CKE
n
signal is input level when commands are provided.
CKE
n-1
signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
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