EtronTech
EM638325
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
2M x 32 Synchronous DRAM (SDRAM)
Preliminary (Rev 0.8 Nov/2001)
Features
Clock rate: 285/250/200/183/166
/143/125 MHz
Fully synchronous operation
Internal pipelined architecture
Four internal banks (512K x 32bit x 4bank)
Programmable Mode
- CAS# Latency: 2 or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
-
Burst-Read-Single-Write
Burst stop function
Individual byte controlled by DQM0-3
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
Single +3.3V 0.3V power supply
Interface: LVTTL
Package: 400 x 875 mil, 86 Pin TSOP II,
0.50mm pin pitch
Package: 10 x 11 mm,90 ball BGA,0.65mm
ball pitch
Pin Assignment (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
/WE
/CAS
/RAS
/CS
NC
BS0
BS1
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
8 6
8 5
8 4
8 3
8 2
8 1
8 0
7 9
7 8
7 7
7 6
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
Ordering Information
Part Number
Frequency
Package
EM638325TS-3.5 285MHz
TSOP
II
EM638325TS-4 250MHz TSOP
II
EM638325TS-5 200MHz TSOP
II
EM638325TS-5.5 183MHz
TSOP
II
EM638325TS-6 166MHz TSOP
II
EM638325TS-7 143MHz TSOP
II
EM638325TS-8 125MHz TSOP
II
Part Number
Frequency
Package
EM638325VF-3.5 285MHz 10x11
BGA
EM638325VF-4 250MHz 10x11 BGA
EM638325VF-5 200MHz 10x11 BGA
EM638325VF-5.5 183MHz 10x11 BGA
EM638325VF-6 166MHz 10x11 BGA
EM638325VF-7 143MHz 10x11 BGA
EM638325VF-8 125MHz 10x11 BGA
A
V S S
DQ 1 5
V S S Q
V D D Q
DQ 0
V D D
B
DQ 1 4
DQ 1 3
V D D Q
V S S Q
DQ 2
DQ 1
C
DQ 1 2
DQ 1 1
V S S Q
V D D Q
DQ 4
DQ 3
D
DQ 1 0
DQ 9
V D D Q
V S S Q
DQ 6
DQ 5
E
DQ 8
N C
V S S
V D D
N C
DQ 7
F
D Q M 1
N C
N C
CA S
W E
D Q M 0
G
N C
CK E
C L K
N C
C S
RA S
H
N C
A 9
A 8
B S 0
N C
N C
J
A 5
A 6
A 7
B S 1
A 1 0
A 0
K
D Q M 3
A 3
A 4
A 1
A 2
D Q M 2
L
DQ 3 1
N C
V S S
V D D
N C
DQ 1 6
M
DQ 2 9
DQ 3 0
V D D Q
V S S Q
DQ 1 7
DQ 1 8
N
DQ 2 7
DQ 2 8
V S S Q
V D D Q
DQ 1 9
DQ 2 0
P
DQ 2 5
DQ 2 6
V D D Q
V S S Q
DQ 2 1
DQ 2 2
R
V S S
DQ 2 4
V S S Q
V D D Q
DQ 2 3
V D D
1
2
3
4
5
6
7
8
9
1 0
EtronTech
2Mega x 32 SDRAM
EM638325
Preliminary
2
Rev 0.8
Nov 2001
Overview
The EM638325 SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured
as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock
signal, CLK). Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits. Read and write
accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number
of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then
followed by a Read or Write command.
The EM638325 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at
the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use.
By having a programmable mode register, the system can choose the most suitable modes to maximize its
performance. These devices are well suited for applications requiring high memory bandwidth.
Block Diagram
R E F R E S H
C O U N T E R
CO LU MN
C O U N T E R
A D D R E S S
B U F F E R
A 0
A 9
B S 0
B S 1
C O N T R O L
S IG N A L
G E N E R A T O R
D Q M 0 ~ 3
DLL
C L O C K
B U F F E R
COMMAND
D E C O D E R
Colum n De coder
Sense Ampl ifier
Row Decoder
2048 X 256 X 32
CELL ARRAY
(BANK #0)
Sense Ampl ifier
Colum n De coder
Row Decoder
2048 X 256 X 32
CELL ARRAY
(BANK #3)
M O D E
R E G IS T E R
CL K
C K E
C S #
R A S #
C A S #
W E #
A 1 0 /A P
D Q 0
D
D Q 3 1
Sense Ampl ifier
Colum n De coder
Row Decoder
2048 X 256 X 32
CELL ARRAY
(BANK #1)
Sense Ampl ifier
Colum n De coder
Row Decoder
2048 X 256 X 32
CELL ARRAY
(BANK #2)
D Q
B U F F E R
EtronTech
2Mega x 32 SDRAM
EM638325
Preliminary
3
Rev 0.8
Nov 2001
Pin Descriptions
Table 1. Pin Details of EM638325
Symbol Type Description
CLK Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the
positive edge of CLK. CLK also increments the internal burst counter and controls the
output registers.
CKE Input
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes
low synchronously with clock(set-up and hold time same as other inputs), the internal clock
is suspended from the next clock cycle and the state of output and burst address is frozen
as long as the CKE remains low. When all banks are in the idle state, deactivating the clock
controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except
after the device enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK, are disabled
during Power Down and Self Refresh modes, providing low standby power.
BS0,
BS1
Input Bank Select: BS0 and BS1 defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied. BS is also used to program the 11th bit of the
Mode and Special Mode registers.
A0-A10 Input Address Inputs: A0-A10 are sampled during the BankActivate command (row address A0-
A10) and Read/Write command (column address A0-A7 with A10 defining Auto Precharge)
to select one location out of the 256K available in the respective bank. During a Precharge
command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH).
The address inputs also provide the op-code during a Mode Register Set or Special Mode
Register Set command.
CS# Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external
bank selection on systems with multiple banks. It is considered part of the command code.
RAS# Input
Row Address Strobe: The RAS# signal defines the operation commands in conjunction
with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS#
and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate
command or the Precharge command is selected by the WE# signal. When the WE# is
asserted "HIGH," the BankActivate command is selected and the bank designated by BS is
turned on to the active state. When the WE# is asserted "LOW," the Precharge command is
selected and the bank designated by BS is switched to the idle state after the precharge
operation.
CAS#
Input Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of CLK.
When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is started by
asserting CAS# "LOW." Then, the Read or Write command is selected by asserting WE#
"LOW" or "HIGH."
WE# Input
Write Enable: The WE# signal defines the operation commands in conjunction with the
RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is
used to select the BankActivate or Precharge command and Read or Write command.
DQM0 -
DQM3
Input Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer controls.
The I/O buffers are placed in a high-z state when DQM is sampled HIGH. Input data is
masked when DQM is sampled HIGH during a write cycle. Output data is masked (two-
clock latency) when DQM is sampled HIGH during a read cycle. DQM3 masks DQ31-
DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7-DQ0.
DQ0-
DQ31
Input/
Output
Data I/O: The DQ0-31 input and output data are synchronized with the positive edges of
CLK. The I/Os are byte-maskable during Reads and Writes.
EtronTech
2Mega x 32 SDRAM
EM638325
Preliminary
4
Rev 0.8
Nov 2001
NC -
No Connect: These pins should be left unconnected.
V
DDQ
Supply
DQ Power: Provide isolated power to DQs for improved noise immunity.
V
SSQ
Supply
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
V
DD
Supply
Power Supply: +3.3V
0.3V
V
SS
Supply
Ground
EtronTech
2Mega x 32 SDRAM
EM638325
Preliminary
5
Rev 0.8
Nov 2001
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command State
CKE
n-1
CKE
n
DQM
(6)
BS
0,1
A
10
A
9-0
CS#
RAS#
CAS#
WE#
BankActivate
Idle
(3)
H X X V
Row
address
L
L
H
H
BankPrecharge
Any H X X V
L X L
L
H
L
PrechargeAll
Any H X X X H X L L H L
Write
Active
(3)
H X X V L
L H L L
Write and AutoPrecharge
Active
(3)
H X X V H
Column
address
(A0 ~ A7)
L H L L
Read
Active
(3)
H X X V L
L H L H
Read and Autoprecharge
Active
(3)
H X X V H
Column
address
(A0 ~ A7)
L H L H
Mode Register Set
Idle H X X
OP
code
L L L L
No-Operation
Any H X X X
X X L
H
H
H
Burst Stop
Active
(4)
H X X X
X X L
H
H
L
Device Deselect
Any
H X X X X X H X X X
AutoRefresh
Idle H H X X
X X L
L
L
H
SelfRefresh Entry
Idle H L X X
X X L
L
L
H
SelfRefresh Exit
Idle
L H X X X X H X X X
(SelfRefresh)
L
H
H
H
Clock Suspend Mode Entry
Active H L X X
X X X
X
X
X
Power Down Mode Entry
Any
(5)
H L X X X X H X X X
L
H
H
H
Clock Suspend Mode Exit
Active L H X X
X X X
X
X
X
Power Down Mode Exit
Any
L H X X X X H X X X
(PowerDown)
L
H
H
H
Data Write/Output Enable
Active H X L X X X X X X X
Data Mask/Output Disable
Active H X H X X X X X X X
Note: 1. V = Valid, X = Don't care, L = Logic low, H = Logic high
2. CKE
n
signal is input level when commands are provided.
CKE
n-1
signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. DQM0-3
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