MP3276

Rev. 4.00

Fault Protected 16 Channel, 12-Bit

Data Acquisition Subsystem

FEATURES

Fault Protected 16-Channel 12-Bit A/D
Converter with Sample & Hold, Reference,
Clock and 3-state Outputs

Fast Conversion, less than 15

Microprocessor Bus Interface

2's Complement Data Output

Parallel or Serial Data Output Modes

65 ns Bus Access Time

Remote Analog Ground Sensing

Overvoltage Protected Input (

50 V over the Sup-

ply Voltages)

Precision Reference for Long Term Stability and
Low Gain T.C.

Guaranteed Linearity Over Temperature

Guaranteed Performance at +12/5 V,

12 &

15 V

Low Power: 110 mW typ. (7 mW per Channel typ.)

32 Channel Version: MP3274

GENERAL DESCRIPTION

The MP3276 is a complete 16-channel, 12-bit Data Acquisi-

tion Subsystem with 3-state output buffers for direct interfacing
to 16-bit microprocessor buses. Implemented using an ad-
vanced BiCMOS process, the converter combines a 16-channel
passive overvoltage protected multiplexer instrumentation amp,
a sample & hold, a SAR, a 12-bit decoded D/A, a comparator, a
precision reference and the control logic to achieve an accurate
repeated conversion in less than 15

s, and a mux/instrumenta-

tion amp settling period of less than 10

A unique input design provides input overvoltage protection

50 V over the supply voltages. The circuit design can allow

for an overvoltage condition on unselected channels without dis-
rupting the measured channel or operation of the MP3276! The
internal 4 V reference has sufficient output current to provide
other system reference needs. Precision thin film scaling and
offset resistors are laser trimmed to provide for less than 2 LSB
INL for +10 V inputs on all channels.

In addition, the MP3276 will output either full scale (0111 ....)

for overrange and full scale (1000....) for underrange condi-
tions. This greatly simplifies microprocessor software develop-
ment.

SIMPLIFIED BLOCK DIAGRAM

Comp

SAR

4 V

REF

16 Ch.

MUX

AB0-3

(4 pins)

AIN0-15

(16 pins)

REF OUT

Control

Logic

GND REF.

DGND V

VDAC

Latch/

Shift Register

3-state

Drivers

DB0-DB11

REF IN /2

CLK

WR RD

PXS

ADEN

STL

STS

AGND

REF

AGND

GND

REF IN

MP3276

Rev. 4.00

PIN OUT DEFINITIONS

Negative Analog Supply

Analog Input 12, AB3-AB0 = 1100

N/C or GND

Analog Input 13, AB3-AB0 = 1101

N/C or GND

Analog Input 14, AB3-AB0 = 1110

N/C or GND

Analog Input 15, AB3-AB0 = 1111

N/C or GND

GND Ref.

Input Ground Reference

AGND

ADC Analog Ground

Ref In

Reference Input

Ref Out

Reference Output

AGND3

Reference Analog Ground

DGND

Digital Ground

DB0/SDC

Data Output Bit 0/Serial Data
Clock

N/C

No Connection

DB1

Data Output Bit 1

DB2

Data Output Bit 2

DB3

Data Output Bit 3

DB4

Data Output Bit 4

DB5

Data Output Bit 5

DB6

Data Output Bit 6

DB7

Data Output Bit 7

DB8

Data Output Bit 8

DB9

Data Output Bit 9

DB10

Data Output Bit 10

DB11/SDO

Data Output Bit 11/Serial
Data Out

STS

Conversion Status

STL

Mux Settling Status

PXS

Parallel/XSerial

Read Enable

Chip Select

Write Enable

PLCC
PIN NO.

NAME

DESCRIPTION

ADEN

Address Enable

AB3

Channel Address 3

AB2

Channel Address 2

AB1

Channel Address 1

AB0

Channel Address 0

GND

Positive Digital Supply

Positive Analog Supply

Analog Input 0, AB3-AB0 = 0000

N/C or GND

Analog Input 1, AB3-AB0 = 0001

N/C or GND

Analog Input 2, AB3-AB0 = 0010

N/C or GND

Analog Input 3, AB3-AB0 = 0011

N/C or GND

N/C

No Connection

Analog Input 4, AB3-AB0 = 0100

N/C or GND

Analog Input 5, AB3-AB0 = 0101

N/C or GND

Analog Input 6, AB3-AB0 = 0110

N/C or GND

Analog Input 7, AB3-AB0 = 0111

N/C or GND

AGND2

Analog Ground Mux Return

Analog Input 8, AB3-AB0 = 1000

N/C or GND

Analog Input 9, AB3-AB0 = 1001

N/C or GND

Analog Input 10, AB3-AB0 = 1010

N/C or GND

Analog Input 11, AB3-AB0 = 1011

N/C or GND

PGA
PADS

PLCC
PIN NO.

NAME

DESCRIPTION

PGA
PADS

MP3276

Rev. 4.00

ELECTRICAL CHARACTERISTICS TABLE

Unless Otherwise Specified: V

= 5 V, V

= 15 V, V

= 15 V, GNDRef = 0 V, T

= 25

REF

IN = ReOut

Parameter

Symbol

Min

Typ

Max

Min

Max

Units

Test Conditions/Comments

Resolution (All Grades)

Bits

KEY FEATURES

Resolution

Bits

Conversion Time, Per Channel

CONVR

ACCURACY (A Grade)

Refer to

Table 6. for

output coding

Differential Non-Linearity

DNL

3/4

LSB

Integral Non-Linearity

INL

LSB

Best Fit Line
(Max INL Min INL)/2

Zero Code Error

EZS

LSB

fff to 000 [hex] transition

Full Scale Error

EFS

0.1

0.35

0.5

REF

IN = 4.000 V

POWER SUPPLY REJECTION

Max change in Full Scale
Calibration

= 15 V

1.5 V or 12 V

0.6 V

LSB

= 5 V

0.25 V

2.5

LSB

= 15 V

1.5 V or

12 V

0.6 V or

LSB

5 V

0.25 V

REFERENCE VOLTAGES

Ref. Voltage Input

Ref In

3.6

4.4

]

5 K

, V

= 5 V

Ref. Voltage Output

Ref Out

3.975

4.025

Ref. Source Current

3.0

4.0

3.0

Ref. Sink Current

ANALOG INPUT

Input Voltage Range

Ground Reference

GND Ref.

CM Range

CM RR

TBD

LSB/V

Input Resistance

100

130

100

Input Capacitance

Aperture Delay

180

From WR low to high after STL
high to low

Channel-to-Channel Isolation

DIGITAL INPUTS
CS, WR, RD AB0-AB4,
ADEN, SDC

Logical "1" Voltage

2.4

5.5

2.4

5.5

Logical "0" Voltage

0.5

0.8

0.5

0.8

Leakage Currents

=GND to V

Input Capacitance

Tmin to Tmax

MP3276

Rev. 4.00

ELECTRICAL CHARACTERISTICS TABLE (CONT'D)

Description

Symbol

Min

Typ

Max

Min

Max

Units

Conditions

DIGITAL OUTPUTS

OUT

=15 pF

(Data Format 2's Complement)
DB0/SDCDB11/SDO, STL, STS

Logical "1" Voltage

4.0

2.4

SOURCE

= 0.5 mA

Logical "0" Voltage

0.4

SINK

= 1.6 mA

Tristate Leakage

OUT

=GND to V

POWER SUPPLIES

Operating Range

+4.5

+5.5

+4.5

+5.5

+11.4

+16.5

+11.4

+16.5

4.75

16.5

4.75

16.5

Tested at 11.4 and 16.5 only

Operating Current

1.5

Power Dissipation

110

200

Tmin to Tmax

NOTES

Tester measures code transitions by dithering the voltage of the analog input (V

). The difference between the measured and the

ideal code width is the DNL error. The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage

Guaranteed. Not tested.

All channel input pins and ground reference pin have protection which becomes active above

60 V.

All digital inputs have diodes to V

and AGND. Input DC currents will not exceed specified limits for any input voltage between GND

and V

Refin should not vary from Refout by more than

10% of the nominal value of Refout.

Specifications are subject to change without notice

ABSOLUTE MAXIMUM RATINGS (T

= +25

C unless otherwise noted)

1, 2

to DGND

0 to +16.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

to DGND

0 to 16.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

to DGND

0 to +7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AGND to DGND

1 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital Inputs/Outputs
to DGND

0.5 V to V

LOGIC

+0.5 V

. . . . . . . . . . . . . . . . . . . . .

Analog Inputs (A

0 A

31, GND REF)

to AGND

60 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REF OUT

Indefinite short to DGND,

. . . . . . . . . . . . . . . . . . .

Momentary short to V

Maximum Junction Temperature

150

. . . . . . . . . . . . . . . . .

Package Power Dissipation Rating to 75

PGA, PLCC

1800 mW

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Derates above 75

25 mW/

. . . . . . . . . . . . . . . . . . . . .

Lead Temperature, Soldering

300

C, 10 Sec

. . . . . . . . . . . .

Storage Temperature (Ceramic)

C to +150

. . . . . . . .

NOTES:

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

Any input pin which can see a value outside the absolute maximum ratings

should be protected by Schottky diode clamps

(HP5082-2835) from input pin to the supplies.

All logic inputs have protection diodes which will protect the device from

short transients outside the supplies of less than 100mA for less than 100

MP3276

Rev. 4.00

PRODUCT INFORMATION

Basic Description

The MP3276 is a fault protected data acquisition subsystem

available in monolithic form. This product contains all of the cir-
cuitry necessary to acquire 16 channels of quasi differential or
single-ended analog signals at

10 V input range and 15kHz

bandwidth. Connections to power, the analog input signals and
the digital system are all that is required. The MP3276's input
circuitry is protected against active input signals present with the
MP3276 power off. This is also the case for any channel exceed-

ing the MP3276 analog input dynamic range without interfering
with the channel being digitized. The channel address and
channel conversion can be managed in two ways: random
channel conversion or same channel conversion. Circuitry on
the chip adds a MUX/instrumentation amp settling (STL) delay
of 10

s max, when a new channel is selected (ADEN = 1). Con-

version start is initiated without delay for the single-channel case
(ADEN = 0). Data is available in either parallel or serial format.

TIMING

Control and Timing Considerations Parallel Mode (PXS = 1)

The MP3276 can be operated in the stand-alone mode, with

one line for control and everything else hard-wired; or under mi-
croprocessor control, where changes can be made dynamically.
There are 4 control lines: ADEN, CS, WR, and RD with their
functions described in

Table 1.

PXS is the control pin for formatting data for serial or parallel

control.

Note 1: If RD = 1, data outputs remain high impedance. It is recommended that RD will not change during a conver-
sion in order to reduce noise. It is further recommended that RD = 1 during conversion to reject any noise present on
the data bus.

Table 1. Logic Truth Table for PXS = 1 (Parallel Mode)

ADEN

Data

STL

STS

Comments

No operation

Hi-Z

No operation if ADEN = 0

Hi-Z

Input MUX channel selected, STL set on WR falling edge

Hi-Z

MUX select disabled

Hi-Z

Start convert on WR rising edge

Hi-Z

Start convert on STL falling edge

Hi-Z

STS goes low at end of conversion

Data outputs enabled

ADC

Data from previous conversion on data bus

Hi-Z

Data outputs disabled

Hi-Z

Data/RD disabled while STS high

Last ADC

Data from last conversion on data bus

Hi-Z

STL, MUX select disabled with ADEN = 0,
data outputs disabled on STS rising edge

ADC

New data appears on data bus on falling edge of STS

Read ADC Data Parallel Output Mode (PXS = 1)

(See Figure 2. and Table 3.)

ADC Channel Select and Start Convert

(See Figure 1. and Table 2.)

MP3276

Rev. 4.00

The MP3276 is easily interfaced to a wide variety of micropro-

cessors and other digital systems. Discussion of the timing re-
quirements of the MP3276 control signals follows.

Figure 1. shows a complete timing diagram for the MP3276

convert start operation.

Either WR or CS may be used to initiate a conversion. We

recommend using WR as used in

Figure 1. It is quieter and has

less propagation delay than CS. If CS is used to trigger the con-
version the specified set-up times will be longer.

A conversion is started by taking WR low, then high again

(conversion is enabled on the rising edge of WR). There are two
possible conditions that will affect conversion timing.

1. ADEN = 1. At the falling edge of WR, the input channel is

determined by the data present on the address bits. The
track and hold begins to settle after which STL returns low,
indicating that the multiplexer and the buffer amp have set-
tled to less than 1/2 LSB of final value. If the rising edge of
WR returns high prior to STL going low, conversion will begin
on the falling edge of STL. If the rising edge of WR is delayed
until after STL returns low, the input signal is sampled and
the conversion is started at the rising edge of WR giving the
user better control of the sampling time.

2. ADEN = 0. At the falling edge of WR the data present at the

address is ignored and the channel selected during the pre-
vious conversion remains selected. In this case the track
and hold settling time is omitted and STL never goes high. At
the rising edge of WR the input signal is sampled, and con-
version is started.

There are two possible states that the data outputs could be in

during a conversion.

1. If RD is held high during a conversion the outputs would re-

main high impedance throughout the conversion. This is the
preferred method of operation as any noise present on the
data bus is rejected.

2. If RD and CS are held low during a conversion, the data pre-

sent will be from the previous conversion until the present
conversion is completed when STS returns low. The data
from the new conversion will appear on the outputs. The
state of RD or CS should not change during a conversion.

Once a conversion is started and the STL or STS line goes

high, convert start commands will be ignored until the conver-
sion cycle is completed. The output data buffers cannot be en-
abled during conversion. In addition, all inputs and outputs
which change during conversion can introduce noise, and
should be avoided when possible.

ADC Control Timing

Table 2. ADC Write Timing

(See Figure 1.)

Tmin to

Tmax

Limits

Comments/Test Conditions

CS to WR Set-Up Time

ns min

CS to WR Hold Time

ns min

Address to WR Set-Up Time

ns min

Address to WR Hold Time

ns min

WR Pulse Width

ns min

ADEN to WR Set-Up Time

ns min

ADC Conversion Timing

WR to STL Delay

150

ns max

Load ckt of Figure 5, C

= 20 pF,

ADEN = 1

STL High (mux/amp settle)

s max

Load ckt of Figure 5, C

= 20 pF

STL to STS Low (Converting)

s max

Load ckt of Figure 5, C

= 20 pF

WR to STS High (ADEN = 0)

200

250

ns max

STL = 0 when ADEN = 0

WR to STS Low (ADEN = 1)

s max

STS High to Bus Relinquish Time

150

ns max

Load ckt of Figure 4

STS Low to Data Valid (RD = 0)

ns max

Load ckt of Figure 3, C

= 20 pF

ADC Write Timing

Time

Interval

MP3276

Rev. 4.00

ADDRESS

Figure 1. Timing for ADC Channel Select Start Conversion

STL

ADEN

STS

DB0-DB11

RD = 0

DB0-DB11

RD = 1

HIGH Z

Previous ADC Data

New ADC Data

Table 3. ADC Read Timing

(

See Figure 2.)

Tmin to

Tmax

Limits

Comments/Test Conditions

CS to RD Set-Up Time

ns min

CS to RD Hold Time

ns min

RD to Data Valid Delay

100

150

ns max

Load ckt of

Figure 3., C

= 20 pF

150

200

ns max

Load ckt of

Figure 3., C

= 100 pF

Bus Relinquish Time after RD

100

150

ns max

Load ckt of

Figure 4.

High
RD Pulse Width

100

150

ns min

Load ckt 4

ADC Read Timing

Time

Interval

DATA

Figure 2. Timing for ADC Read

Valid

MP3276

Rev. 4.00

Figure 3. Load Circuit for Data

Access Time Test

a. High-Z to V

b. High-Z to V

+5 V

Figure 4. Load Circuit for
Bus Relinquish Time Test

10pF

a. V

to High-Z

10pF

b. V

to High-Z

+5 V

Figure 5. Load Circuit for WR to STS Delay

DGND

STL, STS

Serial Data Output Mode (PXS = 0)

The MP3276 output data is available in serial form when PXS

= 0 prior to the RD high-to-low transition. When PXS = 0, the
DB11/SDO pin functions as the serial data output. The
DB0/SDC pin functions as the serial clock input and all other
data outputs are 3-stated.

The serial data output sequence is MSB (DB11) first to LSB

(DB0) last. The MSB (DB11) data bit appears at DB11/SDO
when STS goes low. The second most significant bit appears at
DB11/SDO on the next DB0/SDC high-to-low transition. The
LSB (DB0) is present at DB11/SDO on the 11th SDC high-to-low
transition.

The control pin functions (ADEN, CS, WR, and RD) are the

same as the parallel mode of operation. Further information re-
garding serial control and timing is shown in

Figure 6., Table 4.

and

Table 5.

For a minimum interconnect serial environment, the channel

address state can be generated in at least two ways, using an
address counter, or using an address serial to parallel converter.
WR can then be used as the counter clock or shift register load
signal as well as the A/D converter start convert signal on the ris-
ing edge. (Note that the falling edge loads the address present at
the address port.)

SDC

DB11/SDO

Figure 6. Serial Data Mode Timing

DB11 (MSB)

DB10

SDC should be in a high state during the STS high period. SDC can make the first high to low transition after t

. In normal use it is

assumed that PXS is hardwired low. However, if the mode of operation is changed, PXS must go low prior to RD going low.

STS

See Table 4

ÇÇÇÇÇ

MP3276

Rev. 4.00

Table 4. Serial Data Output Mode Timing (

See Figure 6.)

Tmin to

Tmax

Limits

Comments/Test Conditions

STS low to SDO (DB11) Valid,

ns max

Load Ckt 4 of

Figure 3.

RD = 0
Minimum clock high pulse width

ns max

SDC low to data valid delay

150

200

ns max

Load ckt of

Figure 3., C

= 20pF

200

250

ns max

Load ckt of

Figure 3., C

= 100pF

Serial Data Output Timing

Time

Interval

Table 5. Logic Truth Table Serial Data Output Mode

ADEN

Data

STL

STS

Comments

No Operation

Hi-Z

Serial mode enabled (1)

Hi-Z

No operation if ADEN = 0

Hi-Z

Input MUX channel selected, STL
set on falling edge of WR

Hi-Z

MUX select disabled

Hi-Z

Start convert on WR rising edge

Hi-Z

Start convert on STL falling edge

Hi-Z

STS goes low at end of conversion

PXS

ADC Channel Select and Start Convert

DB0/SDC

Serial output (DB11/SDO) and
serial clock input (DB0/SDC)
enabled

MSB (DB11)

MSB data available at DB11/SDO

DB10

Next significant bit shifted out to
DB11/SDO

DB10

No Operation

DB10

No Operation

DB9

Next significant bit shifted out to
DB11/SDO

Hi-Z

Data outputs/SDC input disabled

Hi-Z

Data outputs/RD disabled when
STS = 1

Hi-Z

STL, MUX select disabled when
ADEN = 0

MSB (DB11)

New data appears at DB11/SDO
on falling edge of STS

Read ADC Data (

See Table 4. and Figure 6.)

Table 6. Key Output Codes vs. Input Voltage (2's Complement Code)

2's Complement Output Code (Hexidecimal)

Ideal Transition Voltage

+FS 1 1/2 LSB

0 V +1/2 LSB

0 V 1/2 LSB

FS +1/2 LSB

0111

0000

1111

1000

1111

0000

1111

0000

1110 (7fe) to

0000 (000) to

1111 (fff) to

0000(800) to

0111

0000

1000

1111

0000

1111 (7ff)

0001 (001)

0000 (000)

0001 (801)

MP3276

Rev. 4.00

APPLICATION INFORMATION

The MP3276 is a complete A/D converter system, with its

own built-in reference and clock. It may be used by itself ("stand-
alone" operation), or it may be interfaced with a microprocessor
which can control both conversion and formatting of output.

Successful application of the MP3276 requires careful atten-

tion to four main areas:

Physical layout.

Connection/Trimming according to mode of operation.

Conditioning of input signals.

Control and Timing considerations.

Physical Layout

The 12-bit accuracy of the MP3276 represents a dynamic

range of 72dB. Precautions must be taken to avoid any interfer-
ing signals, whether conducted or radiated, to assure that this is
not degraded.

Avoid placing the chip and its analog signals near logic
traces. In general, using a double sided printed circuit
card with a good ground plane on the component side is
recommended. Routing analog signals between ground
traces will help isolate digital control logic. If these lines
cross, do so at right angles. The GND Ref. is the positive
terminal of the MUX/Instrumentation amplifier and will
provide common mode noise rejection. It should be
close to and shielded together with the channel inputs in
order to take advantage of this feature.

Power supplies should be quiet and well regulated.
Grounds should be tied together at the package and
back to the system ground with a single path. Bypass the
supplies at the device with a 0.01 to 0.1

F ceramic cap

and a 10-47

F tantalum type, in parallel.

"Stand-Alone" Operation

The MP3276 can be used in "stand-alone" operation, which is

useful in systems not requiring full computer bus interface capa-
bility. This operation is available for either parallel or serial mode.

For this operation, CS = 0, ADEN = 1, and conversion is con-

trolled by WR. The 3-state buffers are enabled when RD goes
low. There are two possible conditions that the 3-state buffers
could be in during a conversion. If RD goes low prior to WR, the
output buffers are enabled and the data from the previous con-
version is available at the outputs during STL = 1. At the end of
the present conversion which is initiated at the rising edge of
WR, STS returns low and the new conversion result is placed on
the output data buffers.

If WR goes low prior to RD, the data buffers remain in a high

impedance state and conversion is initiated at the rising edge of
WR. Upon the end of the conversion the STS returns low and
the conversion result is placed on the output data buffers. It is

imperative that RD or WR not change during a conversion to in-
sure that errors will not occur.

Ground Reference

The ground reference pin can be used for remote ground

sensing of a common mode input signal with a maximum 6 V p-p
around AGND.

This common input can also be used to dither each input's

"zero". By averaging multiple conversions digitally, higher reso-
lution for each input conversion can be obtained. Patterns for
this dither can be a ramp, a stair step, or white noise.

COMP

S
A

VDAC

130k

26k

130k

26k

1 of 16

GND Ref.

Figure 7. Equivalent Input Circuit

1/2
V

REF

Quasi Differential Sampling

Method 1

For remote ground sensing where the remote ground does

not change more than

3 V from the A/D ground, connect GND

Ref to the remote ground.

Method 2

Where Method 1 applies to each channel or group of chan-

nels, add a mux to allow connecting the appropriate ground to
GND Ref.

Method 3

Use two parts. Tie both GND Ref pins together and connect

this node to the "common" remote GND. Control the sample
point by connecting each STL through an "OR" gate whose out-
put is "NAND" connect with WR (inverted WR). Use this output
as WR to both WR inputs. By controlling the WR, sample delay
differences between the two converters is minimized. Two parts
from the same date code will further minimize this difference.
Treat one A/D as the (+) terminal and the other as the () termi-
nal of the differential signal. Now the difference can be taken
digitally.

MP3276

Rev. 4.00

0.079

0.095

2.00

2.41

0.016

0.020

0.406

0.508

1.086

1.110

27.6

28.2

0.788

0.812

20.0

20.6

0.100 typ.

2.54 typ.

0.170

0.190

4.32

4.83

0.050 typ.

1.27 typ.

68 LEAD PIN GRID ARRAY

(PGA)

G68

SYMBOL

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

Seating Plane

Pin 1

CONNECTION TABLE

L10

K10

K11

J10

J11

H10

H11

G10

G11

F10

F11

E10

E11

D10

D11

C10

C11

B11

PAD

PIN

PAD

PIN

PAD

PIN

Note: The letters A-H and numbers 1-8 are the coordinates
of a grid. For example, pin 1 is at the intersections of the "B"
vertical line and the "2" horizontal line.

B10

A10

PAD

PIN

Index
Mark

IP = Index Pin, not connected

MP3276

Rev. 4.00

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary
depending upon a user's specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.

Copyright 1994 EXAR Corporation
Datasheet April 1995
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

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