MP7612
Rev. 3.00
E
1996
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538
z
(510) 668-7000
z
FAX (510) 668-7010
FEATURES
Eight Independent 12-Bit DACs with Output Amplifiers
Low Power 320 mW (typ.)
Serial Digital Data and Address Port (3-Wire
Standard)
12-Bit Resolution, 11 Bit Accuracy
Extremely Well Matched DACs
Extremely Low Analog Ground Current (<60
A/Channel)
+10 V Output Swing with +11.4 V Supplies
Zero Volt Output Preset (Data = 10 .. 00)
Rugged Construction Latch-Up Free
Parallel Version: MP7613
Octal 12-Bit DAC Array
TM
D/A Converter with Output Amplifier
and Serial Data/Address
P Control Logic
APPLICATIONS
Data Acquisition Systems
ATE
Process Control
Self-Diagnostic Systems
Logic Analyzers
Digital Storage Scopes
PC Based Controller/DAS
...the analog plus company
TM
April 1996-4
GENERAL DESCRIPTION
The MP7612 provides eight independent 12-bit resolution
Digital-to-Analog Converters with voltage output amplifiers and
a 3-wire standard serial digital address and data port.
Typical DAC matching for B grade versions is 0.7 LSB across
all codes. Accuracy of +0.75 LSB for DNL and +1 LSB for INL is
also achieved for B grades. The output amplifier is capable of
sinking and sourcing 5mA, and the output voltage settles to
12-bits in less than 30
s (typ.).
The MP7612 is equipped with a serial data (3-wire standard)
-processor logic interface to reduce pin count, package size,
and board space.
Built using an advanced linear BiCMOS, these devices offer
rugged solutions that are latch-up free, and take advantage of
EXAR's patented thin-film resistor process which exhibits excel-
lent long term stability and reliability.
SIMPLIFIED BLOCK DIAGRAM
VO0
VO7
SDO
V
RP
V
RN
DAC0
DAC7
V
RP
V
RN
+
+
D
Q
XR XE
LAT0
LAT7
D
Q
XR XE
12
12
RST
V
RN
V
RP
+
Tri-State Buffer
XE0 - XE7
4 to 16 Decoder
Not Used
8
LD
12
4
SDI
CLK
LD
LAT
D
Q
EN
LAT
D
Q
EN
A0 to A3
D0 to D11
16-Bit Shift Register
V
EE
V
EE
V
CC
V
CC
AGND
AGND V
REF
DGND DV
DD
V
RP
XE0
XE7
LD
8
MP7612
2
Rev. 3.00
ORDERING INFORMATION
Package
Type
Temperature
Range
INL
(LSB)
Part No.
PLCC
40 to +85
C
MP7612AP
2
PLCC
40 to +85
C
MP7612BP
1
Res.
(Bits)
12
12
DNL
(LSB)
1
0.75
FSE
(LSB)
8
6
SOIC
40 to +85
C
MP7612AS
2
SOIC
40 to +85
C
MP7612BS
1
12
12
1
0.75
8
6
PIN CONFIGURATIONS
VO0
VO1
VO2
VO3
V
EE
V
CC
V
REF
V
CC
V
EE
VO4
VO5
VO6
DGND
DV
DD
DGND
N/C
SDO
SDI
CLK
AGND
28
1
15
14
2
3
4
5
6
7
17
16
8
9
19
18
10
11
23
22
21
20
27
26
25
24
12
13
VO7
AGND
N/C
N/C
N/C
N/C
28 Pin SOIC (Jedec, 0.346")
LD
RST
44 Pin PLCC
1
See the following page for
pin descriptions
MP7612
3
Rev. 3.00
PIN DESCRIPTION
SOIC
Pin #
PLCC
Pin #
Symbol
Description
1
2
AGND
Analog Ground
2
3
VO0
DAC 0 Output
3
4
VO1
DAC 1 Output
4
5
VO2
DAC 2 Output
5
6
VO3
DAC 3 Output
6
7
V
EE
Analog Negative Power Supply (12 V)
7
9
V
CC
Analog Positive Power Supply (+12 V)
8
12
V
REF
Voltage Reference Input (+5 V)
9
13
V
CC
Analog Positive Power Supply (+12 V)
10
15
V
EE
Analog Negative Power Supply (12 V)
11
18
VO4
DAC 4 Output
12
19
VO5
DAC 5 Output
13
20
VO6
DAC 6 Output
14
21
VO7
DAC 7 Output
15
24
AGND
Analog Ground
16
N/C
No Connection
17
26
RST
Reset all DACs to 0 V Output
18
N/C
No Connection
19
29
LD
Load Signal; Load Data to Selected DAC
20
31
CLK
Serial Data Clock
21
32
SDI
Serial Data Input
22
34
SDO
Shift Register Serial Output
23
N/C
No Connection
24
37
DGND
Digital Ground
25
40
DV
DD
Digital Positive Power Supply (+5 V)
26
N/C
No Connection
27
1, 8, 10, 11, 14,
16, 17, 22, 23,
25, 27, 28, 30,
33, 35, 36, 38,
39, 41, 42, 43
N/C
No Connection
28
44
DGND
Digital Ground
MP7612
4
Rev. 3.00
25
C
Tmin to Tmax
ELECTRICAL CHARACTERISTICS
V
CC
= +12 V, V
EE
= 12 V, V
REF
= 5 V, DV
DD
= 5.0 V, T = 25
C, Output Load = 5k
(unless otherwise noted)
Parameter
Symbol
Min
Typ
Max
Min
Max
Units
Test Conditions/Comments
STATIC PERFORMANCE
Resolution (All Grades)
N
12
Bits
Integral Non-Linearity
INL
LSB
End Point Linearity Spec
(Relative Accuracy)
A
2
2
B
1
1
Differential Non-Linearity
DNL
LSB
A
1
1
B
0.75
0.75
Positive Full Scale Error
+FSE
LSB
A
6
8
8
B
4
6
6
Negative Full Scale Error
FSE
LSB
A
6
8
8
B
4
6
6
Bipolar Zero Offset
ZOFS
LSB
A
4
4
B
3
3
INL Matching
INL
LSB
A
2
2
B
1.5
1.5
All Channels Maximum Error
ME
LSB
with DAC 0 adjusted to
minimum error
A
4
4
B
2
2
Bipolar Zero Matching
ZOFS
LSB
A
4
4
B
3
3
Full Scale Error Matching
FSE
LSB
A
4
4
B
3
3
DYNAMIC PERFORMANCE
Voltage Settling from LD
t
sd
30
50
50
sec
ZS to FS (20 V Step)
to VDAC Out
1
Channel-to-Channel Crosstalk
1, 6
CT
0.04
LSB
DC
Digital Feedthrough
1, 6
Q
70
dB
CLK and Data to V
OUTi
Power Supply Rejection Ratio
PSRR
5
ppm/%
V
EE
&
V
CC
= +5%, ppm of FS
REFERENCE INPUTS
Impedance of V
REF
REF
350
700
1.05k
350
1.05k
See Application Hints for driving
the reference input
V
REF
Voltage1,
2
V
REF
3.5
6
V
MP7612
5
Rev. 3.00
25
C
Tmin to Tmax
ELECTRICAL CHARACTERISTICS (CONT'D)
Parameter
Symbol
Min
Typ
Max
Min
Max
Units
Test Conditions/Comments
DIGITAL INPUTS
3
Logic High
V
IH
2.4
V
Logic Low
V
IL
0.8
V
Input Current
I
L
+10
A
Input Capacitance
1
C
L
8
pF
ANALOG OUTPUTS
Output Swing V
EE
+1.4 V
CC
1.4
V
Output Drive Current
5
5
mA
Output Impedance
R
O
1
Output Short Circuit Current
I
SC
25
mA
+FS to AGND
30
mA
+FS to V
EE
40
mA
FS to AGND
55
mA
FS to V
CC
DIGITAL OUTPUTS
Output High Voltage
V
OH
4.5
V
Output Low Voltage
V
OL
0.5
V
POWER SUPPLIES
V
CC
Voltage
5
V
CC
V
REF
+1.5
12
12.75 V
REF
+1.5 12.75
V
V
EE
Voltage
5
V
EE
12.75
12
5
12.75
5
V
DV
DD
Voltage
DV
DD
4.5
5
5.5
4.5
5.5
V
Positive Supply Current
I
CC
8
10
10
mA
Bipolar zero
Negative Supply Current
I
EE
15
20
20
mA
Bipolar zero
Digital Supply Current
I
DD
2
2
mA
Bipolar zero
Power Dissipation
PD
ISS
320
420
450
mW
Bipolar zero
ANALOG GROUND CURRENT
Per Channel
1
I
AGND
60
A
See Application Notes
DIGITAL TIMING
SPECIFICATIONS
1,4
V
IL
= 0, V
IH
= 5.0, C
L
= 20 pF
Input Clock Pulse Width
t
CH
, t
CL
35
ns
Data Setup Time
t
DS
15
ns
Data Hold Time
t
DH
15
ns
CLK to SDO Propagation Delay
t
PD
40
ns
DAC Register Load Pulse Width
t
LD
35
ns
Preset Pulse Width
t
PR
50
ns
Clock Edge to Load Time
t
CKLD1
140
ns
Note: t
LD
and t
CKLD2
cannot both
t
CKLD2
0
be min. since t
CKLD1
=t
CKLD2
+t
LD
LD Falling Edge to SDO
t
HZ1
50
ns
Tri-state Enable
LD Rising Edge to SDO
t
HZ2
50
ns
Tri-state Disable
LD Rising Edge to CLK Enable
t
LDCK
50
ns
LD Set-up Time with Respect
t
LDSU
30
ns
to CLK
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