MP7628
1
Rev. 2.00
FEATURES
Readback Capability for all DACs
On-Chip Latches for All DACs
Linearity Grades to +1/8 LSB
Single Supply Voltage (5 Volt)
DACs Matched to 1%
Four Quadrant Multiplication
Microprocessor TTL/CMOS Compatible
Latch-Up Free
Dual Version: MP7529B
5 V CMOS
Quad Multiplying 8-Bit
Digital-to-Analog Converter
APPLICATIONS
Microprocessor Controlled Gain and Attenuation
Circuits
Microprocessor Controlled/Programmable
Power Supplies
Hardware Redundant Applications Requiring
Data Readback
GENERAL DESCRIPTION
The MP7628 is a quad 8-bit Digital-to-Analog Converter de-
signed using a decoded DAC architecture featuring excellent
DAC-to-DAC matching and guaranteed monotonicity.
Separate on-chip latches are provided for each DAC to allow
easy microprocessor interface.
The readback function allows the user to poll or read the data
latches, eliminating the need for storing information in RAM. In
the event the microprocessor power supply is interrupted, it can
poll the DACs to establish the last known system state.
Data is transferred into any of the four DAC data latches via
common 8-bit TTL/CMOS compatible input port. Control inputs
DS1, DS2 and A/B determine which DAC is to be loaded. The
MP7628's load cycle is similar to the write cycle of a random ac-
cess memory and the device is bus compatible with most 8-bit
microprocessors.
The device operates at +5 V power supply and dissipates
less than 5mW.
All DACs offer excellent four quadrant multiplication charac-
teristics with a separate reference input and feedback resistor
for each DAC.
THREE-STATE
BUFFER
SIMPLIFIED BLOCK DIAGRAM
THREE-STATE
BUFFER
LATCH A
DAC A
LATCH B
DAC B
THREE-STATE
BUFFER
LATCH C
DAC C
THREE-STATE
BUFFER
LATCH D
DAC D
BI-
DIRECTIONAL
LINE
DRIVER
CONTROL
LOGIC
DB0
(LSB)
DATA BUS
DB7
(MSB)
GND
V
DD
V
REFB
V
REFA
R
FBA
I
OUT1A
I
OUT2A
/
I
OUT2B
I
OUT1B
R
FBB
R
FBC
I
OUT1C
I
OUT2C
/
I
OUT2D
I
OUT1D
R
FBD
R
FB
V
REFD
V
REFC
R
FB
R
FB
R
FB
A/B
R/W
DS1
DS2
MP7628
2
Rev. 2.00
ORDERING INFORMATION
Package
Type
Temperature
Range
Part No.
Ceramic Dip
MP7628AD
Ceramic Dip
MP7628BD
Ceramic Dip
MP7628SD*
Ceramic Dip
MP7628TD*
Plastic Dip
MP7628JN
40 to +85
C
55 to +125
C
55 to +125
C
Plastic Dip
MP7628KN
+1/2
+1/4
+1/2
+1/4
+1/2
+1/4
+1/2
+1/4
+1/2
+1/4
+1/2
+1/4
+1.8
+0.9
+1.8
+0.9
+1.8
+0.9
PLCC
MP7628JP
+1/2
+1/2
+1.8
SOIC
MP7628JS
+1/2
+1/2
+1.8
SOIC
MP7628KS
+1/4
+1/4
+0.9
40 to +85
C
40 to +85
C
40 to +85
C
40 to +85
C
40 to +85
C
40 to +85
C
PLCC
MP7628KP
40 to +85
C
+1/4
+1/4
+0.9
INL
(LSB)
Gain Error
(% FSR)
DNL
(LSB)
*Contact factory for non-compliant military processing
PIN CONFIGURATIONS
See Packaging Section for
Package Dimensions
1
2
3
4
5
6
7
8
9
10
28
27
26
25
24
23
22
21
20
19
11
12
13
14
18
17
16
15
(LSB) DB0
DB1
DB2
DB3
DB4
DB5
DB7 (MSB)
DB6
28 Pin CDIP, PDIP (0.600")
D28, N28
V
DD
V
REFA
R
FBA
R
FBB
V
REFB
GND
V
REFC
R
FBC
R
FBD
V
REFD
I
OUT1A
I
OUT2A
/I
OUT2B
I
OUT1B
I
OUT1C
I
OUT2C
/I
OUT2D
I
OUT1D
3
2
1
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
28
27
26
25
24
23
22
21
20
19
28 Pin PLCC
P28
V
DD
V
REFA
R
FBA
I
OUT1A
DB0
DB1
DB2
R
FBB
V
REFB
I
OUT2A
/
I
OUT2B
I
OUT1B
DB3
DB4
DB5
DB6
DB7
(MSB)
R
FBD
V
REFD
I
OUT1C
I
OUT2C
/
I
OUT2D
I
OUT1D
R
FBC
V
REFC
GND
28
1
15
14
2
3
4
5
6
7
17
16
8
9
19
18
10
11
23
22
21
20
27
26
25
24
12
13
(LSB)
28 Pin SOIC (Jedec, 0.300")
S28
See
Pin Out
at Left
A/B
R/W
DS1
DS2
DS1
DS2
A/B
R/W
MP7628
3
Rev. 2.00
PIN OUT DEFINITIONS
1
V
DD
Power Supply
2
V
REFA
Reference Voltage for DAC A
3
R
FBA
Feedback Resistor for DAC A
4
I
OUT1A
Current Output 1 DAC A
5
I
OUT2A
/
Current Output 2 DAC A/DAC B
I
OUT2B
6
I
OUT1B
Current Output 1 DAC B
7
R
FBB
Feedback Resistor for DAC B
8
V
REFB
Reference Voltage for DAC B
9
DB0
Data Input Bit 0 (LSB)
10
DB1
Data Input Bit 1
11
DB2
Data Input Bit 2
12
DB3
Data Input Bit 3
13
DB4
Data Input Bit 4
14
DB5
Data Input Bit 5
15
DB6
Data Input Bit 6
16
DB7
Data Input Bit 7 (MSB)
17
A/B
DAC Selection
18
R/W
Read/Write
19
DS1
Control 1
20
DS2
Control 2
21
V
REFD
Reference Voltage for DAC D
22
R
FBD
Feedback Resistor for DAC D
23
I
OUT1D
Current Output 1 DAC D
24
I
OUT2C
/
Current Output 2 DAC C/DAC D
I
OUT2D
25
I
OUT1C
Current Output 1 DAC C
26
R
FBC
Feedback Resistor for DAC C
27
V
REFC
Reference Voltage for DAC C
28
GND
Ground
PIN NO.
NAME
DESCRIPTION
MP7628
4
Rev. 2.00
ELECTRICAL CHARACTERISTICS
(V
DD
= + 5 V, V
REF
= +10 V unless otherwise noted)
25
C
Tmin to Tmax
Parameter
Symbol
Min
Typ
Max
Min
Max
Units
Test Conditions/Comments
STATIC PERFORMANCE
1
FSR = Full Scale Range
Resolution (All Grades)
N
8
8
Bits
Integral Non-Linearity
INL
LSB
End Point Linearity Spec.
(Relative Accuracy)
J, A, S
+1/2
+1/2
K, B, T
+1/4
+1/4
Differential Non-Linearity
DNL
LSB
All grades monotonic over full
J, A, S
+1/2
+1/2
temperature range.
K, B, T
+1/4
+1/4
Gain Error
GE
% FSR
Using Internal R
FB
J, A, S
+1.5
+1.8
Digital Inputs = V
INH
K, B, T
+0.8
+0.9
Gain Temperature Coefficient
2
TC
GE
+2
ppm/
C
Gain/
Temperature
Power Supply Rejection Ratio
PSRR
+200
+400
ppm/%
|
Gain/
V
DD
|
V
DD
= + 5%
Digital Inputs = V
INH
Output Leakage Current (all)
I
OUT1
+50
+200
nA
Digital Inputs = V
INL
REFERENCE INPUT
Voltage Range
2
+20
+20
V
Input Resistance
R
IN
12
28
12
28
k
DIGITAL INPUTS
3
Logic Thresholds
V
INH
2.4
2.4
V
V
INL
0.8
0.8
V
Input Leakage Current
I
LKG
+1
+10
A
Input Capacitance
2
C
IN
3
pF
DATA BUS OUTPUTS
Output Capacitance
2
C
OUT
7
pF
Input Leakage Current
I
LKG
+1
+10
A
ANALOG OUTPUTS
Propagation Delay
2
500
750
ns
From digital input to 90% of
final analog output current
Output Capacitance
2
C
OUT
120
pF
DAC Inputs all 1's
C
OUT
80
pF
DAC Inputs all 0's
Glitch Energy
2
160
440
nVs
Typical for code transition from
all 0's to all 1's
MP7628
5
Rev. 2.00
25
C
NOTES:
Specifications are subject to change without notice
ELECTRICAL CHARACTERISTICS (CON'T)
Tmin to Tmax
Parameter
Symbol
Min
Typ
Max
Min
Max
Units
Test Conditions/Comments
POWER SUPPLY
5
Functional Voltage Range
2
V
DD
4.5
5.5
4.5
5.5
V
Supply Current
I
DD
50
50
A
All digital inputs = 0 V or all = 5 V
SWITCHING
CHARACTERISTICS
2, 4
Data Write Time
t
W
320
400
ns
Write Strobe Req.
t
DSW
200
250
ns
Data Hold Time
t
DHLD
40
50
ns
Data Read Time
t
R
480
600
ns
3-state Hold Time
t
TSHD
240
300
ns
Read Strobe Req.
t
DSR
320
400
ns
1
Full Scale Range (FSR) is 10V for unipolar mode.
2
Guaranteed but not production tested.
3
Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur.
4
See timing diagrams.
5
Specified values guarantee functionality. Refer to other parameters for accuracy.
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
C unless otherwise noted)
1, 2
V
DD
to GND
+7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Input Voltage to GND (2)
GND 0.5 to V
DD
+0.5 V
.
I
OUT1
, I
OUT2
to GND (2)
GND 0.5 to V
DD
+0.5 V
. . . . . . . .
V
REF
to GND
+25 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
RFB
to GND
+25 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature
65
C to +150
C
. . . . . . . . . . . . . . . . .
Lead Temperature (Soldering, 10 seconds)
+300
C
. . . . . .
Package Power Dissipation Rating to 75
C
CDIP, PDIP, SOIC, PLCC
1050mW
. . . . . . . . . . . . . . . . .
Derates above 75
C
14mW/
C
. . . . . . . . . . . . . . . . . . . . .
NOTES:
1
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings
should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies.
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