MP7643
1
Rev. 1.00
4-Channel, Programmable Gain
Voltage Output, 15 MHz Input Bandwidth
8-Bit DACs with Multiplying
Parallel Digital Data Port
FEATURES
Programmable Gain
4 Independent 2-Quadrant Multiplying 8-Bit DACs
with Output Amplifiers
Dual Positive (+10 V and +5 V) Supplies or
Dual (+5 V) Supplies Capability
High Speed:
12.5 MHz Digital Clock Rate
V
REF to
V
OUT
Settling Time: 150ns to 8-bit
(typ)
Voltage Reference Input Bandwidth:
15 MHz
Very Low Noise Gain Control
Low Power: 80mW
Low AC Voltage Reference Feedthrough
Excellent Channel-to-Channel Isolation
DNL = +0.5 LSB, INL = +1 LSB (typ)
DACs Matched to +0.5% (typ)
Low Harmonic Distortion: 0.25% typical with
V
REF
= 1 V p-p @ 1 MHz
Latch-Up Free
ESD Protection: 2000 V Minimum
APPLICATIONS
Direct High-Frequency Automatic Gain Control
Video AGC & CCD Level AGC
Convergence Adjustment for High-Resolution
Monitors (Workstations)
Multiplier Replacement
GENERAL DESCRIPTION
The MP7643 is ideal for digital gain control of high frequency
analog signals such as video, composite video and CCD. The
device includes 4-channels of high speed, wide bandwidth, two
quadrant multiplying, 8-bit accurate digital-to-analog converter.
It includes an output drive buffer per channel capable of driving a
+1mA (typ) load. DNL of better than +0.5 LSB is achieved with a
channel-to-channel matching of typically 0.5%. Stability, match-
ing, and precision of the DACs are achieved by using MPS' thin
film technology. Excellent channel-to-channel isolation is also
achieved with MPS' BiCMOS process which cannot be
achieved using a typical CMOS technology.
An open loop architecture (patent pending) provides wide
small signal bandwidth from V
REF
to output up to 15 MHz (typ),
fast output settling time of 150 ns, and excellent V
REF
feedthrough isolation. The negative feedback terminal of the
output op amp is available for user gain control. In addition, low
distortion in the order of 0.25% with a 1 V p-p, 1 MHz signal is
achieved.
The combination of a constant input Z and the ability to vary
V
REFN
within V
CC
1.8 V to V
EE
+1.5 V allows flexibility for opti-
mum system design.
The MP7643 is fabricated on a junction isolated, high speed
BiCMOS (BiCMOS IV
TM
) process with thin film resistors. This
process enables precision high speed analog/digital (mixed-
mode) circuits to be fabricated on the same chip.
ORDERING INFORMATION
Package
Type
Temperature
Range
Part No.
Gain Error
(% FSR)
SOIC
40 to +85
C
MP7643AS
+0.5
+1
+1.5
Plastic Dip
40 to +85
C
MP7643AN
+0.5
+1
+1.5
INL
(LSB)
DNL
(LSB)
MP7643
2
Rev. 1.00
SIMPLIFIED BLOCK DIAGRAM
V
REF1
V
OUT1
INV1
V
REF2
V
OUT2
INV2
V
REF3
V
OUT3
INV3
V
REF4
V
OUT4
INV4
V
REFN
V
DD
V
CC
V
EE
DBO
DB7
(MSB)
LD
A1
A0
DGND
Control
Logic
LATCH4
LATCH3
LATCH2
LATCH1
DAC1
DAC2
DAC3
DAC4
MP7643
3
Rev. 1.00
PIN CONFIGURATIONS
See Packaging Section for
Package Dimensions
13
16
14
15
1
2
3
4
5
6
7
8
9
10
28
27
26
25
24
23
22
21
20
19
11
18
12
17
28 Pin PDIP (0.300")
NN28
A1
INV4
DB7
V
REFN
DGND
A0
28 Pin SOIC (Jedec, 0.300")
S28
28
1
15
14
2
3
4
5
6
7
17
16
8
9
19
18
10
11
23
22
21
20
27
26
25
24
12
13
DB5
DB6
V
DD
V
CC
V
EE
V
REF1
V
REF2
V
OUT2
INV2
DB4
DB3
LD
V
REF4
V
REF3
V
OUT3
INV3
INV1
V
OUT1
DB2
DB1
DB0
V
OUT4
DB7
V
REFN
DGND
DB5
DB6
V
DD
V
CC
V
EE
V
REF1
V
REF2
V
OUT2
INV2
INV1
V
OUT1
A1
INV4
A0
DB4
DB3
LD
V
REF4
V
REF3
V
OUT3
INV3
DB2
DB1
DB0
V
OUT4
PIN OUT DEFINITIONS
1
DB5
Data Input Bit 5
2
DB6
Data Input Bit 6
3
V
DD
Digital Positive Supply
4
V
CC
Analog Positive Supply
5
V
EE
Analog Negative Supply
6
DB7
Data Input Bit 7
7
V
REFN
Negative Reference Input
8
DGND
Digital Ground
9
INV1
Inverting Input 1
10
V
OUT1
DAC 1 Output
11
V
REF1
DAC 1 Positive Reference Input
12
V
REF2
DAC 2 Positive Reference Input
13
V
OUT2
DAC 2 Output
14
INV2
Inverting Input 2
PIN NO.
NAME
DESCRIPTION
15
INV3
Inverting Input 3
16
V
OUT3
DAC 3 Output
17
V
REF3
DAC 3 Positive Reference Input
18
V
REF4
DAC 4 Positive Reference Input
19
V
OUT4
DAC 4 Output
20
INV4
Inverting Input 4
21
A0
DAC Address Bit 0
22
A1
DAC Address Bit 1
23
DB0
Data Input Bit 0
24
DB1
Data Input Bit 1
25
DB2
Data Input Bit 2
26
LD
Load Data to Selected DAC
27
DB3
Data Input Bit 3
28
DB4
Data Input Bit 4
PIN NO.
NAME
DESCRIPTION
MP7643
4
Rev. 1.00
ELECTRICAL CHARACTERISTICS TABLE FOR DUAL SUPPLIES
Unless Otherwise Noted: V
DD
= 5 V, V
CC
= +5 V, V
EE
= 5 V, V
REF
= 3 V and 3 V, T = 25
C,
Output Load = No Resistive Load, V
REFN
= DGND = 0 V, Gain = 1
25
C
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions/Comments
DC CHARACTERISTICS
Resolution (All Grades)
N
8
Bits
Differential Non-Linearity
DNL
+0.5
+0.8
LSB
Integral Non-Linearity
INL
+1
+1
LSB
Monotonicity
Guaranteed
Gain Error
GE
+1.5
% FSR
FSR = Full Scale Range
1
Zero Scale Offset
Z
OFS
+50
mV
Output Drive Capability
I
O
+1
mA
REFERENCE/INV INPUTS
Impedance of V
REF
REF
6
18
k
Voltage Range
V
RP
V
EE
+1.5
V
CC
1.8
V
V
REF
Max Swing is V
REFN
+3 V
INV DC Voltage Range
V
RN
V
EE
+1
0
V
DYNAMIC
CHARACTERISTICS
2
R
L
= 5 k, C
L
= 20 pF
Input to Output Bandwidth
15
MHz
V
R
= 1.6 V pp, R
L
= 5k to V
EE
Input to Output Settling Time
5
150
ns
V
R
= 1.6 V pp, R
L
= 5k to V
EE
Small Signal Voltage Reference
t
r
15
MHz
V
OUT
=50mV p-p above code 16
Input to Output Bandwidth
Small Signal Voltage Reference
t
r
15
MHz
V
OUT
=50mV p-p for all codes
Input to Output Bandwidth
Voltage Settling from V
REF
to
t
sr
300
ns
V
R
=0 to V
R
= 3V Step
6
V
DAC
Out
to 1 LSB
Voltage Settling from Digital
t
sd
300
ns
ZS to FS to 1 LSB
Code to V
DAC
Out
V
REF
Feedthrough
F
DT
TBD
dB
Codes=0 @ 1 MHz
Group Delay
GD
TBD
ns
Harmonic Distortion
T
HD
TBD
%
V
REF
=1MHz Sine 3V p-p
Channel-to-Channel Crosstalk
C
T
TBD
dB
@ 1 MHz, single channel
Digital Feedthrough
Q
TBD
nVS
CLK to V
OUT
Power Supply
PSRR
+0.05
%/%
V=+5%
Rejection Ratio
POWER CONSUMPTION
Positive Supply Current
I
CC
12
mA
V
REF
= 0 V
Negative Supply Current
I
EE
12
mA
V
REF
= 0 V
Power Dissipation
P
DISS
80
mW
V
REF
= 0 V, Codes = all 1
DIGITAL INPUT
CHACTERISTICS
Logic High
3
V
IH
2.4
V
Logic Low
3
V
IL
0.8
V
Input Current
I
L
+10
A
Input Capacitance
2
C
L
8
pF
MP7643
5
Rev. 1.00
ELECTRICAL CHARACTERISTICS TABLE
Description
Symbol
Min
Typ
Max
Units
Conditions
DIGITAL TIMING
SPECIFICATIONS (2, 4)
Address to LD Setup
t
AS
70
ns
Address to LD Hold
t
AH
0
ns
Data to LD Setup
t
DS
70
ns
Data to LD Hold
t
DH
0
ns
LD Pulse Width
t
LD
70
ns
PRESET Pulse Width
t
PR
50
ns
25
C
NOTES
1
Full Scale Range (FSR) is 3V.
2
Guaranteed but not production tested.
3
Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur.
4
See Figure 1.
5
For reference input pulse: t
R
= t
F
> 100 ns.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25
C unless otherwise noted)
1, 2
V
CC
to V
REFN
+6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
EE
to V
REFN
6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
CC
to DGND
+13.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
EE
to DGND
6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
REF
1-4 to DGND, V
REFN
V
CC
to V
EE
. . . . . . . . . . . . . . . . . .
V
OUT
1-4 to DGND, V
REFN
V
CC
to V
EE
. . . . . . . . . . . . . . . . . .
Digital Input & Output Voltage to DGND 0.5 to V
DD
+0.5 V
Operating Temperature Range
Extended Industrial
40
C to +85
C
. . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
65
C to 150
C
. . . . . . . . .
Storage Temperature
150
C
. . . . . . . . . . . . . . . . . . . . . . . . . .
Lead Temperature (Soldering, 10 sec)
+300
C
. . . . . . . . . . .
Package Power Dissipation Rating @ 75
C
PDIP, SOIC, PLCC
1050mW
. . . . . . . . . . . . . . . . . . . . . . .
Derates above 75
C
14mW/
C
. . . . . . . . . . . . . . . . . . . . .
NOTES:
1
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings
should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies.
All inputs have protection diodes which will protect the device from short
transients outside the supplies of less than 100mA for less than 100
s.
MP7643
6
Rev. 1.00
Figure 1. Timing Diagram
t
AS
t
AH
t
DS
t
DH
1/2 LSB
1/2 LSB
A1, A0
DB0 to DB7
LD
V
OUT
t
LD
t
SD
2-4
Decoder
A0, A1
LD
To DAC1 Latch Enable
To DAC2 Latch Enable
To DAC3 Latch Enable
To DAC4 Latch Enable
Figure 2. Input Control Logic (Simplified)
Block Diagram
L
L
L
DAC1 Transparent
L
L
DAC1 Latched
L
L
H
DAC2 Transparent
L
H
DAC2 Latched
L
H
L
DAC3 Transparent
H
L
DAC3 Latched
L
H
H
DAC4 Transparent
H
H
DAC4 Latched
H
X
X
No Operation
LD
A1
A0
Operation
Table 1. Truth Table
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
DAC Output Voltage
V
Oi
= V
REFN
+ (V
Ri
AGND) ( )
D
256
0
0
0
0
0
0
0
0
(
1
)
256
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
Table 2. DAC Transfer Function
Analog Output vs. Digital Code (With V
REF
Shorted to INV)
0
0
0
0
1
(V
Ri
V
REFN
)
+ V
REFN
(
)
256
(V
Ri
V
REFN
)
+ V
REFN
(
)
256
(V
Ri
V
REFN
)
+ V
REFN
255
254
V
REFN
Note: These outputs must be ratioed up for gain in the output amplifier.
MP7643
7
Rev. 1.00
THEORY OF OPERATION
The MP7643 is a 4-channel multiplying D/A converter that in-
corporates a novel open loop architecture invented by MPS.
The design produces the wider bandwidth, faster settling time,
more constant group delay, and a lower noise operation
compared to the conventional R-2R based architectures. This
device is particularly useful in applications where analog multi-
pliers are used to perform the gain adjustment function for high
frequency analog signal conditioning. Analog multipliers pro-
duce higher noise and offset. This design allows for digital con-
trol of gain with constant and very low noise from the low gain
through high gain ranges of operation.
Linearity Characteristics
Each DAC achieves DNL
+0.5 LSB (typ), INL
+1 LSB
(typ), and gain error
+1.5%. Since all 4 channel D/A convert-
ers are fabricated on the same IC, the linearity matching and
gain matching of +0.5% (typ) is achieved.
AC and Transient Settling Characteristics
The novel subranging architecture delivers a 15 MHz (typ.)
3 dB bandwidth. With all codes = 1 and a 1.6 V step impulse at
V
REF
(1-4), the analog output settles to 8 bits of accuracy in typi-
cally 150 ns (with R
L
= 5k to V
EE
). Also with V
REF
= 3 V or 3 V
and a FS to ZS or ZS to FS code change, the respective analog
output settles to 8 bits typically in 300 ns. Note that the AC per-
formance specifications also match between all 4 channels.
The above AC and transient performance is achieved with each
channel consuming only 20 mW (typ.) with either
5 V or 0 V to
10 V supplies.
Digital Interface
The MP7643 allows direct interface to most microprocessor
buses without additional I/O circuitry.
Figure 1. and Figure 2.
describe the operation, specification and interface characteris-
tics of the logic port.
The address bits A0 and A1 determine which D/A channel is
selected. When LD input is low the respective latch of the D/A is
enabled (digital input data becomes transparent to the latch and
the selected DAC channel), and digital data is loaded into the se-
lected DAC.
Power Supplies and Voltage Reference DC Voltage
Ranges
For the single supply operation, V
CC
= +10 V, V
DD
= +5 V, and
V
EE
= GND = 0 V. The V
OUT
1-4 and V
REF
1-4 range would be
V
CC
1.8 V (10 1.8 = 8.2 V) to V
EE
+1.5 V (0 + 1.5 = 1.5 V).
V
REFN
is the equivalent of AGND for this DAC. In this mode
V
REFN
can be set at (V
CC
+ V
EE
)/2 = (10 + 0)/2 = 5 V. V
REFN
DC
range can, however, be set from V
EE
+1.5 = 1.5 V to V
CC
1.5 =
8.2 V. Refer to
Table 2. for the relationship equations.
For the dual supply operation, V
CC
= +5, V
DD
= +5, and V
EE
=
5 V. The V
OUT
1-4 and V
REF
1-4 range would be V
CC
1.8 V (5
V 1.8 = 3.2 V) to V
EE
+1.5 V (5 + 1.5 = 3.5 V). In this mode
V
REFN
can be set to (V
CC
+ V
EE
)/2 = (5 5)/2 = 0 V. However,
V
REFN
DC range can be set from V
EE
+1.5 V = 3.5 V to V
CC
1.8
= +3.2 V. Refer to
Table 2. for the relationship equations.
About the INV Input and its DC Voltage Range
V
CC
V
OUT
1-4
INV
1-4
I1
Q2
Q1
V
REF
1-4
V
REFN
DAC
V
EE
+1
Figure 3. Simplified Block Diagram
As noted in the specification table, the max DC value of the
INV input pin is V
O
.
Figure 3. shows a simplified block diagram
of the internal circuitry around INV. If V
INV
exceeds V
O
, Q1 will
saturate and the amp and consequently the DAC becomes non-
functional.
The min DC range of INV is limited to V
be
(Q1) and V
CE
(sat)
of I
1
. Therefore, INV (min-DC) = V
EE
+1 V.
MP7643
8
Rev. 1.00
Graph 1. Relative Accuracy vs. Digital Code
DACs 1 to 4
Graph 2. Typical Gain and Group Delay vs. Frequency
(with 5K Resistor Across Output to V
EE
)
256
192
128
64
0
1
0.75
0.5
0.25
0
0.25
0.5
0.75
1
Digital Code
Relative Accuracy
(LSB)
MHz
Gain
(5dB/DIV)
Group Delay
(20 ns/DIV)
MP7643
9
Rev. 1.00
28 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
NN28
SYMBOL
MIN
MAX
MIN
MAX
INCHES
A
0.130
0.230
3.30
5.84
A
1
0.015
0.381
B
0.014
0.023
0.356
0.584
B
1
(1)
0.038
0.065
0.965
1.65
C
0.008
0.015
0.203
0.381
D
1.340
1.485
34.04
37.72
E
0.290
0.325
7.37
8.26
E
1
0.240
0.310
6.10
7.87
e
0.100 BSC
2.54 BSC
L
0.115
0.150
2.92
3.81
0
15
0
15
Q
1
0.055
0.070
1.40
1.78
S
0.020
0.100
0.508
2.54
MILLIMETERS
Note:
(1)
The minimum limit for dimensions B1 may be 0.023"
(0.58 mm) for all four corner leads only.
28
1
15
14
D
e
B
1
A
1
E
1
A
L
B
Q
1
Seating
Plane
C
E
S
MP7643
10
Rev. 1.00
SYMBOL
MIN
MAX
MIN
MAX
A
0.097
0.104
2.464
2.642
A1
0.0050
0.0115
0.127
0.292
B
0.014
0.019
0.356
0.483
C
0.0091
0.0125
0.231
0.318
D
0.701
0.711
17.81
18.06
E
0.292
0.299
7.42
7.59
e
0.050 BSC
1.27 BSC
H
0.400
0.410
10.16
10.41
h
0.010
0.016
0.254
0.406
L
0.016
0.035
0.406
0.889
0
8
0
8
INCHES
MILLIMETERS
28 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC)
S28
e
D
E
H
B
A
L
C
A
1
Seating
Plane
h x 45
28
15
14
MP7643
11
Rev. 1.00
Notes
MP7643
12
Rev. 1.00
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary
depending upon a user's specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.
Copyright 1995 EXAR Corporation
Datasheet April 1995
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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