MP8775
Rev. 3.01
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7017
E
1999
CMOS
20 MSPS, 8-Bit, High Speed
Analog-to-Digital Converter
FEATURES
8-Bit Resolution
20 MHz Sampling Rate
DNL = +1/2 LSB, INL = +1 LSB (typ)
Internal S/H Function
Single Supply: 5 V
V
IN
DC Range: 0 V to V
DD
V
REF
DC Range: 1 V to V
DD
Low Power: 85 mW typ. (excluding reference)
Latch-Up Free
ESD Protection: 2000 V Minimum
Power Down Available: MP8776
3 V Version: MP87L75
Small 20 Pin SOIC Package
APPLICATIONS
Digital Color Copiers
Cellular Telephones
CCD's Based Systems
Hardware Scanners
Video Capture Boards
March 1999-4
GENERAL DESCRIPTION
The MP8775 is an 8-bit Analog-to-Digital Converter in a
small 20 pin SOIC package.
Designed using an
advanced 5 V CMOS process, this part offers excellent
performance, low power consumption and latch-up free
operation.
This device uses a two-step flash architecture to maintain
low power consumption at high conversion rates. The
input circuitry of the MP8775 includes an on-chip S/H
function and allows the user to digitize analog input
signals between GND and V
DD
. Careful design and chip
layout have achieved a low analog input capacitance.
This reduces "kickback" and eases the requirements of
the buffer/amplifier used to drive the MP8775.
The designer can choose the internally generated
reference voltages by connecting V
RB
to V
RBS
and V
RT
to
V
RTS
, or provide external reference voltages to the V
RB
and V
RT
pins. The internal reference generates 0.6 V at
V
RB
and 2.6 V at V
RT
. Providing external reference
voltages allows easy interface to any input signal range
between GND and V
DD
. This also allows the system to
adjust these voltages to cancel zero scale and full scale
errors, or to change the input range as needed.
The device operates from a single +5 V supply. Power
consumption is 85 mW at F
s
= 20 MHz.
Specified for operation over the commercial / industrial
(--40 to +85C) temperature range, the MP8775 is
available in Surface Mount (SOIC), Shrunk Small Outline
(SSOP) and Plastic dual-in-line (PDIP) packages.
SIMPLIFIED BLOCK AND TIMING DIAGRAM
MSB
Comp.
LSB
Comp.
Latch
Latch
Encoder
+
Error
Correction
F/F
S/H
Clock Logic
AGND
DB7 (MSB)
DB0 (LSB)
CLK
V
RBS
V
RB
V
RT
V
RTS
V
DD
DV
DD
DGND
GND
AV
DD
V
IN
N
N-3
N-2
N-1
N
CLK
DB7-
DB0
Sample
MP8775
2
Rev. 3.01
ORDERING INFORMATION
Package
Type
Temperature
Range
Part No.
DNL
(LSB)
SOIC
--40 to +85
C
MP8775AS
INL
(LSB)
3/4
1 1/2
PDIP
--40 to +85
C
MP8775AN
3/4
1 1/2
SSOP
--40 to +85
C
MP8775AQ
3/4
1 1/2
PIN CONFIGURATIONS
See Packaging Section for
Package Dimensions
20 Pin SOIC (Jedec, 0.300")
20 Pin SSOP
DGND
V
RB
V
RBS
AGND
V
IN
AV
DD
V
RT
V
RTS
DV
DD
CLK
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7 (MSB)
DGND
DV
DD
20
1
11
10
2
3
4
5
6
7
15
14
13
12
17
16
8
9
19
18
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DGND
V
RB
V
RBS
AGND
V
IN
AV
DD
V
RT
V
RTS
DV
DD
CLK
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7 (MSB)
DGND
DV
DD
20 Pin PDIP (0.300")
PIN OUT DEFINITIONS
1
DGND
Digital Ground
2
DB0
Data Output Bit 0 (LSB)
3
DB1
Data Output Bit 1
4
DB2
Data Output Bit 2
5
DB3
Data Output Bit 3
6
DB4
Data Output Bit 4
7
DB5
Data Output Bit 5
8
DB6
Data Output Bit 6
9
DB7
Data Output Bit 7 (MSB)
10
DV
DD
Digital Power Supply
PIN NO.
NAME
DESCRIPTION
11
CLK
Sample Clock
12
DV
DD
Digital Power Supply
13
V
RTS
Generates 2.6 V if tied to V
RT
14
V
RT
Top Reference
15
AV
DD
Analog Power Supply
16
V
IN
Analog Input
17
AGND
Analog Ground
18
V
RBS
Generates 0.6 V if tied to V
RB
19
V
RB
Bottom Reference
20
DGND
Digital Ground
PIN NO.
NAME
DESCRIPTION
03
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CLK
PIPELINE DELAY
N + 1
N + 2
Sample "N"
t
HL
t
DL
N -- 3
N -- 2
N -- 1
DATA N
DATA
1/FS
t
PWH
t
PWL
Figure 1. MP8775 Timing Diagram
MP8775
4
Rev. 3.01
ELECTRICAL CHARACTERISTICS TABLE (CONT'D)
Description
Symbol
Min
Typ
Max
Units
Conditions
AC PARAMETERS
Differential Gain Error
d
G
2
%
FS = 4 x NTSC
Differential Phase Error
d
PH
1
FS = 4 x NTSC
POWER SUPPLIES
Operating Voltage (AV
DD
, DV
DD
)
9
V
DD
5
V
Current (AV
DD
+ DV
DD
)
I
DD
17
25
mA
Does not include ref. current
25
C
Notes:
1
Tester measures code transitions by dithering the voltage of the analog input (V
IN
). The difference between the measured and the
ideal code width (V
REF
/256) is the DNL error (Figure 2.). The INL error is the maximum distance (in LSBs) from the best fit line to
any transition voltage (Figure 3.). Accuracy is a function of the sampling rate (FS).
2
Guaranteed. Not tested.
3
Specified values guarantee functionality. Refer to other parameters for accuracy.
4
--1 dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy within
the specified bandwidth.
5
See V
IN
input equivalent circuit (Figure 4.). Switched capacitor analog input requires driver with low output resistance.
6
All inputs have diodes to DV
DD
and DGND. Input DC currents will not exceed specified limits for any input voltage between
DGND and DV
DD
.
7
t
R
, t
F
should be limited to >5 ns for best results.
8
Depends on the RC load connected to the output pin.
9
AGND and DGND pins are connected through the silicon substrate. Connect together at the package and to the analog ground plane.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
C unless otherwise noted)
1, 2, 3
V
DD
to GND
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
RT
& V
RB
V
DD
+0.5 to GND --0.5 V
. . . . . . . . . . . . . . . . . . . .
V
IN
V
DD
+0.5 to GND --0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
All Inputs
V
DD
+0.5 to GND --0.5 V
. . . . . . . . . . . . . . . . . . . . .
All Outputs
V
DD
+0.5 to GND --0.5 V
. . . . . . . . . . . . . . . . . . .
Storage Temperature
--65 to +150
C
. . . . . . . . . . . . . . . . . . .
Lead Temperature (Soldering 10 seconds)
+300
C
. . . . . . .
Package Power Dissipation Rating @ 75
C
SOIC, SSOP, PDIP
700 mW
. . . . . . . . . . . . . . . . . . . . . . .
Derates above 75
C
9 mW/C
. . . . . . . . . . . . . . . . . . . . . .
Notes:
1
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short
transients outside the supplies of less than 100mA for less than 100
m
s.
3
V
DD
refers to AV
DD
and DV
DD
. GND refers to AGND and DGND.
MP8775
5
Rev. 3.01
N + 1
N
N--1
Output
Codes
Analog
Input
Code Width (N) = V
(
N+1)
-- V
(
N)
LSB = [
V
RT
-- V
RB
] / 256
DNL
(N)
= [ V
(N+1)
-- V
(N)
] -- LSB
Figure 2. DNL Measurement
LSB
DNL
7
6
5
4
3
2
1
Output
Codes
Analog Input (Volt)
Figure 3. INL Error Calculation
Best Fit Line
EFS
EZS
LSB
Ideal Transfer Line
Real Transfer Line
INL
V
(N+1)
V
(N)
Figure 4. Equivalent Input Circuit
V
RT
+ V
RB
2
CLK
CLK
CLK
5pF
1.5pF
CLK
CLK
CLK
5pF
1.5pF
V
IN
[N--2]
AV
DD
V
IN
6 pF
Figure 5. Typical Circuit Connections
50
W
Analog
Input
0.1
m
F
0.1
m
F
0.1
m
F
+5 V
Clock
V
IN
V
DD
V
RTS
V
RT
V
RB
V
RBS
GND
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CLK
MP8775
10
m
F
Digital
Outputs
AGND
APPLICATION NOTES
Signals should not exceed AV
DD
+0.5V or go below AGND
--0.5V or DV
DD
+0.5 V or DGND --0.5 V. All pins have internal
protection diodes that will protect them from short transients
(<100
m
s) outside the supply range.
AGND and DGND pins are connected internally through the
P-- substrate. DC voltage differences between these pins will
cause undesirable internal substrate currents.
The power supply (AV
DD
) and reference voltage (V
RT
& V
RB
)
pins should be decoupled with 0.1
m
F and 10
m
F capacitors to
AGND, placed as close to the chip as possible.
The digital outputs should not drive long wires or buses. The
capacitive coupling and reflections will contribute noise to the
conversion.
It is possible for the data valid delay (t
DL
) to be equal to or
greater than the high pulse width of the sampling clock (t
PWH
),
See
Figure 1. This can cause timing related errors. For sample
rates above 14 MSPS use only the rising edge of the sample
clock (CLK) to latch data from the MP8775 to other parts of the
system.
The reference can be biased internally by shorting V
RT
to
V
RTS
and V
RB
to V
RBS
. This will generate 0.6 V at V
RB
and 2.6 V
at V
RT
(see
Figure 5.).
If the internal reference pins V
RTS
and/or V
RBS
are not used
they should be left unconnected.
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