MP8798

Rev. 3.00

FEATURES

10-Bit Resolution

4-Channel Mux

Sampling Rates from <1 kHz to 1 MHz

Very Low Power CMOS - 30 mW (typ)

Power Down; Lower Consumption 3 mW (typ)

Input Range between GND and V

No S/H Required for Analog Signals less than 100 kHz

No S/H Required for CCD Signals less than 1 MHz

Single Power Supply (4 to 6 Volts)

Latch-Up Free

High ESD Protection: 4000 Volts Minimum

3 V Version: MP87L98

CMOS

Very Low Power, 1 MSPS 10-Bit

Analog-to-Digital Converter with 4-Channel Mux

BENEFITS

Reduced Board Space (Small Package)

Reduced External Parts, No Sample/Hold Needed

Suitable for Battery & Power Critical Applications

Designer can Adapt Input Range & Scaling

APPLICATIONS

· µ

P/DSP Interface and Control Applications

High Resolution Imaging Scanners & Copiers

Wireless Digital Communications

Multiplexed Data Acquisition

GENERAL DESCRIPTION

The MP8798 is a flexible, easy to use, precision 10-bit

Analog-to-Digital Converter with 4-channel mux that operates
over a wide range of input and sampling conditions. The
MP8798 can operate with pulsed "on demand" conversion
operation or continuous "pipeline" operation for sampling rates
up to 1 MHz. The elimination of the S/H, requirements, very low
power, and small package size offer the designer a low cost
solution. No sample and hold is required for charge couple
device applications, up to 1 MHz, or multiplexed input
applications when the signal source bandwidth is limited to 100
kHz. The input architecture of the MP8798 allows direct
interface to any analog input range between AGND and AV

to 2 V, 1 to 4 V, 0 to 5 V, etc.). The user simply sets V

REF(+)

and

REF()

to encompass the desired input range.

Scaled reference resistor tap 1/2 R allows for customizing

the transfer curve as well as providing a 1/2 span reference
voltage. Digital outputs are CMOS and TTL compatible.

The MP8798 uses a two-step flash technique. The first

segment converts the 4 MSBs and consists of 15 autobalanced
comparators, latches, an encoder, and buffer storage registers.
The second segment converts the remaining 6 LSBs.

When the power down input is "high", the data outputs DB9 to

DB0 hold the current values and V

REF()

is disconnected from

REF1().

The power consumption during the power down mode

is approximately 3mW.

Specified for operation over the commercial / industrial (40

to +85

C) temperature range, the MP8798 is available in plastic

dual-in-line (PDIP), surface mount (SOIC), and shrink small
outline (SSOP) packages.

ORDERING INFORMATION

Package

Type

Temperature

Range

Part No.

DNL

(LSB)

INL

(LSB)

SOIC

40 to +85

MP8798AS

PDIP

40 to +85

MP8798AN

SSOP

40 to +85

MP8798AQ

MP8798

Rev. 3.00

SIMPLIFIED BLOCK AND TIMING DIAGRAM

OFW

DFF

CLK

Ladder

Fine

Com-

Adder

CLK

1/2 R

AGND DGND

Coarse

Comparators

OFW

Resolution

parators

N-1

REF(+)

REF1()

DB9-DB0

1 or 4

MUX

IN1

IN4

2 to 4

Decoder

IN2

IN3

REF()

Latch

PIN CONFIGURATIONS

See Packaging Section for
Package Dimensions

28 Pin SOIC (Jedec, 0.300") S28

28 Pin SSOP A28

DB2
DB1
DB0
PD

AGND

1/2 R

IN4

REF()

REF(+)

DGND

A1
A0

CLK
DB8

DB3
DB4
DB5
DB6
DB7

DB9

OFW

IN3

IN2

IN1

REF1()

DB2
DB1
DB0
PD

AGND

1/2 R

IN4

REF()

REF(+)

DGND

A1
A0

CLK
DB8

DB3
DB4
DB5
DB6
DB7

DB9

OFW

IN3

IN2

IN1

REF1()

28 Pin PDIP (0.300")

NN28

MP8798

Rev. 3.00

PIN OUT DEFINITIONS

DB3

Data Output Bit 3

DB4

Data Output Bit 4

DB5

Data Output Bit 5

DB6

Data Output Bit 6

DB7

Data Output Bit 7

DGND

Digital Ground

Digital V

Write (Active Low)

Address 1 Input

Address 0 Input

CLK

Clock Input

DB8

Data Output Bit 8

DB9

Data Output Bit 9 (MSB)

OFW

Overflow Output

PIN NO.

NAME

DESCRIPTION

REF(+)

Upper Reference Voltage

REF()

Lower Reference Voltage

REF1()

Lower Reference Voltage

1/2 R

Reference Ladder Tap

IN1

Analog Signal Input 1

IN2

Analog Signal Input 2

IN3

Analog Signal Input 3

IN4

Analog Signal Input 4

AGND

Analog Ground

Analog V

Power Down

DB0

Data Output Bit 0 (LSB)

DB1

Data Output Bit 1

DB2

Data Output Bit 2

PIN NO.

NAME

DESCRIPTION

TRUTH TABLE FOR INPUT CHANNEL SELECTION

IN1

IN2

IN3

IN4

Previous selection

SELECTED ANALOG INPUT

Note: WR, A1, A0 are internally connected to GND through
500k

resistance.

MP8798

Rev. 3.00

ELECTRICAL CHARACTERISTICS TABLE

Unless Otherwise Specified: AV

= DV

= 5 V, F

= 1 MHz (50% Duty Cycle),

REF(+)

= 4.6, V

REF()

= AGND, T

= 25

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions/Comments

KEY FEATURES

Resolution

Bits

Sampling Rate

.001

MHz

For Rated Performance

ACCURACY

Differential Non-Linearity

DNL

3/4

LSB

Integral Non-Linearity

INL

LSB

Best Fit Line
(Max INL Min INL)/2

Zero Scale Error

EZS

+0.50

LSB

Reference from V

REF(+)

to V

REF()

Full Scale Error

EFS

2.5

LSB

REFERENCE VOLTAGES

Positive Ref. Voltage

REF(+)

Negative Ref. Voltage

REF()

AGND

Differential Ref. Voltage

REF

0.5

Ladder Resistance

525

675

900

Ladder Temp. Coefficient

TCO

2000

ppm/

Ladder Switch Resistance

Ladder Switch Off Leakage

LKG-SW

ANALOG INPUT

Input Bandwidth

100

kHz

Input Voltage Range

REF()

REF(+)

Input Capacitance

Aperture Delay

DIGITAL INPUTS

Logical "1" Voltage

2.0

Logical "0" Voltage

0.8

Leakage Currents

=DGND to DV

CLK

100

PD, (Internal Res to DGND)

Input Capacitance

Clock Timing (

See NO TAG)

Clock Period

1000

Rise & Fall Time

, t

"High" Time

250

500,000

"Low" Time

150

500,000

MP8798

Rev. 3.00

ELECTRICAL CHARACTERISTICS TABLE (CONT'D)

Specifications are subject to change without notice

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions/Comments

DIGITAL OUTPUTS

OUT

=15 pF

Logical "1" Voltage

-0.5

LOAD

= 2 mA

Logical "0" Voltage

0.4

LOAD

= 4 mA

Tristate Leakage

OUT

= 0 to DV

Data Hold Time (

See NO TAG)

HLD

Data Valid Delay

Write Pulse Width

Multiplexer Address Setup Time

Multiplexer Address Hold Time

Delay from WR to Multiplexer

Enable

MUXEN1

Power Down Time

300

Power Up Time

200

POWER SUPPLIES

Power Down (I

)

PD-DD

0.6

1.2

Operating Voltage (AV

, DV

)

6.5

Current (AV

+ DV

)

= 2 V

NOTES:

Guaranteed. Not tested.

Tester measures code transition voltages by dithering the voltage of the analog input (V

). The difference between the measured

code width and the ideal value (V

REF

/1024) is the DNL error (

see NO TAG). The INL error is the maximum distance (in LSBs) from

the best fit line to any transition voltage (

See Figure 7.).

See V

input equivalent circuit (

see Figure 9.).

Clock specification to meet aperture specification (t

). Actual rise/fall time can be less stringent with no loss of accuracy.

Specified values guarantee functional device. Refer to other parameters for accuracy.

System can clock MP8798 with any duty cycle as long as all timing conditions are met.

Input range where input is converted correctly into binary code. Input voltage outside specified range converts to zero or full scale
output.

and AV

are connected through the silicon substrate. Connect together at the package.

ABSOLUTE MAXIMUM RATINGS (T

= +25

C unless otherwise noted)

1, 2

(to GND)

+7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REF(+)

& V

REF()

GND 0.5 to V

+0.5 V

. . . . . . . . . . . . . .

GND 0.5 to V

+0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . .

All Inputs

GND 0.5 to V

+0.5 V

. . . . . . . . . . . . . . . . . . . . .

All Outputs

GND 0.5 to V

+0.5 V

. . . . . . . . . . . . . . . . . . .

Storage Temperature

65 to +150

. . . . . . . . . . . . . . . . . . .

Lead Temperature (Soldering 10 seconds)

+300

. . . . . . .

Package Power Dissipation Rating to 75

SOIC, PDIP

1000mW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Derates above 75

14mW/

. . . . . . . . . . . . . . . . . . . . .

NOTES:

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

Any input pin which can see a value outside the absolute maximum ratings

should be protected by Schottky diode clamps

(HP5082-2835) from input pin to the supplies.

All inputs have protection diodes which will protect the device from short

transients outside the supplies of less than 100mA for less than 100

refers to AV

and DV

. GND refers to AGND and DGND.

MP8798

Rev. 3.00

AUTO
BALANCE

CLOCK

DATA

ANALOG
INPUT

SAMPLE
N1

Figure 1. MP8798 Timing Diagram

SAMPLE
N

SAMPLE
N+1

AUTO
BALANCE

N-1

HLD

THEORY OF OPERATION

Analog-to-Digital Conversion

The MP8798 converts analog voltages into 1024 digital

codes by encoding the outputs of 15 coarse and 67 fine compa-
rators. Digital logic is used to generate the overflow bit. The con-
version is synchronous with the clock and it is accomplished in 2
clock periods.

The reference resistance ladder is a series of 1025 resistors.

The first and the last resistor of the ladder are half the value of
the others so that the following relations apply:

REF

= 1024

R V

REF

= V

REF(+)

REF()

= 1024

LSB

The clock signal generates the two internal phases,

(CLK

high) and

(CLK low = sample) (

See Figure 2.). The rising

edge of the CLK input marks the end of the sampling phase (

Internal delay of the clock circuitry will delay the actual instant

when

disconnects the latches from the comparators. This de-

lay is called aperture delay (t

The coarse comparators make the first pass conversion and

selects a ladder range for the fine comparators. The fine compa-
rators are connected to the selected range during the next

phase.

Figure 2. MP8798 Comparators

Latch

Ref
Ladder

COARSE COMPARATOR

Latch

Selected
Range

FINE COMPARATOR

TAP

Sampling, Ladder Sampling, and Conversion Timing

Figure 3. shows this relationship as a timing chart. A

sam-

pling, ladder sampling and output data relationships are shown
for the general case where the levels which drive the ladder
need to change for each sampled A

time point. The ladder is

referenced for both last A

sample and next A

sample at the

same time. If the ladder's levels change by more than 1 LSB,
one of the samples must be discarded. Also note that the clock
low period for the discarded A

can be reduced to the minimum

time of 150 ns.

Figure 3. A

Sampling, Ladder Sampling & Conversion Timing

Settle by Clock Update Time

Reference Stable Time For Sample A

Sample A

Reference Stable Time For Sample A

Hold Reference Value Past
Clock Change for t

Time

Short Cycle Sample will be discarded

Sample A

Not Used

Sample A

Sample Ladder

for A

Sample Ladder

for A

Sample Ladder

for A

Sample Ladder

for A

Compare Ladder

V/S A

Compare Ladder

V/S A

Compare Ladder

V/S A

Compare Ladder

V/S A

DATA A

Not Used

DATA

Ladder Compare

(LSB Bank)

Ladder Sample

Window (MSB Bank)

Sample

Window

Clock

Update

References

External

Internal

External

MP8798

Rev. 3.00

Accuracy of Conversion: DNL and INL

The transfer function for an ideal A/D converter is shown in

Figure 4.

Figure 4. Ideal A/D Transfer Function

3FF

3FE

3FD

REF()

REF(+)

DIGITAL

CODES

000

002

LSB

OFW = 0

0.5

LSB

0.5

LSB

001

OFW = 1

1 LSB

V001

V002

3FE

3FF

0FW

The overflow transition (V

OFW

) takes place at:

= V

OFW

= V

REF(+)

0.5

LSB

The first and the last transitions for the data bits take place at:

= V001 = V

REF()

+ 0.5

LSB

= V

3FF

= V

REF(+)

1.5

LSB

LSB = V

REF

/ 1024 = (V

3FF

V001) / 1022

Note that the overflow transition is a flag and has no impact on

the data bits.

In a "real" converter the code-to-code transitions don't fall

exactly every V

REF

/1024 volts.

A positive DNL (Differential Non-Linearity) error means that

the real width of a particular code is larger than 1 LSB. This error
is measured in fractions of LSBs.

A Max DNL specification guarantees that ALL code widths

(DNL errors) are within the stated value. A specification of Max
DNL = + 0.5 LSB means that all code widths are within 0.5 and
1.5 LSB. If V

REF

= 4.608 V then 1 LSB = 4.5 mV and every code

width is within 2.25 and 6.75 mV.

N + 1

N 1

Output
Codes

Analog
Input

(N+1) Code Width = V

(N+1)

(N)

LSB = [ V

REF(+)

REF()

] / 1024

DNL

(N)

= [ V

(N+1)

 V

(N)

] LSB

Figure 5. DNL Measurement

On Production Tester

LSB

DNL

(N+1)

(N)

The formulas for Differential Non-linearity (DNL), Integral

Non-Linearity (INL) and zero and full scale errors (E

, E

) are:

DNL (001) = V002 V001 LSB

: : :

DNL (3FE) = V

3FF

3FE

LSB

(full scale error) = V

3FF

REF(+)

1.5

LSB]

(zero scale error) = V

001

REF()

+ 0.5

LSB]

Figure 6. Real A/D Transfer Curve

DIGITAL

CODES

0.5

LSB

000

001

002

3FE

3FF

1.5

LSB

V001

V002

3FE

3FF

REF()

REF(+)

Figure 6. shows the zero scale and full scale error terms.

MP8798

Rev. 3.00

Figure 7. gives a visual definition of the INL error. The chart

shows a 3-bit converter transfer curve with greatly exaggerated
DNL errors to show the deviation of the real transfer curve from
the ideal one.

After a tester has measured all the transition voltages, the

computer draws a line parallel to the ideal transfer line. By defi-
nition the best fit line makes equal the positive and the negative
INL errors. For example, an INL error of 1 to +2 LSB's relative
to the Ideal Line would be +1.5 LSB's relative to the best fit line.

Figure 7. INL Error Calculation

Output
Codes

Analog Input (Volt)

Best Fit Line

EFS

EZS

LSB

Ideal Transfer Line

Real Transfer Line

INL

Clock and Conversion Timing

A system will clock the MP8798 continuously or it will give

clock pulses intermittently when a conversion is desired. The
timing of

Figure 8a shows normal operation, while the timing of

Figure 8b keeps the MP8798 in balance and ready to sample the
analog input.

Figure 8. Relationship of Data to Clock

CLOCK

DATA

b. Single sampling

BALANCE

CLOCK

DATA

a. Continuous sampling

N+1

Analog Input

The MP8798 has very flexible input range characteristics.

The user may set V

REF(+)

and V

REF()

to two fixed voltages and

then vary the input DC and AC levels to match the V

REF

range.

Another method is to first design the analog input circuitry and
then adjust the reference voltages for the analog input range.
One advantage is that this approach may eliminate the need for
external gain and offset adjust circuitry which may be required
by fixed input range A/Ds.

The MP8798's performance is optimized by using analog in-

put circuitry that is capable of driving the A

input.

Figure 9.

shows the equivalent circuit for A

300

15 pF

Figure 9. Analog Input Equivalent Circuit

60 pF

87 pF

160

1 pF

10 pF

Channel

Selection

Control

R Series

R MUX

500

87 pF

1/2 [ V

REF(+)

+ V

REF()

]

4 pF

MP8798

Rev. 3.00

Analog Input Multiplexer

The MP8798 includes a 4-channel analog input multiplexer.

The relationship between the clock, the multiplexer address, the
WR and the output data is shown in

Figure 10.

Clock

DB0-DB9

ÉÉÉÉÉÉÉÉÉÉ

ÉÉ

CLKS2

CLKH2

Address

Sample N

Old Address

Sample M

New Address

Sample

M+1

N-2 Valid

N-1 Valid

Old Address

N Valid

Old Address

M Valid

New Address

Figure 10. MUX Address Timing

CLKS2

= t

CLKH2

= 0

A1, A0

MUXEN

(Internal Signal)

MUXEN1

Figure 11. Analog MUX Timing

Reference Voltages

The input/output relationship is a function of V

REF

= V

REF()

REF

= V

REF(+)

REF()

DATA = 1023

REF

)

A system can increase total gain by reducing V

REF

Digital Interfaces

The logic encodes the outputs of the comparators into a bi-

nary code and latches the data in a D-type flip-flop for output.

The functional equivalent of the MP8798 (

Figure 12.) is com-

posed of:

Delay stage (t

) from the clock to the sampling phase

(

An ideal analog switch which samples V

An ideal A/D which tracks and converts V

with no

delay.

A series of two DFF's with specified hold (t

HLD

) and

delay (t

) times.

, t

HLD

and t

are specified in the Electrical Characteristics

table.

Figure 12. MP8798 Functional Equivalent

Circuit and Interface Timing

A/D

MP8798

CLK

DB9-DB0

N+1

N-1

HLD

D Q

DB9-DB0

CLK

MP8798

Rev. 3.00

APPLICATION NOTES

Figure 14. Typical Circuit Connections

OFW

CLK

DB9 - DB0

AGND

DGND

(Substrate)

MP8798

IN1

REF(+)

REF()

1/2 R

Buffer

1D,

1A,

= 4.7 or 10

F Tantalum

= 0.1

F Chip Cap or low inductance capacitor

= Clock Transmission Line Termination

Reference

Voltage

Source

REF1()

+5 V

1 of 4

IN4

100

Resistive

Isolation of

50 to 100

The following information will be useful in maximizing the per-

formance of the MP8798.

1. All signals should not exceed AV

+0.5 V or AGND 0.5 V

or DV

+0.5 V or DGND 0.5 V.

2. Any input pin which can see a value outside the absolute

maximum ratings (AV

or DV

+0.5 V or AGND 0.5 V)

should be protected by diode clamps (HP5082-2835) from
input pin to the supplies. All MP8798 inputs have input pro-
tection diodes which will protect the device from short tran-
sients outside the supply ranges.

3. The design of a PC board will affect the accuracy of MP8798.

Use of wire wrap is not recommended.

4. The analog input signal (V

) is quite sensitive and should be

properly routed and terminated. It should be shielded from
the clock and digital outputs so as to minimize cross coupling
and noise pickup.

5. The analog input should be driven by a low impedance (less

than 50

6. Analog and digital ground planes should be substantial and

common at one point only. The ground plane should act as a

shield for parasitics and not a return path for signals. To re-
duce noise levels, use separate low impedance ground
paths.

DGND should not be shared with other digital cir-

cuitry. If separate low impedance paths cannot be provided,
DGND should be connected to AGND next to the MP8798.

should not be shared with other digital circuitry to

avoid conversion errors caused by digital supply transients.
DV

for the MP8798 should be connected to AV

next to

the MP8798.

8. DV

and AV

are connected inside the MP8798 through

the N doped silicon substrate. Any DC voltage difference
between DV

and AV

will cause undesirable internal

currents.

9. Each power supply and reference voltage pin should be

decoupled with a ceramic (0.1

F) and a tantalum (10

F) ca-

pacitor as close to the device as possible.

10. The digital output should not drive long wires. The capacitive

coupling and reflection will contribute noise to the conver-
sion. When driving distant loads, buffers should be used.
100

resistors in series with the digital outputs in some ap-

plications reduces the digital output disruption of A

MP8798

Rev. 3.00

Figure 15. Example of a Reference Voltage Source

0.1

MP5010

+5 V

5 k

100k

Figure 16.

5 V Analog Input

REF(+)

IN1

REF()

5 V

+5 V

DB0

AGND

For R = 5k use Beckman Instruments #694-3-R10k resistor array or equivalent.

NOTE: High R values affect the input BW of ADC due to the (R

of ADC) time constant. Therefore, for different

applications the R value needs to be selected as a tradeoff between A

settling time and power dissipation.

1 of 4

IN4

Figure 17.

10 V Analog Input

REF(+)

IN1

REF()

10 V

+5 V

DB0

For R = 5k use Beckman Instruments #694-3-R10k resistor array or equivalent.

NOTE: High R values affect the input BW of ADC due to the (R

of ADC) time constant. Therefore, for different

applications the R value needs to be selected as a tradeoff between A

settling time and power dissipation.

1 of 4

IN4

AGND

MP8798

Rev. 3.00

28 LEAD PLASTIC DUAL-IN-LINE

(300 MIL PDIP)

NN28

SYMBOL

MIN

MAX

MIN

MAX

INCHES

0.130

0.230

3.30

5.84

0.015

0.381

0.014

0.023

0.356

0.584

(1)

0.038

0.065

0.965

1.65

0.008

0.015

0.203

0.381

1.340

1.485

34.04

37.72

0.290

0.325

7.37

8.26

0.240

0.310

6.10

7.87

0.100 BSC

2.54 BSC

0.115

0.150

2.92

3.81

0.055

0.070

1.40

1.78

0.020

0.100

0.508

2.54

MILLIMETERS

Note:

(1)

The minimum limit for dimensions B1 may be 0.023"
(0.58 mm) for all four corner leads only.

Seating

Plane

MP8798

Rev. 3.00

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary
depending upon a user's specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.

Copyright 1993 EXAR Corporation
Datasheet April 1995
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

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