EXAR Corporation, 48720 Kato Road, Fremont, CA 94538

(510) 668-7000

FAX (510) 668-7017

ST16C1450/51

PLCC Package

UNIVERSAL ASYNCHRONOUS RECEIVER/

TRANSMITTER ( UART)

DESCRIPTION

The ST16C1450, ST16C1451 series (here on denoted as the 145X) is a universal asynchronous receiver and

transmitter (UART). The 145X is foot print compatible to the SSI 73M1550 and SSI 73M2550 UART with one byte

FIFO and higher operating speed and lower access time. The 145X provides enhanced UART functions with a

modem control interface, independent programmable baud rate generators with clock rates to 1.5 Mbps. Onboard

status registers provide the user with error indications and operational status. System interrupts and modem

control features may be tailored by external software to meet specific user requirements. An internal loop-back

capability allows onboard diagnostics. The 145X is available in a 28-pin PLCC/plastic-DIP, 48-pin TQFP

packages. The Baud rate generator can be configured for either crystal or external clock input with the exception

of the 28 pin 1451 package. An external clock must be provided for the 28 pin 1451 package. Each package type,

with the exception of the 28 pin 1450, provides a buffered reset output that can be controlled through user software.

The 145X is fabricated in an advanced CMOS process to achieve low drain power and high speed requirements.

FEATURES

Pin compatible to SSI 73M1550/2550/Software

compatible INS8250, NS16450

1.5 Mbps transmit/receive operation (24MHz

Max.) with programmable clock control

Modem control signals (-CTS, -RTS, -DSR, -DTR,

-RI, -CD).

Programmable character lengths (5, 6, 7, 8) with

Even, odd, or no parity.

Four levels of prioritized interrupts, minimize ex-

ternal software interaction

Software controlled tri-state interrupt outputs

Provides enhanced 16C450 features for power

down and software controllable reset output

Crystal or external clock input (except 28 pin

ST16C1451)

460.8 Kbps transmit/receive operation with 7.3728

MHz crystal or external clock source

ORDERING INFORMATION

Part number

Pin Package

Operating temperature

ST16C1450CP28 28 PDIP

0° C to + 70° C

ST16C1450CJ28 28 PLCC

0° C to + 70° C

ST16C1450CQ48 48 TQFP

0° C to + 70° C

ST16C1451CP28 28 PDip

0° C to + 70° C

ST16C1451CJ28 28 PLCC

0° C to + 70° C

ST16C1451CQ48 48 TQFP

0° C to + 70° C

Part number

Pin Package

Operating temperature

ST16C1450IP28

28 PDIP

-40° C to + 85° C

ST16C1450IJ28

28 PLCC

-40° C to + 85° C

ST16C1450IQ48 48 TQFP

-40° C to + 85° C

ST16C1451IP28

28 PDip

-40° C to + 85° C

ST16C1451IJ28

28 PLCC

-40° C to + 85° C

ST16C1451IQ48 48 TQFP

-40° C to + 85° C

-CS

-CTS

RESET

-DTR

-RTS

-CD

-DS

-IOW

-IOR

-RI

ST16C1450CJ28

Rev. 3.10

ST16C1450/51

Rev. 3.10

48 Pin TQFP Package

28 Pin Package DIP

Figure 1, Package Descriptions, 28 pin, 48 pin ST16C1450/51

28 Pin PLCC Package

-CS

XTAL1

XTAL2

-IOW

VCC

-CD

-DSR

-CTS

RESET

-DTR

-RTS

INT

-RI

-IOR

GND

T
16

C145

2
8

-CS

-CTS

-RESET

-DTR

-RTS

-CD

-DS

-I
O

GND

-I
O

-RI

ST16C1451CJ28

N.C.

-CS

N.C.

-CTS

RESET

-DTR

-RTS

N.C.

-C

-D

A
L
1

A
L
2

-I
O

-R

INT

ST16C145XCQ48

-CS

CLK

-IOW

GND

VCC

-CD

-DSR

-CTS

RESET

-DTR

-RTS

INT

RST

-RI

-IOR

T
16

C145

2
8

ST16C1450/51

Rev. 3.10

SYMBOL DESCRIPTION

Symbol

Signal

Pin Description

type

Address-0 Select Bit. - Internal register address selection.

Address-1 Select Bit. - Internal register address selection.

Address-2 Select Bit. - Internal register address selection.

CLK

Clock Input. - This function is associated with 28 pin

ST16C1451CJ28 package only. An external clock must be

connected to this pin to clock the baud rate generator and

internal circuitry (see Programmable Baud Rate Genera-

tor).

-CS

Chip Select (active low) - A logic 0 on this pin selects the

UART I/O for external access. Data can be transferred

between the user CPU and the 145X or the 145X and the

CPU.

D0-D7

1-8

43,

45-47,

3-6

I/O

Data Bus (Bi-directional) - These pins are the eight bit, tri-

state data bus for transferring information to or from the

controlling CPU. D0 is the least significant bit and the first

data bit in a transmit or receive serial data stream.

GND

Pwr

Signal and power ground.

INT

Interrupt (three state, active high) - This function is associ-

ated with UART channel interrupts (INT). INT is enabled

when MCR bit-3 is set to a logic 1, interrupts are enabled in

the interrupt enable register (IER), and when an interrupt

condition exists. Interrupt conditions include: receiver er-

rors, available receiver buffer data, transmit buffer empty,

or when a modem status flag is detected.

-IOR

Read strobe. (active low strobe) - A logic 0 transition on this

pin will load the contents of an Internal register defined by

address bits A0-A2 onto the 145X data bus (D0-D7) for

access by an external CPU.

-IOW

Write strobe. (active low strobe) - A logic 0 transition on this

ST16C1450/51

Rev. 3.10

SYMBOL DESCRIPTION

Symbol

Signal

Pin Description

type

pin will transfer the contents of the data bus (D0-D7) from

the external CPU to an internal register that is defined by

address bits A0-A2.

RESET

Reset. (active high) - A logic 1 on this pin will reset the

internal registers and all the outputs (Also see signal RST).

The UART transmitter output and the receiver input will be

disabled during reset time. (See 145X External Reset

Conditions for initialization details.)

RST

Reset output (active high). This function is associated with

the 28 pin ST16C1451 and the 48 pin ST16C1450/51

packages only. This function provides a buffered RESET

output that operates in two modes. The modes are config-

ured by IER bit-5. When IER bit-5 is a logic 0, the standard

reset mode is selected and RST will follow the logical state

of the RESET pin (see RESET). When IER bit-5 is a logic

1, the special mode is selected. During special mode

operation, the user may send software (SOFT) resets via

MCR bit-2. This is useful when the user desires the capabil-

ity of resetting an externally connected device only. During

special mode operation, soft resets from MCR bit 2 are

ORd with the state of the input pin, RESET. Therefore

both reset types will be seen at the RST pin.

VCC

Pwr

Power supply input.

XTAL1

Crystal or External Clock Input - This function is associated

with all packages types except the 28 pin ST16C1451,

which must have external clock (see CLK). Functions as a

crystal input or as an external clock input. A crystal can be

connected between this pin and XTAL2 to form an internal

oscillator circuit. This configuration requires an external 1

resistor between the XTAL1 and XTAL2 pins. Alterna-

tively, an external clock can be connected to this pin to

provide custom data rates (see Baud Rate Generator

Programming).

XTAL2

Output of the Crystal Oscillator or Buffered Clock - (See also

XTAL1). - This function is associated with all packages

ST16C1450/51

Rev. 3.10

types except the 28 pin ST16C1451. The crystal oscillator

output or buffered clock output should be left open if an

external clock is connected to XTAL1.

-CD

Carrier Detect (active low) - A logic 0 on this pin indicates

that a carrier has been detected by the modem.

-CTS

Clear to Send (active low) - A logic 0 on the -CTS pin

indicates the modem or data set is ready to accept transmit

data from the 145X. Status can be tested by reading MSR

bit-4. This pin has no effect on the UARTs transmit or

receive operation.

-DSR

Data Set Ready (active low) - A logic 0 on this pin indicates

the modem or data set is powered-on and is ready for data

exchange with the UART. This pin has no effect on the

UARTs transmit or receive operation.

-DTR

Data Terminal Ready (active low) - A logic 0 on this pin

indicates that the 145X is powered-on and ready. This pin

can be controlled via the modem control register. Writing a

logic 1 to MCR bit-0 will set the -DTR output to logic 0,

enabling the modem. This pin will be a logic 1 after writing

a logic 0 to MCR bit-0, or after a reset. This pin has no effect

on the UARTs transmit or receive operation.

-RI

Ring Indicator (active low) - A logic 0 on this pin indicates the

modem has received a ringing signal from the telephone

line. A logic 1 transition on this input pin will generate an

interrupt.

-RTS

Request to Send (active low) - A logic 0 on the -RTS pin

indicates the transmitter has data ready and waiting to send.

Writing a logic 1 in the modem control register (MCR bit-1)

will set this pin to a logic 0 indicating data is available. After

a reset this pin will be set to a logic 1. This pin has no effect

on the UARTs transmit or receive operation.

Receive Data - This input is associated with individual serial

channel data to the 145X receive input circuit. The RX signal

SYMBOL DESCRIPTION

Symbol

Signal

Pin Description

type

ST16C1450/51

Rev. 3.10

Symbol

Signal

Pin Description

type

will be a logic 1 during reset, idle (no data), or when the

transmitter is disabled. During the local loop-back mode,

the RX input pin is disabled and TX data is connected to the

UART RX Input, internally.

Transmit Data (A-B) - This output is associated with indi-

vidual serial transmit channel data from the 145X. The TX

signal will be a logic 1 during reset, idle (no data), or when

the transmitter is disabled. During the local loop-back

mode, the TX output pin is disabled and TX data is internally

connected to the UART RX Input.

All unused input pins should be tied to VCC or GND.

SYMBOL DESCRIPTION

ST16C1450/51

Rev. 3.10

GENERAL DESCRIPTION

The 145X provides serial asynchronous receive data

synchronization, parallel-to-serial and serial-to-paral-

lel data conversions for both the transmitter and

receiver sections. These functions are necessary for

converting the serial data stream into parallel data that

is required with digital data systems. Synchronization

for the serial data stream is accomplished by adding

start and stops bits to the transmit data to form a data

character (character orientated protocol). Data integ-

rity is insured by attaching a parity bit to the data

character. The parity bit is checked by the receiver for

any transmission bit errors. The electronic circuitry to

provide all these functions is fairly complex especially

when manufactured on a single integrated silicon

chip. The 145X represents such an integration with

greatly enhanced features. The 145X is fabricated

with an advanced CMOS process.

The 145X is an upward solution that is designed to

work with high speed modems and shared network

environments, that require fast data processing time.

Increased performance is realized in the 145X by

providing higher operating speed and lower access

time. This allows the external processor to handle

more networking tasks within a given time. The im-

proved performance reduces the bandwidth require-

ment for the external controlling CPU, increasing

performance, and reducing power consumption.

The 145X is capable of operation to 1.5Mbps with a 24

MHz clock input. With a crystal or external clock input

of 7.3728 MHz the user can select data rates up to

460.8 Kbps. Internal crystal clock operation is not

available on the 28 pin ST16C1451.

The rich feature set of the 145X is available through

internal registers. Selectable TX and RX baud rates,

and modem interface controls are all standard fea-

tures. Following a power on reset or an external reset,

the 145X is software compatible with the, ST16C450.

FUNCTIONAL DESCRIPTIONS

UART Functions

The UART provides the user with the capability to Bi-

directionally transfer information between an external

CPU, the 145X package, and an external serial de-

vice. A logic 0 on the chip select pin -CS allows the

user to configure, send data, and/or receive data via

the UART.

Internal Registers

The 145X provides 11 internal registers for monitoring

and control of the UART functions. These resisters are

shown in Table 3 below. The UART registers function

as data holding registers (THR/RHR), interrupt status

and control registers (IER/ISR), line status and control

registers (LCR/LSR), modem status and control reg-

isters (MCR/MSR), programmable data rate (clock)

control registers (DLL/DLM), and a user assessable

scratchpad register (SPR).

ST16C1450/51

Rev. 3.10

Table 3, INTERNAL REGISTER DECODE

READ MODE

WRITE MODE

General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): Note 1*

Receive Holding Register

Transmit Holding Register

Interrupt Enable Register

Interrupt Status Register

Line Control Register

Modem Control Register

Line Status Register

Modem Status Register

Scratchpad Register

Baud Rate Register Set (DLL/DLM): Note *2

LSB of Divisor Latch

MSB of Divisor Latch

Note 1* The General Register set is accessible only when CS is a logic 0.

Note 2* The Baud Rate register set is accessible only when CS is a logic 0 and LCR bit-7 is a logic 1.

Programmable Baud Rate Generator

The 145X supports high speed modem technologies

that have increased input data rates by employing

data compression schemes. For example a 33.6Kbps

modem that employs data compression may require a

115.2Kbps input data rate. A 128.0Kbps ISDN modem

that supports data compression may need an input

data rate of 460.8Kbps.

A single baud rate generator is provided for both the

transmitter and receiver. The programmable Baud

Rate Generator is capable of accepting an input clock

up to 24 MHz, as required for supporting a 1.5Mbps

data rate. The 145X can be configured for internal

clock (XTAL) operation on all packages except the 28

pin ST16C1451. The 28 pin ST16C1451 requires an

external clock input and this device can not be config-

ured for internal (XTAL) operation. For internal (XTAL)

clock oscillator operation, an industry standard micro-

processor crystal (parallel resonant/ 22-33 pF load) is

connected externally between the XTAL1 and XTAL2

pins, with an external 1 M

resistor across it. Alterna-

tively, an external clock can be connected to the

XTAL1 pin to clock the internal baud rate generator for

standard or custom rates. (see Baud Rate Generator

Programming).

The generator divides the input 16X clock by any

divisor from 1 to 2

-1. The 145X divides the basic

external clock by 16. The basic 16X clock provides

data rates to support standard and custom applica-

tions using the same system design. The data rate is

configured via the DLL and DLM internal register

functions. Customized Baud Rates can be achieved

by selecting the proper divisor values for the MSB and

LSB sections of baud rate generator.

Programming the Baud Rate Generator Registers

DLM (MSB) and DLL (LSB) provides a user capability

for selecting the desired final baud rate. The example

in Table 4 below, shows the selectable baud rates

available when using a 1.8432 MHz external clock

input.

ST16C1450/51

Rev. 3.10

Table 4, BAUD RATE GENERATOR PROGRAMMING TABLE (1.8432 MHz CLOCK):

Output

User

DLM

DLL

Baud Rate

16 x Clock

Program

Divisor

Value

(Decimal)

(HEX)

2304

900

1536

600

110

1047

417

150

768

300

384

180

600

192

1200

2400

3600

4800

7200

9600

19.2k

38.4k

57.6k

115.2k

Crystal oscillator connection

22pF

33pF

1.8432 MHz

50-120

R2
1M

XTA

ST16C1450/51

Rev. 3.10

Special (Enhanced Feature) Mode

The 145X supports the standard features of the

ST16C450. In addition the 145X supports two en-

hanced features not available on the ST16C450 pack-

age. These features are enabled by bit-5 of the IER

reset and a power down feature. The power down

feature (controlled by MCR bit-7) provides the user

with the capability to conserve power when the pack-

age is not in actual use with out destroying internal

around from power down to returned package opera-

tion. Each package type, with the exception of the 28

pin 1450, provides a buffered reset output that can be

controlled through user software. When enabled by

the IER register, MCR bit-7 can be used to power down

the 145X and/or MCR bit-2 can be used to initiate a

SOFT reset at the RST output pin. Soft resets are

useful when the user desires the capability of resetting

an externally connected device only. During special

mode operation, soft resets from MCR bit 2 are ORd

with resets on the input pin, RESET. Therefore both

reset types will be seen at the RST pin.

Loop-back Mode

The internal loop-back capability allows onboard diag-

nostics. In the loop-back mode the normal modem

interface pins are disconnected and reconfigured for

loop-back internally. MCR register bits 0-3 are used

for controlling loop-back diagnostic testing. In the

loop-back mode INT enable and MCR bit-2 in the MCR

inputs respectively. MCR signals -DTR and -RTS (bits

0-1) are used to control the modem -CTS and -DSR

inputs respectively. The transmitter output (TX) and

the receiver input (RX) are disconnected from their

associated interface pins, and instead are connected

together internally (See Figure 4). The -CTS, -DSR, -

CD, and -RI are disconnected from their normal

modem control inputs pins, and instead are connected

internally to -DTR, -RTS, INT enable and MCR bit-2.

Loop-back test data is entered into the transmit hold-

ing register via the user data bus interface, D0-D7.

The transmit UART serializes the data and passes the

serial data to the receive UART via the internal loop-

back connection. The receive UART converts the

serial data back into parallel data that is then made

available at the user data interface, D0-D7. The user

optionally compares the received data to the initial

transmitted data for verifying error free operation of

the UART TX/RX circuits.

In this mode, the receiver and transmitter interrupts

are fully operational. The Modem Control Interrupts

are also operational. However, the interrupts can only

be read using lower four bits of the Modem Control

Status Register bits 4-7. The interrupts are still con-

trolled by the IER.

ST16C1450/51

Rev. 3.10

The following table delineates the assigned bit functions for the twelve 145X internal registers. The assigned bit

functions are more fully defined in the following paragraphs.

Table 5, ST16C145X INTERNAL REGISTERS

A2 A1 A0

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

[Default]

Note 3*

General Register Set: Note 1*

0 0 0

RHR [XX]

bit-7

bit-6

bit-5

bit-4

bit-3

bit-2

bit-1

bit-0

0 0 0

THR [XX]

bit-7

bit-6

bit-5

bit-4

bit-3

bit-2

bit-1

bit-0

0 0 1

IER [00]

Special

Modem

Receive

Transmit

Receive

Mode

Status

Line

Holding

Enable

Interrupt

Status

interrupt

0 1 0

ISR [01]

INT

priority

status

bit-2

bit-1

bit-0

0 1 1

LCR [00]

divisor

set

even

parity

stop

word

latch

break

parity

enable

bits

length

enable

bit-1

bit-0

1 0 0

MCR [00]

Power

loop

INT

SOFT

-RTS

-DTR

Down

back

enable

Reset

1 0 1

LSR [60]

THR &

THR.

break

framing

parity

overrun

receive

TSR

empty

interrupt

error

data

empty

ready

1 1 0

MSR [X0]

DSR

CTS

delta

-CD

-RI

-DSR

-CTS

1 1 1

SPR [FF]

bit-7

bit-6

bit-5

bit-4

bit-3

bit-2

bit-1

bit-0

Special Register Set: Note *2

0 0 0

DLL [XX]

bit-7

bit-6

bit-5

bit-4

bit-3

bit-2

bit-1

bit-0

0 0 1

DLM [XX]

bit-15

bit-14

bit-13

bit-12

bit-11

bit-10

bit-9

bit-8

Note 1* The General Register set is accessible only when CS is a logic 0.

Note 2* The Baud Rate register set is accessible only when CS is a logic 0 and LCR bit-7 is a logic 1.

Note 3*

The value between the square brackets represents the registers initialized HEX value, X = N/A.

ST16C1450/51

Rev. 3.10

Transmit (THR) and Receive (RHR) Holding Reg-

isters

The serial transmitter section consists of an 8-bit

Transmit Hold Register (THR) and Transmit Shift

the Line Status Register (LSR). Writing to the THR

transfers the contents of the data bus (D7-D0) to the

TSR and UART via the THR, providing that the THR

is empty. The THR empty flag in the LSR register will

be set to a logic 1 when the transmitter is empty or

when data is transferred to the TSR. Note that a write

operation can be performed when the transmit holding

The serial receive section also contains an 8-bit

Receive Holding Register, RHR and a Receive Serial

Shift Register (RSR). Receive data is removed from

the 145X by reading the RHR register. The receive

section provides a mechanism to prevent false starts.

On the falling edge of a start or false start bit, an

internal receiver counter starts counting clocks at the

16x clock rate. After 7 1/2 clocks the start bit time

should be shifted to the center of the start bit. At this

time the start bit is sampled and if it is still a logic 0 it

is validated. Evaluating the start bit in this manner

prevents the receiver from assembling a false charac-

ter. Receiver status codes will be posted in the LSR.

Interrupt Enable Register (IER)

The interrupt Enable Register (IER) masks the inter-

rupts from receiver ready, transmitter empty, line

status and modem status registers. These interrupts

would normally be activated at the INT output pin.

IER BIT-0:

This interrupt will be issued when the RHR has data or

is cleared when the RHR is empty.

Logic 0 = Disable the receiver ready interrupt. (normal

default condition)

Logic 1 = Enable the RXRDY interrupt.

IER BIT-1:

This interrupt will be issued whenever the THR is

empty and is associated with bit-5 in the LSR register.

This interrupt will be issued whenever the THR is

empty

Logic 0 = Disable the Transmit Holding Register

Empty (TXRDY) interrupt. (normal default condition)

Logic 1 = Enable the TXRDY interrupt.

IER BIT-2:

This interrupt will be issued whenever an receive data

error condition exists as reflected in LSR bits 1-4.

Logic 0 = Disable the receiver line status interrupt.

(normal default condition)

Logic 1 = Enable the receiver line status interrupt.

IER BIT-3:

This interrupt will be issued whenever there is a

modem status change as reflected in MSR bits 0-3.

Logic 0 = Disable the modem status register interrupt.

(normal default condition)

Logic 1 = Enable the modem status register interrupt.

IER BIT 4-:

Not Used - initialized to a logic 0.

IER BIT 5:

This bit is used to enable the enhanced features of the

145X. Enhanced features include SOFT reset func-

tion, and the power down function. When enabled

(IER bit-5 = a logic 1), a logic 1 at MCR bit will power

down the 145X, the logical state of MCR bit-2 will be

reflected at the RST output pin.

Logic 0 = enable basic ST16C450 functions only.

(normal default condition).

Logic 1 = enable special mode functions in addition to

basic ST16C450 functions, MCR bit-2 (soft reset) and

MCR bit-7 (power down) functions.

IER BIT 6-7-:

Not Used - initialized to a logic 0.

ST16C1450/51

Rev. 3.10

Table 6, INTERRUPT SOURCE TABLE

Priority

[ ISR BITS ]

Level

Bit-3 Bit-2 Bit-1 Bit-0

Source of the interrupt

LSR (Receiver Line Status Register)

RXRDY (Received Data Ready)

TXRDY (Transmitter Holding Register Empty)

MSR (Modem Status Register)

ISR BIT-0:

Logic 0 = An interrupt is pending and the ISR contents

may be used as a pointer to the appropriate interrupt

service routine.

Logic 1 = No interrupt pending. (normal default condi-

tion)

ISR BIT 1-3: (logic 0 or cleared is the default condition)

These bits indicate the source for a pending interrupt

at interrupt priority levels 1, 2, 3, and 4 (See Interrupt

Source Table).

ISR BIT 4-7: (logic 0 or cleared is the default condition)

Not Used - initialized to a logic 0.

Line Control Register (LCR)

The Line Control Register is used to specify the

asynchronous data communication format. The word

length, the number of stop bits, and the parity are

selected by writing the appropriate bits in this register.

LCR BIT 0-1: (logic 0 or cleared is the default condi-

tion)

These two bits specify the word length to be transmit-

ted or received.

BIT-1

BIT-0

Word length

LCR BIT-2: (logic 0 or cleared is the default condition)

The length of stop bit is specified by this bit in

conjunction with the programmed word length.

BIT-2

Word length

Stop bit

length

(Bit time(s))

5,6,7,8

1-1/2

6,7,8

LCR BIT-3:

Parity or no parity can be selected via this bit.

Logic 0 = No parity. (normal default condition)

Logic 1 = A parity bit is generated during the transmis-

sion, receiver checks the data and parity for transmis-

sion errors.

LCR BIT-4:

If the parity bit is enabled with LCR bit-3 set to a logic

1, LCR BIT-4 selects the even or odd parity format.

ST16C1450/51

Rev. 3.10

Logic 0 = ODD Parity is generated by forcing an odd

number of logic 1s in the transmitted data. The

receiver must be programmed to check the same

format. (normal default condition)

Logic 1 = EVEN Parity is generated by forcing an even

the number of logic 1s in the transmitted. The receiver

must be programmed to check the same format.

LCR BIT-5:

If the parity bit is enabled, LCR BIT-5 selects the

forced parity format.

LCR BIT-5 = logic 0, parity is not forced. (normal

default condition)

LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit

is forced to a logical 1 for the transmit and receive

data.

LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit

is forced to a logical 0 for the transmit and receive

data.

LCR

Parity selection

Bit-5

Bit-4

Bit-3

No parity

Odd parity

Even parity

Force parity 1

Forced parity 0

LCR BIT-6:

When enabled, the Break control bit causes a break

condition to be transmitted (the TX output is forced to

a logic 0 state). This condition exists until disabled by

setting LCR bit-6 to a logic 0.

Logic 0 = No TX break condition. (normal default

condition)

Logic 1 = Forces the transmitter output (TX) to a logic

0 for alerting the remote receiver to a line break

condition.

LCR BIT-7:

The internal baud rate counter latch and Enhance

Feature mode enable.

Logic 0 = Divisor latch disabled. (normal default

condition)

Logic 1 = Divisor latch and enhanced feature register

enabled.

Modem Control Register (MCR)

This register controls the interface with the modem or

a peripheral device.

MCR BIT-0:

Logic 0 = Force -DTR output to a logic 1. (normal

default condition)

Logic 1 = Force -DTR output to a logic 0.

MCR BIT-1:

Logic 0 = Force -RTS output to a logic 1. (normal

default condition)

Logic 1 = Force -RTS output to a logic 0.

MCR BIT-2:

In the normal mode, this bit is associated the RST

(buffered reset output) function and is enabled by bit-

5 of the IER register. The RST function is available on

28 pin ST16C1451 package only. The 48 pin

ST16C1450/51 package all provide the RST function.

While in the normal mode, the logical state of the RST

pin will follow exactly the logical state of RESET pin,

i.e., soft resets are disabled. During special mode

operation, soft resets from MCR bit 2 are ORd with

the state of the input pin, RESET. Therefore both reset

types will be seen at the RST pin.

Logic 0 = The RST output pin is a logic 0. (normal

default condition)

Logic 1 = The RST output pin is a logic 1

In the loop-back mode where MCR bit-4 is a logic 1 this

bit is used to write the state of the modem -RI interface

signal.

Loop-back mode, Logic 0 = sets -RI internally to a logic

Loop-back mode, Logic 1 = sets -RI internally to a logic

MCR BIT-3

This bit controls the tri-state interrupt function or in the

loop-back mode this bit is used to control the modem

-CD signal.

Logic 0 = Forces INT outputs to the tri-state mode or

ST16C1450/51

Rev. 3.10

sets -CD to a logic 1 in the loop-back mode. (normal

default condition).

Logic 1 = Forces the INT outputs to the active mode

or sets -CD to a logic 0 in the loop-back mode.

In the Loop-back mode, sets -CD internally to a logic

MCR BIT-4:

Enable the local loop-back mode (diagnostics). In this

mode the transmitter output (-TX) and the receiver

input (-RX), -CTS, -DSR, -CD, and -RI are discon-

nected from the 145X I/O pins. Internally the modem

data and control pins are connected into a loop-back

data configuration. In this mode, the receiver and

transmitter interrupts remain fully operational. The

Modem Control Interrupts are also operational, but the

interrupts sources are switched to the lower four bits of

the Modem Control. Interrupts continue to be con-

trolled by the IER register.

Logic 0 = Disable loop-back mode. (normal default

condition)

Logic 1 = Enable local loop-back mode (diagnostics).

MCR BIT 5-6:

Not Used - initialized to a logic 0.

MCR BIT-7:

Logic 0 = No power down mode. (normal default

condition)

Logic 1 = Enable power down mode with baud rate

generator circuitry disabled.

Line Status Register (LSR)

This register provides the status of data transfers

between. the 145X and the CPU.

LSR BIT-0:

Logic 0 = No data in receive holding register. (normal

default condition)

Logic 1 = Data has been received and is saved in the

receive holding register (RHR).

LSR BIT-1:

Logic 0 = No overrun error. (normal default condition)

Logic 1 = Overrun error. A data overrun error occurred

in the receive shift register. This happens when addi-

tional data arrives while the RHR is full. In this case the

previous data in the shift register is overwritten. Note

that under this condition the data byte in the receive

shift register is not transferred into the RHR, therefore

the data in the RHR is not corrupted by the error.

LSR BIT-2:

Logic 0 = No parity error. (normal default condition)

Logic 1 = Parity error. The receive character does not

have correct parity information and is suspect.

LSR BIT-3:

Logic 0 = No framing error. (normal default condition)

Logic 1 = Framing error. The receive character did not

have a valid stop bit(s).

LSR BIT-4:

Logic 0 = No break condition. (normal default condi-

tion)

Logic 1 = The receiver received a break signal (RX

was a logic 0 for at least one character frame time).

LSR BIT-5:

This bit indicates that the 145X is ready to accept new

characters for transmission. This bit causes the 145X

to issue an interrupt to the CPU when the transmit

holding register is empty and the interrupt enable is

set.

Logic 0 = Transmit holding register (THR) is not

empty.

Logic 1 = Transmit holding register is empty. When

this bit is a logic 1, the CPU can load a maximum of

1 new characters into the Transmit Holding Register

for transmission. (normal default condition)

LSR BIT-6:

Logic 0 = Transmitter holding (THR) and shift registers

(TSR) are full.

Logic 1 = Transmitter holding and shift registers are

empty.

LSR BIT-7:

Not Used - initialized to a logic 0.

Modem Status Register (MSR)

This register provides the current state of the control

interface signals from the modem, or other peripheral

device that the 145X is connected to. Four bits of this

ST16C1450/51

Rev. 3.10

These bits are set to a logic 1 whenever a control input

from the modem changes state. These bits are set to

a logic 0 whenever the CPU reads this register.

MSR BIT-0:

Logic 0 = No -CTS Change (normal default condition)

Logic 1 = The -CTS input to the 145X has changed

state since the last time it was read. A modem Status

Interrupt will be generated.

MSR BIT-1:

Logic 0 = No -DSR Change. (normal default condition)

Logic 1 = The -DSR input to the 145X has changed

state since the last time it was read. A modem Status

Interrupt will be generated.

MSR BIT-2:

Logic 0 = No -RI Change. (normal default condition)

Logic 1 = The -RI input to the 145X has changed from

a logic 0 to a logic 1. A modem Status Interrupt will be

generated.

MSR BIT-3:

Logic 0 = No -CD Change. (normal default condition)

Logic 1 = Indicates that the -CD input to the has

changed state since the last time it was read. A

modem Status Interrupt will be generated.

MSR BIT-4:

During normal operation, this bit is the compliment of

the -CTS input. During the loop-back mode this bit is

equivalent to MCR bit-1 (-RTS).

MSR BIT-5:

During normal operation, this bit is the compliment of

the -DSR input. During the loop-back mode, this bit is

equivalent to MCR bit-0 (-DTR).

MSR BIT-6:

During normal operation, this bit is the compliment of

the -RI input. Reading this bit in the loop-back mode

produces the state of MCR bit-2 for packages support-

ing the RST (soft reset) feature. The RST function is

associated with the 28 pin ST16C1451 and the 48 pin

ST16C1450/51 package only.

MSR BIT-7:

During normal operation, this bit is the compliment of

the -CD input. Reading this bit in the loop-back mode

produces the state of MCR bit-3 (INT - Interrupt).

Note: Whenever any MSR bit(s) 0-3: are set to logic

1, a MODEM Status Interrupt will be generated.

Scratchpad Register (SPR)

The ST16C145X provides a temporary data register to

store 8 bits of user information.

ST16C1450/51 EXTERNAL RESET CONDITIONS

REGISTERS

RESET STATE

IER

IER BITS 0-7=0

ISR

ISR BIT-0=1, ISR BITS 1-7=0

LCR

LCR BITS 0-7=0

MCR

MCR BITS 0-7=0

LSR

LSR BITS 0-4=0,

LSR BITS 5-6=1 LSR, BIT 7=0

MSR

MSR BITS 0-3=0,

MSR BITS 4-7=input signals

SIGNALS

RESET STATE

High

SOFT reset

High

-RTS

High

-DTR

High

INT

Three state

ST16C1450/51

Rev. 3.10

AC ELECTRICAL CHARACTERISTICS

=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.

Clock pulse duration

Oscillator/Clock frequency

MHz

Address strobe width

Address setup time

-IOR delay from chip select

-IOR strobe width

Chip select hold time from -IOR

Read cycle delay

12d

Delay from -IOR to data

12h

Data disable time

13d

-IOW delay from chip select

13w

-IOW strobe width

13h

Chip select hold time from -IOW

15d

Write cycle delay

16s

Data setup time

16h

Data hold time

17d

Delay from -IOW to output

100 pF load

18d

Delay to set interrupt from MODEM

100 pF load

input

19d

Delay to reset interrupt from -IOR

100 pF load

20d

Delay from stop to set interrupt

Rclk

21d

Delay from -IOR to reset interrupt

100 pF load

22d

Delay from stop to interrupt

23d

Delay from initial INT reset to transmit

Rclk

start

24d

Delay from -IOW to reset interrupt

Reset pulse width

Baud rate devisor

-1

Rclk

Symbol

Parameter

Limits

Units

Conditions

3.3

5.0

Min

Max

Min

Max

ST16C1450/51

Rev. 3.10

ABSOLUTE MAXIMUM RATINGS

Supply range

7 Volts

Voltage at any pin

GND - 0.3 V to VCC +0.3 V

Operating temperature

-40

C to +85

Storage temperature

-65

C to 150

Package dissipation

500 mW

DC ELECTRICAL CHARACTERISTICS

=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.

ILCK

Clock input low level

-0.3

0.6

-0.5

0.6

IHCK

Clock input high level

2.4

VCC

3.0

VCC

Input low level

-0.3

0.8

-0.5

0.8

Input high level

2.0

2.2

VCC

Output low level on all outputs

0.4

= 5 mA

Output low level on all outputs

0.4

= 4 mA

Output high level

2.4

= -5 mA

Output high level

2.0

= -1 mA

Input leakage

±10

Clock leakage

±10

Avg power supply current

1.3

Input capacitance

Symbol

Parameter

Limits

Units

Conditions

3.3

5.0

Min

Max

Min

Max

Package Dimensions

28 LEAD PLASTIC DUAL-IN-LINE

(600 MIL PDIP)

Rev. 1.00

SYMBOL

MIN

MAX

MIN

MAX

INCHES

0.160

0.250

4.06

6.35

0.015

0.070

0.38

1.78

0.125

0.195

3.18

4.95

0.014

0.024

0.36

0.56

0.030

0.070

0.76

1.78

0.008

0.014

0.20

0.38

1.380

1.565

35.05

39.75

0.600

0.625

15.24

15.88

0.485

0.580

12.32

14.73

0.100 BSC

2.54 BSC

0.600 BSC

15.24 BSC

0.600

0.700

15.24

17.78

0.115

0.200

2.92

5.08

MILLIMETERS

Seating

Plane

Note: The control dimension is the inch column

Package Dimensions

28 LEAD PLASTIC LEADED CHIP CARRIER

(PLCC)

Rev. 1.00

D 1

0.165

0.180

4.19

4.57

0.090

0.120

2.29

3.05

0.020

0.51

0.013

0.021

0.33

0.53

0.026

0.032

0.66

0.81

0.008

0.013

0.19

0.32

0.485

0.495

12.32

12.57

0.450

0.456

11.43

11.58

0.390

0.430

9.91

10.92

0.300 typ.

7.62 typ.

0.050 BSC

1.27 BSC

0.042

0.056

1.07

1.42

0.042

0.048

1.07

1.22

0.025

0.045

0.64

1.14

SYMBOL

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

Seating Plane

Note: The control dimension is the inch column

x H2

x H1

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user's specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.

Copyright 1991 EXAR Corporation
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ST16C1450/51

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ST16C1450/51