EXAR Corporation, 48720 Kato Road, Fremont, CA 94538

(510) 668-7000

FAX (510) 668-7017

ST16C2550

Rev. 3.20

PLCC Package

DUAL UART WITH 16-BYTE TRANSMIT

AND RECEIVE FIFOS

DESCRIPTION

The ST16C2550 (2550) is a dual universal asynchronous receiver and transmitter (UART). The ST16C2550 is

an improved version of the NS16C550 UART with higher operating speed and lower access time. The 2550

provides enhanced UART functions with 16 byte FIFOs, a modem control interface, and data rates up to 1.5Mbps.

Onboard status registers provide the user with error indications and operational status. System interrupts and

modem control features may be tailored by external software to meet specific user requirements. An internal loop-

back capability allows onboard diagnostics. Independent programmable baud rate generators are provided to

select transmit and receive clock rates from 50 Bps to 1.5 Mbps. The Baud rate generator can be configured for

either crystal or external clock input. The 2550 is available in a 40-pin plastic-DIP, 44-pin PLCC, and 48-pin TQFP

packages. The 40 pin package does not offer TXRDY and RXRDY pins (DMA Signal monitoring). Otherwise the

three package versions are the same. The 2550 is functionally compatible with the 16C2450. The 2550 is

fabricated in an advanced CMOS process to achieve low drain power and high speed requirements.

FEATURES

Pin and functionally compatible to ST16C2450/

Software compatible with INS8250, NS16C550

1.5Mbps transmit/receive operation (24MHz

Max.)

16 byte transmit FIFO to reduce the bandwidth

requirement of the external CPU.

16 byte receive FIFO with error flags to reduce the

bandwidth requirement of the external CPU.

Independent transmit and receive UART control

Four selectable Receive FIFO interrupt trigger

levels

Modem control signals (-CTS, -RTS, -DSR, -DTR,

-RI, -CD, and Software controllable line break)

Programmable character lengths (5, 6, 7, 8) with

Even, odd, or no parity

Status report register

Crystal or external clock input

460.8 Kbps transmit/receive operation with 7.3728

MHz crystal or external clock source

TTL compatible inputs, outputs

ORDERING INFORMATION

Part number

Pins Package

Operating temperature

ST16C2550CP40 40 PDIP

0° C to + 70° C

ST16C2550CJ44 44 PLCC

0° C to + 70° C

ST16C2550CQ48 48 TQFP

0° C to + 70° C

RXB

RXA

-TXRDYB

TXA

TXB

-OPB

-CSA

-CSB

RESET

-DTRB

-DTRA

-RTSA

-OPA

-RXRDYA

INTA

INTB

L
1

L
2

-I
OW

-C

-
R

X
RDY

-I
OR

-D

S
R

-R

I
B

-R

T
S

-C

T
S

-T

Y
A

-R

I
A

-C

-D

S
R

-C

T
S

ST16C2550CJ44

Part number

Pins Package

Operating temperature

ST16C2550IP40

40 PDIP

-40° C to + 85° C

ST16C2550IJ44

44 PLCC

-40° C to + 85° C

ST16C2550IQ48 48 TQFP

-40° C to + 85° C

ST16C2550

Rev. 3.20

48 Pin TQFP Package

40 Pin DIP Package

Figure 1, Package Descriptions, 40 pin, 48 pin ST16C2550

RXB

RXA

-TXRDYB

TXA

TXB

-OPB

-CSA

-CSB

N.C.

-I
OW

-C

-R

X
R

-I
OR

-D

S
R

-R

I
B

-R

T
S

-C

T
S

RESET

-DTRB

-DTRA

-RTSA

-OPA

-RXRDYA

INTA

INTB

N.C.

-TX

-R

I
A

-C

-D

S
R

-C

T
S

ST16C2550CQ48

RXB

RXA

TXA

TXB

-OPB

-CSA

-CSB

XTAL1

XTAL2

-IOW

-CDB

GND

VCC

-RIA

-CDA

-DSRA

-CTSA

RESET

-DTRB

-DTRA

-RTSA

-OPA

INTA

INTB

-CTSB

-RTSB

-RIB

-DSRB

-IOR

T
16

0CP

4
0

ST16C2550

Rev. 3.20

SYMBOL DESCRIPTION

Symbol

Signal

Pin Description

type

Address-0 Select Bit. - Internal register address selection.

Address-1 Select Bit. - Internal register address selection.

Address-2 Select Bit. - Internal register address selection.

-CS A-B

14,15 16,17 10,11

Chip Select A, B (active low) - This function is associated

with individual channels, A through B. These pins enable

data transfers between the user CPU and the 2550 for the

channel(s) addressed. Individual UART sections (A, B) are

addressed by providing a logic 0 on the respective -CS A-

B pin.

D0-D7

1-8

2-9

44-48

I/O

1-3

Data Bus (Bi-directional) - These pins are the eight bit, three

state data bus for transferring information to or from the

controlling CPU. D0 is the least significant bit and the first

data bit in a transmit or receive serial data stream.

GND

Pwr

Signal and power ground.

INT A-B

30,29 33,32 30,29

Interrupt A, B (three state) - This function is associated with

individual channel interrupts, INT A-B. INT A-B are enabled

when MCR bit-3 is set to a logic 1, interrupts are enabled in

the interrupt enable register (IER), and when an interrupt

condition exists. Interrupt conditions include: receiver er-

rors, available receiver buffer data, transmit buffer empty,

or when a modem status flag is detected.

-IOR

Read strobe. (active low Strobe) - A logic 0 transition on this

pin will load the contents of an Internal register defined by

address bits A0-A2 onto the 2550 data bus (D0-D7) for

access by an external CPU.

-IOW

Write strobe. (active low strobe) - A logic 0 transition on this

pin will transfer the contents of the data bus (D0-D7) from

the external CPU to an internal register that is defined by

address bits A0-A2.

-OP2 A-B

31,13 35,15

32,9

Output -2 (User Defined). - This function is associated with

ST16C2550

Rev. 3.20

SYMBOL DESCRIPTION

Symbol

Signal

Pin Description

type

individual channels, A through B. The state at these pin(s)

are defined by the user and through the software setting of

MCR register bit-3. INT A-B are set to the active mode and

OP2 to a logic 0 when MCR-3 is set to a logic 1. INT A-B are

set to the three state mode and OP2 to a logic 1 when MCR-

3 is set to a logic 0. See bit-3, Modem Control Register

(MCR bit-3).

RESET

Reset. (active high) - A logic 1 on this pin will reset the

internal registers and all the outputs. The UART transmitter

output and the receiver input will be disabled during reset

time. (See ST16C2550 External Reset Conditions for ini-

tialization details.)

-RXRDY A-B

34,23 31,18

Receive Ready A-B (active low) - This function is associ-

ated with 44 pin PLCC and 48 pin TQFP packages only. This

function provides the RX FIFO/RHR status for individual

receive channels (A-B). RXRDY is primarily intended for

monitoring DMA mode 1 transfers for the receive data

FIFOs. A logic 0 indicates there is receive data to read/

unload, i.e., receive ready status with one or more RX

characters available in the FIFO/RHR. This pin is a logic 1

when the FIFO/RHR is empty or when the programmed

trigger level has not been reached. This signal can also be

used for single mode transfers (DMA mode 0).

-TXRDY A-B

1,12

43,6

Transmit Ready A-B (active low) - This function is associ-

ated with 44 pin PLCC and 48 pin TQFP packages only.

These outputs provide the TX FIFO/THR status for indi-

vidual transmit channels (A-B). TXRDY is primarily in-

tended for monitoring DMA mode 1 transfers for the trans-

mit data FIFOs. An individual channels -TXRDY A-B buffer

ready status is indicated by logic 0, i.e., at least one location

is empty and available in the FIFO or THR. This pin goes to

a logic 1 when there are no more empty locations in the

FIFO or THR. This signal can also be used for single mode

transfers (DMA mode 0).

VCC

Pwr

Power supply input.

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