ST16C2552

PLCC Package

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs

DESCRIPTION

The ST16C2552 is a dual asynchronous receiver and
transmitter with 16 byte transmit and receive FIFOs.
Independent programmable baud rate generators are
provided to select transmit and receive clock rates
from 50Hz to 1.5 MHz for each UART.
The on board status registers of the ST16C2552
provide the error conditions, type and status of the
transfer operation being performed. Complete MO-
DEM control capability and a processor interrupt
system that may be software tailored to the user's
requirements are included. The ST16C2552 provides
internal loop-back capability for on board diagnostic
testing.
Signalling for DMA transfers is done through two pins
per channel ( TXRDY*, RXRDY* ). The RXRDY*
function is multiplexed on one pin with the OP2* and
BAUDOUT functions. CPU can select these functions
through the Alternate Function Register.
The ST16C2552 is fabricated in an advanced 0.6

CMOS process to achieve low power and high speed
requirements.

FEATURES

Pin to pin and functional compatible to National
NS16C552

16 byte transmit FIFO

16 byte receive FIFO with error flags

Modem control signals (CTS*, RTS*, DSR*, DTR*,
RI*, CD*)

Programmable character lengths (5, 6, 7, 8) bits

Even, odd, or no parity bit generation and detection

Status report register

TTL compatible inputs, outputs

Independent transmit and receive control

Software compatible with INS8250, NS16C550

460.8 kHz transmit/receive operation with 7.372
MHz crystal or external clock source

ORDERING INFORMATION

Part number

Package

Operating temperature

ST16C2552CJ44

PLCC

0° C to + 70° C

ST16C2552IJ44

PLCC

-40° C to + 85° C

Printed December 17, 1996

XTAL1

GND

XTAL2

CHSEL

INTB

RXA

TXA

DTRA*

RTSA*

MFA*

INTA

VCC

TXRDYB*

RIB*

CDB*

DSRB*

RDY

CDA

ST16C2552CJ44

STARTECH

An Company

Rev. 2.0

3-135

ST16C2552CQ48

N.C.

XTAL1

GND

XTAL2

CHSEL

INTB

IOW

ESE

SB*

IOR

SB*

RXA

TXA

DTRA*

RTSA*

MFA*

INTA

VCC

TXRDYB*

RIB*

CDB*

DSRB*

N.C.

YA*

SA*

3-136

ST16C2552

BLOCK DIAGRAM

D0-D7

IOR*

IOW*

RESET

A0-A2

CS*

CHSEL

INTA
INTB

TXRDY* A/B

RXRDY* A/B

DTR A/B*
RTS A/B*
MF A/B*

CTS A/B*
RI A/B*
CD A/B*
DSR A/B*

TX A/B

RX A/B

t
a

Con

t
r
ol

ogi

s
t
e
r

e
l
ect

i
c

Modem

Control

Logic

t
e
rru

Con

t
r
ol

i
c

Transmit

FIFO

Registers

Transmit

Shift

Register

Receive

FIFO

Registers

Receive

Shift

Register

t
e
r

t
B

s

L

i
n

e
s

Con

t
r
ol

i
g

Clock

Baud Rate

Generator

3-137

ST16C2552

Symbol

Pin

Signal Type

Pin Description

SYMBOL DESCRIPTION

D0-D7

2-9

I/O

Bi-directional data bus. Eight bit, three state data bus to
transfer information to or from the CPU. D0 is the least
significant bit of the data bus and the first serial data bit to
be received or transmitted.

RX A/B

39,25

Serial data input A/B. The serial information (data) received
from serial port to ST16C2552 receive input circuit. A mark
(high) is logic one and a space (low) is logic zero. During the
local loopback mode the RX input is disabled from external
connection and connected to the TX output internally.

TX A/B

38,26

Serial data output A/B. The serial data is transmitted via
this pin with additional start , stop and parity bits. The TX will
be held in mark (high) state during reset, local loopback
mode or when the transmitter is disabled.

CS*

Chip select. (active low) A low at this pin enables the
ST16C2552 / CPU data transfer operation.

CHSEL

UART A/B select. UART A or B can be selected by changing
the state of this pin when CS* is active. Low on this pin,
selects the UART B and high on this pin selects UART A
section.

XTAL1

Crystal input 1 or external clock input. A crystal can be
connected to this pin and XTAL2 pin to utilize the internal
oscillator circuit. An external clock can be used to clock
internal circuit and baud rate generator for custom transmis-
sion rates.

XTAL2

Crystal input 2 or buffered clock output. See XTAL1.
Should be left open if a clcok is connected to XTAL1.

IOW*

Write strobe. (active low) A low on this pin will transfer the
contents of the CPU data bus to the addressed register.

IOR*

Read strobe. (active low) A low level on this pin transfers
the contents of the ST16C2552 data bus to the CPU.

A0-A2

10,14,15

Address select lines. To select internal registers.

3-138

ST16C2552

Symbol

Pin

Signal Type

Pin Description

SYMBOL DESCRIPTION

INT A/B

34,17

Interrupt output A/B. (active high) This pin goes high (when
enabled by the interrupt enable register) whenever a re-
ceiver error, receiver data available, transmitter empty, or
modem status condition flag is detected.

MF* A/B

35,19

OP2* (interrupt enable), BAUDOUT* and RXRDY* outputs.
These outputs are multiplexed via Alternate Function Reg-
ister. When output enable function is selected the MF* pin
stays high when INT out pin is set to three state mode and
goes low when INT pin is enabled. See bit-3 modem control
register (MCR bit-3). When BAUDOUT function is selected,
the 16 X TX/RX Baud rate clock output is generated.
RXRDY function can be selected to use to request a DMA
transfer of data from the Receive data FIFO. OP2* is the
default signal and it is selected immediately after master
reset or power-up.

TXRDY* A/B

1,32

Transmit ready. (active low) This pin goes high when the
transmit FIFO of the ST16C2552 is full. It can be used as a
single or multi-transfer.

RTS* A/B

36,23

Request to send A/B (active low). To indicate that the
transmitter has data ready to send. Writing a "1" in the
modem control register (MCR bit-1 ) will set this pin to a low
state. After the reset this pin will be set to high. Note that
this pin does not have any effect on the transmit or receive
operation.

DTR* A/B

37,27

Data terminal ready A/B (active low). To indicate that
ST16C2552 is ready to receive data. This pin can be
controlled via the modem control register (MCR bit-0).
Writing a "1" at the MCR bit-0 will set the DTR* output to low.
This pin will be set to high state after writing a "0" to that
register or after the reset . Note that this pin does not have
any effect on the transmit or receive operation.

RESET

Master reset. (active high) A high on this pin will reset all the
outputs and internal registers. The transmitter output and
the receiver input will be disabled during reset time.

3-139

ST16C2552

Symbol

Pin

Signal Type

Pin Description

SYMBOL DESCRIPTION

CTS* A/B

40,28

Clear to send A/B (active low). The CTS* signal is a
MODEM control function input whose conditions can be
tested by reading the MSR BIT-4. CTS* has no effect on the
transmit or receive operation.

DSR* A/B

41,29

Data set ready A/B (active low). A low on this pin indicates
the MODEM is ready to exchange data with UART. This pin
does not have any effect on the transmit or receive opera-
tion.

CD* A/B

42,30

Carrier detect A/B (active low). A low on this pin indicates
the carrier has been detected by the modem.

RI* A/B

43,31

Ring detect indicator A/B (active low). A low on this pin
indicates the modem has received a ringing signal from
telephone line.

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