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Электронный компонент: ST16C554DIJ68

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EXAR Corporation, 48720 Kato Road, Fremont, CA 94538
(510) 668-7000
FAX (510) 668-7017
ST16C554/554D
ST68C554
Rev. 3.10
PLCC Package
QUAD UART WITH 16-BYTE FIFOS
DESCRIPTION
The ST16C554D is a universal asynchronous receiver
and transmitter (UART) with a dual foot print interface.
The 554D is an enhanced UART with 16 byte FIFOs,
receive trigger levels and data rates up to 1.5Mbps.
Onboard status registers provide the user with error
indications and operational status, modem interface
control. System interrupts may be tailored to meet
user requirements. An internal loopback capability
allows onboard diagnostics. The 554D is available in
64 pin TQFP, and 68 pin PLCC packages. The 68 pin
PLCC package offer an additional 68 mode which
allows easy integration with Motorola, and other popu-
lar microprocessors. The ST16C554CQ64 (64 pin)
offers three state interrupt control while the
ST16C554DCQ64 provides constant active interrupt
outputs. The 64 pin devices do not offer TXRDY/
RXRDY outputs. The 554D combines the package
interface modes of the 16C554 and 68C554 series on
a single integrated chip.
FEATURES
Compatibility with the Industry Standard
ST16C454, ST68C454, ST68C554, TL16C554
1.5 Mbps transmit/receive operation (24MHz)
16 byte transmit FIFO
16 byte receive FIFO with error flags
Independent transmit and receive control
Software selectable Baud Rate Generator
Four selectable Receive FIFO interrupt trigger
levels
Standard modem interface
ORDERING INFORMATION
Part number
Pins Package Operating temperature
ST16C554DCJ68
68
PLCC
0 C to + 70 C
ST16C554DCQ64 64
TQFP
0 C to + 70 C
ST16C554CQ64
64
TQFP
0 C to + 70 C
ST16C554DIJ68
68
PLCC
-40 C to + 85 C
ST16C554DIQ64
64
TQFP
-40 C to + 85 C
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
-DSRA
-CTSA
-DTRA
VCC
-RTSA
INTA
-CSA
TXA
-IOW
TXB
-CSB
INTB
-RTSB
GND
-DTRB
-CTSB
-DSRB
-C
D
B
-R
I
B
RX
B
VC
C
16/
-
6
8
A2
A1
A0
XT
AL
1
XT
AL
2
RE
S
E
T
-R
X
R
D
Y
-
T
X
RDY
GND
RX
C
-R
I
C
-C
D
C
-DSRD
-CTSD
-DTRD
GND
-RTSD
INTD
-CSD
TXD
-IOR
TXC
-CSC
INTC
-RTSC
VCC
-DTRC
-CTSC
-DSRC
-C
D
A
-R
I
A
RX
A
GND
D7
D6
D5
D4
D3
D2
D1
D0
IN
T
S
E
L
VC
C
RX
D
-R
I
D
-C
D
D
ST16C554DCJ68
16 MODE
ST16C554/554D/68C554
2
Rev. 3.10
64 Pin TQFP Package
68 Pin PLCC Package
Figure 1, Package Descriptions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
-DSRA
-CTSA
-DTRA
VCC
-RTSA
INTA
-CSA
TXA
-IOW
-TXB
-CSB
INTB
-RTSB
GND
-DTRB
-CTSB
-D
S
R
B
-C
D
B
-R
I
B
RXB
VCC
A2
A1
A0
XTAL
1
XTAL
2
RES
E
T
GND
RXC
-R
I
C
-C
D
C
-D
S
R
C
-DSRD
-CTSD
-DTRD
GND
-RTSD
INTD
-CSD
TXD
-IOR
TXC
-CSC
INTC
-RTSC
VCC
-DTRC
-CTSC
-C
D
A
-R
I
A
RXA
GND
D7
D6
D5
D4
D3
D2
D1
D0
VCC
RXD
-R
I
D
-C
D
D
ST16C554CQ64
ST16C554DCQ64
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
-DSRA
-CTSA
-DTRA
VCC
-RTSA
-IRQ
-CS
TXA
R/-W
TXB
A3
N.C.
-RTSB
GND
-DTRB
-CTSB
-DSRB
-C
D
B
-R
I
B
RX
B
VC
C
16/
-
68
A2
A1
A0
XT
AL
1
XT
AL
2
-R
E
S
E
T
-R
X
R
D
Y
-
T
X
RDY
GND
RX
C
-R
I
C
-C
D
C
-DSRD
-CTSD
-DTRD
GND
-RTSD
N.C.
N.C.
TXD
N.C.
TXC
A4
N.C.
-RTSC
VCC
-DTRC
-CTSC
-DSRC
-C
D
A
-R
I
A
RX
A
GND
D7
D6
D5
D4
D3
D2
D1
D0
N.
C.
VC
C
RX
D
-R
I
D
-C
D
D
ST16C554DCJ68
68 MODE
ST16C554/554D/68C554
3
Rev. 3.10
Figure 2, Block Diagram 16 Mode
D0-D7
-IOR
-IOW
RESET
A0-A2
-CS A-D
INT A-D
-RXRDY
-TXRDY
INTSEL
-DTR A-D
-RTS A-D
-CTS A-D
-RI A-D
-CD A-D
-DSR A-D
TX A-D
RX A-D
XTAL1
XTAL2
D
a
ta
b
u
s
&
C
o
ntr
ol Lo
g
i
c
Regi
st
er
Se
lec
t
L
ogi
c
Modem
Control
Logic
I
nte
r
r
up
t
C
o
ntr
ol
L
ogi
c
Transmit
FIFO
Registers
Transmit
Shift
Register
Receive
FIFO
Registers
Receive
Shift
Register
In
t
e
r C
o
n
n
ec
t
Bu
s L
i
ne
s
&
C
o
ntr
ol si
gn
als
Cl
ock &
Bau
d
Rat
e
G
e
ne
r
a
to
r
ST16C554/554D/68C554
4
Rev. 3.10
Figure 3, Block Diagram 68 Mode
D0-D7
R/-W
-RESET
A0-A4
-CS
-IRQ
-RXRDY
-TXRDY
-DTR A-D
-RTS A-D
-CTS A-D
-RI A-D
-CD A-D
-DSR A-D
TX A-D
RX A-D
XTAL1
XTAL2
Da
ta
b
u
s
&
C
o
n
t
r
o
l Lo
g
i
c
Re
g
i
st
e
r
Se
l
e
ct
L
ogi
c
Modem
Control
Logic
I
nte
r
r
up
t
Co
n
t
r
o
l
L
ogi
c
Transmit
FIFO
Registers
Transmit
Shift
Register
Receive
FIFO
Registers
Receive
Shift
Register
In
t
e
r Co
n
n
e
c
t Bu
s
L
i
n
e
s
&
C
o
n
t
r
o
l si
g
n
a
l
s
Cl
o
c
k
&
Ba
u
d
Ra
t
e
G
e
n
er
ator
ST16C554/554D/68C554
5
Rev. 3.10
SYMBOL DESCRIPTION
Symbol
Pin
Signal
Pin Description
68
64
type
16/-68
31
-
I
16/68 Interface Type Select (input with internal pull-up). -
This input provides the 16 (Intel) or 68 (Motorola) bus
interface type select. The functions of -IOR, -IOW, INT A-
D, and -CS A-D are re-assigned with the logical state of this
pin. When this pin is a logic 1, the 16 mode interface
16C554D is selected. When this pin is a logic 0, the 68 mode
interface (68C554) is selected. When this pin is a logic 0, -
IOW is re-assigned to -R/W, RESET is re-assigned to -
RESET, -IOR is not used, and INT A-D(s) are connected in
a WIRE-OR configuration. The WIRE-OR outputs are
connected internally to the open source IRQ signal output.
This pin is not available on 64 pin packages which operate
in the 16 mode only.
A0
34
24
I
Address-0 Select Bit. Internal registers address selection in
16 and 68 modes.
A1
33
23
I
Address-1 Select Bit. Internal registers address selection in
16 and 68 modes.
A2
32
22
I
Address-2 Select Bit. - Internal registers address selection
in 16 and 68 modes.
A3-A4
20,50
-
I
Address 3-4 Select Bits. - When the 68 mode is selected,
these pins are used to address or select individual UARTs
(providing -CS is a logic 0). In the 16 mode, these pins are
reassigned as chip selects, see -CSB and -CSC. These pins
are not available on 64 pin packages which operate in the
16 mode only.
-CS
16
-
I
Chip Select. (active low) - In the 68 mode, this pin functions
as a multiple channel chip enable. In this case, all four
UARTs (A-D) are enabled when the -CS pin is a logic 0. An
individual UART channel is selected by the data contents of
address bits A3-A4. When the 16 mode is selected (68 pin
device), this pin functions as -CSA, see definition under -CS
A-B. This pin is not available on 64 pin packages which
operate in the 16 mode only.