Exar

Corporation 48720 Kato Road, Fremont CA, 94538

(510) 668-7000

FAX (510) 668-7017

www.exar.com

áç

ST16C650A

2.90V TO 5.5V UART WITH 32-BYTE FIFO

JANUARY 2004

REV. 5.0.0

GENERAL DESCRIPTION

The ST16C650A

(650A) is a 2.90 to 5.5 volt

Universal Asynchronous Receiver and Transmitter
(UART) with 5 volt tolerant inputs. This device
supports Intel and PC ISA mode data bus interfaces
and is software compatible to industry standard
16C450, 16C550, ST16C580 and ST16C650A
UARTs.

The 650A has 32 bytes of TX and RX FIFOs and is
capable of operating up to serial data rates of 3.125
Mbps at 5 volt supply voltage. The internal registers
include the 16C550 register set plus Exar's enhanced
registers for additional features to support today's
highly demanding data communication needs. The
enhanced features include automatic hardware and
software flow control, selectable TX and RX trigger
levels, and wireless infrared (IrDA) encoder/decoder.

The device provides a new capability to give user the
ability to program the wireless infrared encoder
output pulse width, hence reducing the power
consumption of a handheld unit.

The ST16C650A device comes in the 44-pin PLCC
and 48-pin TQFP packages in both the commercial
and industrial temperature ranges.

OTE

1 Covered by US patents #5,649,122.

FEATURES

Added features in top mark date code of "HC YYWW"
and newer:

2.90 to 5.5 Volt Operation

5 Volt Tolerant Inputs

Automatic RS485 Half-Duplex Control Output

Programmable Infrared Encoder Pulse Width

Sleep Mode with Wake-up Indicator

Device ID & Revision

Up to 3.125 Mbps Data Rate at 5 Volts

Added feature in top mark date code of "I2 YYWW"
and newer:

0 ns address hold time

Intel or PC Mode 8-bit Bus Interface

32-byte Transmit and Receive FIFOs

Automatic Hardware (RTS/CTS) Flow Control

Hardware Flow Control Hysteresis

Automatic Software (Xon/Xoff) Flow Control

APPLICATIONS

Battery Operated Electronics

Handheld Terminal

Personal Digital Assistants

Cellular Phones DataPort

Wireless Infrared Data Communications Systems

IGURE

1. B

LOCK

IAGRAM

XTAL1/CLK
XTAL2

Crystal Osc/Buffer

DTR#, DSR#,
RTS#, CTS#,
CD#, RI#

Intel,

Motorola

or PC

Data Bus

Interface

32 Byte TX FIFO

Baud Rate Generator

Infrared Encoder and

Pulse Width Control

Transmitter

UART

Configuration

Regs

IOR

IOR#

32 Byte RX FIFO

Infrared

Decoder

Receiver with Auto

Software Flow Control

Modem Control Signals

CTS Flow

Control

RTS Flow

Control

BRG

Prescaler

CS1

CS0

DDIS#

INT

TXRDY#

RDRDY#

A2:A0

D7:D0

IOW

CS2#

SEL

S2
S3
IRQA
IRQB
IRQC

IOW#

RESET

PC Mode:

COM 1 to 4

Decode Logic

ST16C650A

áç

2.90V TO 5.5V UART WITH 32-BYTE FIFO

REV. 5.0.0

IGURE

2. I

NTEL

AND

MODE

44-PLCC PACKAGE

48-TQFP PACKAGE

N.C.

RCLK

N.C.

CS0

CS1

-CS2

-BAUDOUT

IOW

IOR

SEL

RESET

OP1#

DTR#

RTS#

OP2#

INT

RXRDY#

N.C.

ST16C650ACQ48

Intel Bus Mode (SEL = VCC)

I
S

N.C.

LPT1#

IOR

AEN

SEL

RESET

OP1#

DTR#

RTS#

IRQA

IRQB

N.C.

CD#

ST16C650ACQ48

PC Mode (SEL = GND)

RCLK

N.C.

CS0

CS1

CS2#

BAUDOUT#

RESET

OP1#

DTR#

RTS#

OP2#

SEL

INT

RXRDY#

N.C

VCC

CD#

DSR

CTS#

XTAL

IOW#

IOW

N.C

IOR#

IOR

IS#

TXRD

AS#

ST16C650ACJ44

Intel Bus Mode (SEL = VCC)

LPT1#

RESET

OP1#

DTR#

RTS#

SEL

IRQA

IRQB

VCC

CD#

DSR#

GND

ST16C650ACJ44

PC Mode (SEL = GND)

40-PDIP PACKAGE

S2#

UDO

AL1

AL2

RI#

ESET

OP1#

DTR#

OP2#

RDY

AS#

DDI

ST16C650ACP40

áç

ST16C650A

REV. 5.0.0

2.90V TO 5.5V UART WITH 32-BYTE FIFO

PIN DESCRIPTIONS

ORDERING INFORMATION

ART

UMBER

ACKAGE

PERATING

EMPERATURE

ANGE

EVICE

TATUS

ST16C650ACP40

40-Lead PDIP

0°C to +70°C

Discontinued. See the ST16C650ACQ48 for a replacement.

ST16C650ACJ44

44-Lead PLCC

0°C to +70°C

Active

ST16C650ACQ48

48-Lead TQFP

0°C to +70°C

Active

ST16C650AIP40

40-Lead PDIP

-40°C to +85°C

Discontinued. See the ST16C650AIQ48 for a replacement.

ST16C650AIJ44

44-Lead PLCC

-40°C to +85°C

Active

ST16C650AIQ48

48-Lead TQFP

-40°C to +85°C

Active

AME

40-

PDIP
P

44-

PLCC

48-

TQFP

YPE

ESCRIPTION

16 (Intel) MODE DATA BUS INTERFACE. The SEL pin is connected to VCC.

Address bus lines [2:0]

A2:A0 selects internal UART's configuration registers.

Data bus lines [7:0] (bidirectional)

IOR#

Input/Output Read (active low)

The falling edge instigates an internal read cycle and retrieves the data
byte from an internal register pointed by the address lines [A2:A0], places
it on the data bus to allow the host processor to read it on the leading
edge. Its function is the same as IOR, except it is active low. Either an
active IOR# or IOR is required to transfer data from 650A to CPU during a
read operation. If this input is unused, it should be connected to VCC to
minimize supply current.

IOR

Input/Output Read (active high)

Same as IOR# but active high. If this input is unused, it should be con-
nected to GND to minimize supply current.

IOW#

Input/Output Write (active low) - Intel bus mode

The falling edge instigates the internal write cycle and the trailing edge
transfers the data byte on the data bus to an internal register pointed by
the address lines [A2:A0]. Its function is the same as IOW, except it is
active low. Either an active IOW# or IOW is required to transfer data from
650A to the Intel type CPU during a write operation. If this input is unused,
it should be connected to VCC to minimize supply current.

ST16C650A

áç

2.90V TO 5.5V UART WITH 32-BYTE FIFO

REV. 5.0.0

IOW

Input/Output Write (active high)

Same as IOW# but active high. If this input is unused, it should be con-
nected to GND to minimize supply current.

CS0

Chip Select 0 input (active high)

This input selects the ST16C650A device. If CS1 or CS2# is used as the
chip select then this pin must be connected to VCC. The 650A is selected
when all three chip selects are active. See

Figure 3

through

Figure 5

CS1

Chip Select 1 input (active high)

This input selects the ST16C650A device. If CS0 or CS2# is used as the
chip select then this pin must be connected to VCC. The 650A is selected
when all three chip selects are active. See

Figure 3

through

Figure 5

CS2#

Chip Select 2 input (active low)

This input selects the ST16C650A device. If CS0 or CS1 is used as the
chip select then this pin must be connected to GND. The 650A is selected
when all three chip selects are active. See

Figure 3

through

Figure 5

INT

Interrupt Output

This output becomes active whenever the transmitter, receiver, line and/or
modem status register has an active condition. See interrupt section for
more detail. When IM# pin is at logic 0 (Intel bus mode), this interrupt out-
put may be set to normal active high or active high open source to provide
wire-OR capability by connecting a 1k to 10k ohms resistor between this
pin and ground.

AS#

Address Strobe input (active low)

In the Intel bus mode, the leading-edge transition of AS# latches the chip
selects (CS0, CS1, CS2#) and the address lines A0, A1 and A2. This
input is used when the address lines are not stable for the duration of a
read or write operation. In devices with top mark date code of "I2 YYWW"
and newer, the address bus is latched even if this input is not used. These
devices feature a '0 ns' address hold time.

See "AC Electrical Characteris-

tics"

. If not required, this input can be permanently tied to GND.

TXRDY#

UART Transmitter Ready (active low)

The output provides the TX FIFO/THR status. See

Table 2

. If it is not

used, leave it unconnected.

RXRDY#

UART Receiver Ready (active low)

This output provides the RX FIFO/RHR status for receive channel A. See

Table 2

. If it is not used, leave it unconnected.

PC Mode Interface Signals. Connect SEL pin to GND and IM# pin to GND to select PC Mode.

PC mode additional Address Lines

In the PC mode, these are the additional address lines from the host
address bus. They are inputs to the on-board chip select decode function
for COM 1-4 and LPT ports. See

Table 1

for details. The pins A4 and A9

have internal 100k

pull-up resistors.

AME

40-

PDIP
P

44-

PLCC

48-

TQFP

YPE

ESCRIPTION

áç

ST16C650A

REV. 5.0.0

2.90V TO 5.5V UART WITH 32-BYTE FIFO

AEN#

Address Enable input (active low)

When AEN# transition to logic 0, it decodes and validates COM 1-4 ports
address per S1, S2 and S3 inputs.

Select 1 to 3

These are the standard PC COM 1-4 ports and IRQ selection inputs. See

Table 1

and

Table 3

for details. The S1 pin has an internal 100k

pull-up

resistor.

IRQA

IRQB

IRQC

Interrupt Request A, B and C Outputs (active high, tri-state)

These are the interrupt outputs associated with COM 1-4 to be connected
to the host data bus. See interrupt section for details. The Interrupt
Requests A, B or C functions as IRQx to the PC bus. IRQx is enabled by
setting MCR bit-3 to logic 1 and the desired interrupt(s) in the interrupt
enable register (IER).

LPT1#

Line Printer Port-1 Decode Logic Output (active low)

This pin functions as the PC standard LPT-1 printer port address decode
logic output, see

Table 1

. The baud rate generator clock output, BAUD-

OUT#, is internally connected to the RCLK input in the PC mode.

LPT2#

Line Printer Port-2 Decode Logic Output (active low)

This pin functions as the PC standard LPT-2 printer port address decode
logic output, see

Table 1

MODEM OR SERIAL I/O INTERFACE

Transmit Data or wireless infrared transmit data

This output is active low in normal standard serial interface operation (RS-
232, RS-422 or RS-485) and active high in the infrared mode. Infrared
mode can be enabled by connecting pin ENIR to VCC or through software
setting after power up.

Receive Data or wireless infrared receive data

Normal received data input idles at logic 1 condition and logic 0 in the
infrared mode. The wireless infrared pulses are applied to the decoder.
This input must be connected to its idle logic state in either normal, logic 1,
or infrared mode, logic 0, else the receiver may report "receive break" and/
or "error" condition(s).

RTS#

Request to Send or general purpose output (active low)

This port may be used for one of two functions:

1) automatic hardware flow control, see EFR bit-6, MCR bit-1and IER bit-
6.

2) RS485 half-duplex direction control, see XFR bits 2 and 5.

RTS# output must be asserted before auto RTS flow control can start.

CTS#

Clear to Send or general purpose input (active low)

If used for automatic hardware flow control, data transmission will be
stopped when this pin is de-asserted and will resume when this pin is
asserted again. See EFR bit-7 and IER bit-7.

DTR#

Data Terminal Ready or general purpose output (active low)

DSR#

Data Set Ready input or general purpose input (active low)

AME

40-

PDIP
P

44-

PLCC

48-

TQFP

YPE

ESCRIPTION

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ST16C650ACJ44

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ST16C650ACJ44