XR-T56L85
...the analog plus company
TM
Low Power
PCM Line Interface
Rev. 2.01
E
1992
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538
z
(510) 668-7000
z
FAX (510) 668-7017
1
June 1997-3
FEATURES10
D
Low Power (Typical 14mA)
D
Single +5V Supply
D
Up to 2.048 Mbps Operation in Both TX and RX
Directions
D
Receiver Input can be:
Balanced Transformer Coupled
Capacitively (Twisted Pair)
Single Coaxial Capacitive Coupling
APPLICATIONS
D
T1 and CEPT Interfaces
D
CPI
D
DMI
GENERAL DESCRIPTION
The XR-T56L85 is a PCM line interface chip. It consists of
both transmit and receive circuitry in a DIL 18 pin
package. The maximum bit rate the chip can handle is
2.048 Mbps and the signal level to the received can be
attenuated by 10dB of cable loss at half the bit rate. Total
current consumption is between 12-16mA at +5V.
ORDERING INFORMATION
Part No.
Package
Operating
Temperature Range
XR-T56L85N
18 Lead 300 Mil CDIP
-40
C to +85
C
XR-T56L85D
18 Lead 300 Mil JEDEC SOIC
-40
C to +85
C
BLOCK DIAGRAM
5
14
12
16
17
18
9
3
2
11
8
4
10
6
15
13
1
PDC
Positive
Threshold
Comparator
Negative
Threshold
Comparator
Peak
Detector
TTL Buffer
TTL Buffer
TTL Buffer
TTL Buffer
TTL Buffer
Bias
Bias
RPOS
RCLK
TE
RNEG
TANK BIAS
BIAS
TXDATA+
TXDATA-
RXDATA+
RXDATA-
RXV
CC
RXGND
TXV
CC
TPOS
TCLK
TNEG
TXGND
Figure 1. Block Diagram
+
+
7
XR-T56L85
2
Rev. 2.01
PIN CONFIGURATION
18
1
10
9
2
3
4
5
6
7
15
14
13
12
11
17
16
8
TXV
CC
TPOS
TCLK
TXDATA+
TXGND
TXDATA-
TNEG
RPOS
PDC
RXDATA+
RXDATA-
TE
BIAS
TANK BIAS
RXGND
RCLK
RNEG
RXV
CC
18 Lead CDIP (0.300")
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
TXV
CC
TPOS
TCLK
TXDATA+
PDC
RXDATA+
RXDATA-
TE
TXGND
TXDATA-
TNEG
RPOS
BIAS
TANK BIAS
RXGND
RCLK
RNEG
RXV
CC
18 Lead SOIC (Jedec, 0.300")
PIN DESCRIPTION
Pin #
Symbol
Type
Description
1
PDC
Peak Detector Capacitor. This pin should be connected to a 0.1
F capacitor
2
RXDATA+
I
Receive Analog Input Positive. The AMI signal received from the line is applied at this and
the RX DATA(-) pin. Data and clock from the signal applied at these two pins recovered and
output on the RPOS, RNEG, and RCLK pins, respectively.
3
RXDATA-
I
Receive Analog Input Negative. See the description for RX DATA(+).
4
TE
O
LC Tank Excitation Output. This output connects to one side of the tank circuitry.
5
BIAS
O
Bias. This pin should be tied to ground through a 0.1
F capacitor.
6
TANK BIAS
Tank Reference. The tank circuitry is biased via this output.
7
RXGND
Receiver Ground. To minimize ground interference a separate pin is used to ground the re-
ceiver section.
8
RCLK
O
Recovered Receive Clock. Recovered clock signal from the AMI signal received at the RX
DATA(+) and RX DATA(-) pins. This signal is output to the terminal equipment.
9
RXV
CC
Receive Supply Voltage. 5V supply voltage for the Receive Section.
10
RNEG
O
Receive Negative Data Output. A signal at this pin corresponds to the receipt of a negative
pulse on the RX DATA(+)/RX DATA(-) pins. This TTL compatible signal is output to the
terminal equipment.
11
RPOS
O
Receive Positive Data Output. A signal at this pin corresponds to the receipt of a positive
pulse on the RX DATA(+)/RX DATA pins. This TTL compatible signal is outputed to the
terminal equipment.
12
TNEG
I
Transmit Negative Data Input. TTL input for a negative polarity pulse (the negative portion
of the AMI pulse train) to be transmitted to the line via the TX DATA(+) and TX DATA pins.
13
TXDATA-
O
Transmit Negative Data Output. This pin, along with the TX DATA(+) pin, forms a differential
driver output, this is used to drive AMI data down the line via a transformer. Note: This is an
open-collector output.
14
TXGND
Transmit Ground.
15
TXDATA+
O
Transmit Positive Data Output. Please see description for TX DATA(-).
16
TCLK
I
Transmit Clock. TPOS and TNEG are sampled on the rising edge of TCLK.
17
TPOS
I
Transmit Positive Data Input. TTL input for a positive polarity pulse (the positive portion of
the AMI pulse train) to be transmitted to the line via the TX DATA(+) and TX DATA(-) pins.
18
TXVcc
Transmit Supply Voltage. 5V supply voltage to the transmit section.
XR-T56L85
3
Rev. 2.01
ELECTRICAL CHARACTERISTICS
Test Conditions: V
CC
= 5V
$
5%, T
A
= -40
C to +85
C, Unless Otherwise Specified
Parameters
Min.
Typ.
Max.
Unit
Conditions
DC Electrical Characteristics
Supply Voltage
4.75
5
5.25
V
Supply Current
14
16
mA
Total Current to Pin 9 & Pin 18 (Transmit-
ter Outputs Open and All Ones Pattern)
Receiver Section
Tank Drive Current
300
500
700
A
Measured at Pin 4, V
CC
= 5V
Clock Output Low
0.3
0.6
V
Measured at Pin 8, I
OL
= 1.6mA
Clock Output High
3.0
3.6
V
Measured at Pin 8, I
OH
=400
A
Data Output Low
0.3
0.6
V
Measured at Pin 10 & 11, I
OL
=1.6mA
Data Output High
3.0
3.6
V
Measured at Pin 10 & 11, I
OH
=400
A
Transmitter Section
Driver Output Low
0.6
0.9
1.2
V
Measured at Pin 13 & 15, I
OL
=-40mA
Output Leakage Current
100
A
Measured in Off State
Output Pull-up to +20V
Input High Voltage
2.2
V
Measured at Pin 12, 16 & 17
I
OL
= -40mA, V
OL
= 1.0V
Input Low Voltage
0.8
V
Measured at Pin 12, 16 & 17
Output Off
Input Low Current
-1.6
mA
Measured at Pin 12, 16 & 17
Input Low Voltage = 0.4V
Input High Current
40
A
Measured at Pin 12, 16 & 17
Input Low Voltage = 0.4V
Output Low Current
-30
mA
Measured at Pin 13 & 15
V
OL
= 1.0V
AC Electrical Characteristices
Receiver Section
Input Level
6
6.6
Vpp
Measured Between Pin 2 & 3
Loss Input Signal Alarm Level
0.6
Vpp
Measured Between Pin 2 & 3
Alarm on Pull Data/Clock Output High
Input Impedance at 2.048MHz
2.5
k
Measured Between Pin 2 & 3
With Sinewave Input
Clock Duty Cycle
35
50
65
%
Measured at Pin 8 at 2.0V DC Level
Clock Rise & Fall Time
20
40
ns
Measured at Pin 8, CL = 15pF
Data Pulse Width
35
50
75
% of
clock
period
Measured at Pin 10 & 11
At 1V DC Level, Cable Loss =
O
dB
Transmitter Section
Pulse Width at 2.048MHz
234
244
264
ns
Measured at Pin 13 & 15
Figure 3
Output Rise Time
12
25
ns
Figure 3
Output Fall Time
12
25
ns
Figure 3
Output Fall Imbalance
2.5
ns
At 50% Output Level
XR-T56L85
4
Rev. 2.01
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
+20V
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature
-65
C to 150
C
. . . . . . . . . . . . . .
SYSTEM DESCRIPTION
The Receiver
The incoming bipolar PCM signal, which is attenuated
and distorted by the cable is applied to the receiver input,
consisting of the RX DATA(+) and RX DATA(-) pins, either
through a balanced transformer, a balanced capacitively
coupled terminal or a single-ended coaxial cable (see
Figure 5). A peak detector following the input generates a
DC reference for the positive and negative threshold
comparator (to extract the positive and negative data
pulses). Information on the positive and negative data
pulses is outputed as TTL compatible signals at pins
RPOS and RNEG, respectively. More specifically, an
output signal present at the RPOS pin indicates that a
positive pulse was received at the RX DATA(+)/RX
DATA(-) pins, from the incoming bipolar data stream.
Likewise an output signal present at the RNEG pin
indicates that a negative pulse was received at the RX
DATA(+)/RX DATA(-) pins. This conversion from the
bipolar signal to TTL compatible signals allows for digital
processing of the clock and data signals by the terminal
equipment. An example of the waveforms of the TTL
compatible recovered clock and data as output by the
receiver portion of the chip is presented in
Figure 2,
Figure 3 and Figure 5. A tank circuit tuned to the
appropriate frequency is added externally to provide the
appropriate frequency-selective filtering of the received
clock signal.
The Transmitter
The transmitter portion of the chip receives TTL
compatible signals and transmits a corresponding bipolar
data stream down the line (See
Figure 5). TPOS and
TNEG are TTL compatible signals that dictate the polarity
of the pulse to be generated and transmitted on the output
bipolar data stream. Both TPOS and TNEG inputs are
sampled by the rising edge of the transmit clock, TCLK.
The TX DATA(+) and TX DATA(-) pins form a differential
driver output, this is used to drive AMI data down the line
via a transformer. The TX DATA(+) and TX DATA(-) pins
are open-collector outputs.
When a logic "high" signal is applied to the TPOS pin, a
positive pulse (the positive portion of the bipolar data
stream) will be transmitted to the line via the TX DATA(+)
O/P and TX DATA(-) O/P pins. Likewise, when a logic
"high" signal is applied to the TNEG pin, a negative pulse
will be transmitted to the line via the TX DATA(+) and TX
DATA(-) pins. An illustration of the key waveforms
involved in this TTL to AMI conversion process, in the
Transmitter portion of the chip is presented in
Figure 4.
XR-T56L85
5
Rev. 2.01
100
0.1
F
V
CC
=5V
0V
CL=15pF
Output
0V
Pin 13 & 15
Pin 7 &14
Pulse
Input
XR-T56L85
Generator
2.048Mbps
Figure 2.
Pin 9 &18
Pin 12, 16, 17
90%
244ns
Input Pulse
from Generator
10%
1.5V
Output from Pin 13
or Pin 15
1.5V
10%
90%
<5ns
<5ns
Vol
+5V
0V
3V
Rise Time
Pulse Width
Fall Time
15ns Typ.
Figure 3.
15ns Typ.
XR-T56L85
6
Rev. 2.01
RXDATA+
RCLK Output At Pin 8
RPOS Output At Pin 11
RNEG Output At Pin 10
TCLK Clock To Pin 16
TPOS To Pin 17
TNEG To Pin 12
Bipolar Signal At
Transformer Output
Figure 4. Receiver Timing Diagram With 1-1-1-1-1-1 Pattern
XR-T56L85
7
Rev. 2.01
TIP
T2
PE65415
1:1:1
56
V
CC
0.1
F
RXDATA+
2
RXDATA-
3
BIAS
5
T.E.
4
RGND
1
RCLK 8
PDC
9
18
TXDATA+
15
TXDATA-
13
TGND
14
RNEG
10
RPOS
11
TNEG
12
TPOS 17
TCLK 16
TANK BIAS
6
XR-T56L85
RING
56
RNEG
RPOS
TNEG
TPOS
TCLK
RCLK
0.1
F
V
CC
Figure 5. Application Circuit for XR-T56L85
7
TIP
RING
T1
L
C
1:1
Device
1.544Mbs
2.048Mbs
L
C
60
H
175pF
60
H
100pF
4
.7
F
RV
CC
U1
56L85TA
L=Tank Coil AIE 4150804 (1.544 and 2.048 Mbs)
75
0.1
F
0.1
F
0.1
F
0.1
F
120
120
0.1
F
TIP
RING
3
5
2
5
3
2
5
3
2
2
3
5
RCACON
V
CC
0.1
F
0.1
F
0.1
F
XR-T56L85
8
Rev. 2.01
A
0.100
0.200
2.54
5.08
A
1
0.015
0.070
0.38
1.78
B
0.014
0.026
0.36
0.66
B
1
0.045
0.065
1.14
1.65
c
0.008
0.018
0.20
0.46
D
0.860
0.960
21.84
24.38
E
1
0.250
0.310
6.35
7.87
E
0.300 BSC
7.62 BSC
e
0.100 BSC
2.54 BSC
L
0.125
0.200
3.18
5.08
0
15
0
15
D
B
e
B
1
18 LEAD CERAMIC DUAL-IN-LINE
(300 MIL CDIP)
Rev. 1.00
SYMBOL
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
18
1
9
10
c
E
1
L
A
1
Seating
Plane
Base
Plane
A
E
Note: The control dimension is the inch column
XR-T56L85
9
Rev. 2.01
SYMBOL
MIN
MAX
MIN
MAX
A
0.093
0.104
2.35
2.65
A
1
0.004
0.012
0.10
0.30
B
0.013
0.020
0.33
0.51
C
0.009
0.013
0.23
0.32
D
0.447
0.463
11.35
11.75
E
0.291
0.299
7.40
7.60
e
0.050 BSC
1.27 BSC
H
0.394
0.419
10.00
10.65
L
0.016
0.050
0.40
1.27
0
8
0
8
INCHES
MILLIMETERS
18 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC)
Rev. 1.00
e
18
10
9
D
E
H
B
A
L
C
A
1
Seating
Plane
Note: The control dimension is the millimeter column
1
XR-T56L85
10
Rev. 2.01
Notes
XR-T56L85
11
Rev. 2.01
Notes
XR-T56L85
12
Rev. 2.01
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user's specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.
Copyright 1992 EXAR Corporation
Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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