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2000 Fairchild Semiconductor Corporation
DS010262
www.fairchildsemi.com
February 1990
Revised August 2000
1
00331 Low
Power T
r
i
p
le D-T
y
pe

Fl
ip-
F
lop
100331
Low Power Triple D-Type Flip-Flop
General Description
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com-
mon Clock (CP
C
), and Master Set (MS) and Master Reset
(MR) inputs. Each flip-flop has individual Clock (CP
n
),
Direct Set (SD
n
) and Direct Clear (CD
n
) inputs. Data enters
a master when both CP
n
and CP
C
are LOW and transfers
to a slave when CP
n
or CP
C
(or both) go HIGH. The Master
Set, Master Reset and individual CD
n
and SD
n
inputs over-
ride the Clock inputs. All inputs have 50 k
pull-down
resistors.
Features
s
35% power reduction of the 100131
s
2000V ESD protection
s
Pin/function compatible with 100131
s
Voltage compensated operating range
=
-
4.2V to
-
5.7V
s
Available to industrial grade temperature range
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagrams
24-Pin DIP/SOIC
28-Pin PLCC
Order Number
Package Number
Package Description
100331SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100331PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100331QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100331QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
-
40
C to
+
85
C)
Pin Names
Description
CP
0
CP
2
Individual Clock Inputs
CP
C
Common Clock Input
D
0
D
2
Data Inputs
CD
0
CD
2
Individual Direct Clear Inputs
SD
n
Individual Direct Set Inputs
MR
Master Reset Input
MS
Master Set Input
Q
0
-Q
2
Data Outputs
Q
0
Q
2
Complementary Data Outputs
www.fairchildsemi.com
2
100331
Truth Tables
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Don't Care
U
=
Undefined
t
=
Time before CP Positive Transition
t
+
1
=
Time after CP Positive Transition
=
LOW-to-HIGH Transition
Logic Diagram
Synchronous Operation (Each Flip-Flop)
Inputs
Outputs
D
n
CP
n
CP
C
MS
MR
Q
n
(t
+
1)
SD
n
CD
n
L
L
L
L
L
H
L
L
L
H
L
L
L
L
L
H
L
L
L
H
X
L
L
L
L
Q
n
(t)
X
H
X
L
L
Q
n
(t)
X
X
H
L
L
Q
n
(t)
Asynchronous Operation (Each Flip-Flop)
Inputs
Outputs
D
n
CP
n
CP
C
MS
MR
Q
n
(t
+
1)
SD
n
CD
n
X
X
X
H
L
H
X
X
X
L
H
L
X
X
X
H
H
U
3
www.fairchildsemi.com
1
00331
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics
(Note 3)
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
0
C to
+
85
C
Note 3: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under "worst case" conditions.
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Maximum Junction Temperature (T
J
)
+
150
C
Pin Potential to Ground Pin (V
EE
)
-
7.0V to
+
0.5V
Input Voltage (DC)
V
EE
to
+
0.5V
Output Current
(DC Output HIGH)
-
50 mA
ESD (Note 2)
2000V
Case Temperature (T
C
)
Commercial
0
C to
+
85
C
Industrial
-
40
C to
+
85
C
Supply Voltage (V
EE
)
-
5.7V to
-
4.2V
Symbol
Parameter
Min
Typ
Max
Units
Conditions
V
OH
Output HIGH Voltage
-
1025
-
955
-
870
mV
V
IN
=
V
IH
(Max)
Loading with
V
OL
Output LOW Voltage
-
1830
-
1705
-
1620
mV
or V
IL
(Min)
50
to
-
2.0V
V
OHC
Output HIGH Voltage
-
1035
mV
V
IN
=
V
IH
(Min)
Loading with
V
OLC
Output LOW Voltage
-
1610
mV
or V
IL
(Max)
50
to
-
2.0V
V
IH
Input HIGH Voltage
-
1165
-
870
mV
Guaranteed HIGH Signal
for All Inputs
V
IL
Input LOW Voltage
-
1830
-
1475
mV
Guaranteed LOW Signal
for All Inputs
I
IL
Input LOW Current
0.5
A
V
IN
=
V
IL
(Min)
I
IH
Input HIGH Current
240
A
V
IN
=
V
IH
(Max)
I
EE
Power Supply Current
-
122
-
65
mA
Inputs OPEN
www.fairchildsemi.com
4
100331
Commercial Version
(Continued)
DIP AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND
SOIC and PLCC AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND
Symbol
Parameter
T
C
=
0
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
f
MAX
Toggle Frequency
375
375
375
MHz
Figures 2, 3
t
PLH
Propagation Delay
0.75
2.00
0.75
2.00
0.75
2.00
ns
t
PHL
CP
C
to Output
Figures 1, 3
t
PLH
Propagation Delay
0.75
2.00
0.75
2.00
0.75
2.00
ns
t
PHL
CP
n
to Output
t
PLH
Propagation Delay
0.70
1.70
0.70
1.70
0.70
1.80
CP
n
, CP
C
=
L
Figures 1, 4
t
PHL
CD
n
, SD
n
to Output
ns
t
PLH
0.70
2.00
0.70
2.00
0.70
2.00
CP
n
, CP
C
=
H
t
PHL
t
PLH
Propagation Delay
1.10
2.60
1.10
2.60
1.10
2.60
CP
n
, CP
C
=
L
t
PHL
MS, MR to Output
ns
t
PLH
1.10
2.80
1.10
2.80
1.10
2.80
CP
n
, CP
C
=
H
t
PHL
t
TLH
Transition Time
0.35
1.30
0.35
1.30
0.35
1.30
ns
Figures 1, 3, 4
t
THL
20% to 80%, 80% to 20%
t
S
Setup Time
Figure 5
D
n
0.40
0.40
0.40
ns
CD
n
, SD
n
(Release Time)
1.30
1.30
1.30
Figure 4
MS, MR (Release Time)
2.30
2.30
2.30
t
H
Hold Time D
n
0.5
0.5
0.7
ns
Figure 5
t
PW
(H)
Pulse Width HIGH
CP
n
, CP
C
, CD
n
,
2.00
2.00
2.00
ns
Figures 3, 4
SD
n
, MR, MS
Symbol
Parameter
T
C
=
0
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
f
MAX
Toggle Frequency
400
400
400
MHz
Figures 2, 3
t
PLH
Propagation Delay
0.75
1.80
0.75
1.80
0.75
1.80
ns
t
PHL
CP
C
to Output
Figures 1, 3
t
PLH
Propagation Delay
0.75
1.80
0.75
1.80
0.75
1.80
ns
t
PHL
CP
n
to Output
t
PLH
Propagation Delay
0.70
1.50
0.70
1.50
0.70
1.60
CP
n
, CP
C
=
L
Figures 1, 4
t
PHL
CD
n
, SD
n
to Output
ns
t
PLH
0.80
1.80
0.70
1.80
0.70
1.80
CP
n
, CP
C
=
H
t
PHL
t
PLH
Propagation Delay
1.10
2.40
1.10
2.40
1.10
2.40
CP
n
, CP
C
=
L
t
PHL
MS, MR to Output
ns
t
PLH
1.10
2.60
1.10
2.60
1.10
2.60
CP
n
, CP
C
=
H
t
PHL
t
TLH
Transition Time
0.35
1.10
0.35
1.10
0.35
1.10
ns
Figures 1, 3, 4
t
THL
20% to 80%, 80% to 20%
t
S
Setup Time
Figure 5
D
n
0.30
0.30
0.30
CD
n
, SD
n
(Release Time)
1.20
1.20
1.20
ns
Figure 4
MS, MR (Release Time)
2.20
2.20
2.20
t
H
Hold Time D
n
0.5
0.5
0.7
ns
Figure 5
t
PW
(H)
Pulse Width HIGH
CP
n
, CP
C
, CD
n
,
2.00
2.00
2.00
ns
Figures 3, 4
SD
n
, MR, MS
5
www.fairchildsemi.com
1
00331
Commercial Version
(Continued)
Note 4: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-
aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (t
OSHL
), or LOW-to-HIGH (t
OSLH
), or in opposite
directions both HL and LH (t
OST
). Parameters t
OST
and t
PS
guaranteed by design.
Symbol
Parameter
T
C
=
0
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
0.75
1.40
0.75
1.40
0.80
1.50
ns
Figures 1, 3 PLCC Only
t
PHL
CP
C
to Output
t
PLH
Propagation Delay
0.70
1.40
0.75
1.40
0.80
1.50
ns
t
PHL
CP
n
to Output
t
PLH
Propagation Delay
0.70
1.50
0.70
1.50
0.80
1.60
CP
n
, CP
C
=
L
Figures 1, 4
t
PHL
CD
n
, SD
n
to Output
ns
PLCC Only
t
PLH
0.80
1.70
0.80
1.70
0.80
1.80
CP
n
, CP
C
=
H
t
PHL
PLCC Only
t
PLH
Propagation Delay
1.10
2.00
1.10
2.00
1.20
2.10
CP
n
, CP
C
=
L
t
PHL
MS, MR to Output
ns
PLCC Only
t
PLH
1.20
2.10
1.20
2.10
1.30
2.20
CP
n
, CP
C
=
H
t
PHL
PLCC Only
t
OSHL
Maximum Skew Common Edge
PLCC Only
Output-to-Output Variation
100
100
100
ps
(Note 4)
Common Clock to Output Path
t
OSHL
Maximum Skew Common Edge
PLCC Only
Output-to-Output Variation
235
235
235
ps
(Note 4)
CP
n
to Output Path
t
OSLH
Maximum Skew Common Edge
PLCC Only
Output-to-Output Variation
120
120
120
ps
(Note 4)
Common Clock to Output Path
t
OSLH
Maximum Skew Common Edge
PLCC Only
Output-to-Output Variation
275
275
275
ps
(Note 4)
CP
n
to Output Path
t
OST
Maximum Skew Opposite Edge
ps
PLCC Only
Output-to-Output Variation
125
125
125
(Note 4)
Common Clock to Output Path
t
OST
Maximum Skew Opposite Edge
ps
PLCC Only
Output-to-Output Variation
265
265
265
(Note 4)
CP
n
to Output Path
t
PS
Maximum Skew
PLCC Only
Pin (Signal) Transition Variation
90
90
90
ps
(Note 4)
Common Clock to Output Path
t
PS
Maximum Skew
PLCC Only
Pin (Signal) Transition Variation
90
90
90
ps
(Note 4)
CP
n
to Output Path