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Электронный компонент: 100344QI

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2000 Fairchild Semiconductor Corporation
DS009883
www.fairchildsemi.com
July 1988
Revised August 2000
1
00344 Low
Power 8-Bi
t Lat
c
h
wi
th Cut-
O
f
f Dri
vers
100344
Low Power 8-Bit Latch with Cut-Off Drivers
General Description
The 100344 contains eight D-type latches, individual inputs
(D
n
), outputs (Q
n
), a common enable pin (E), latch enable
(LE), and output enable pin (OEN). A Q output follows its D
input when both E and LE are LOW. When either E or LE
(or both) are HIGH, a latch stores the last valid data
present on its D input prior to E or LE going HIGH.
A HIGH on OEN holds the outputs in a cut-off state. The
cut-off state is designed to be more negative than a normal
ECL LOW level. This allows the output emitter-followers to
turn off when the termination supply is
-
2.0V, presenting a
high impedance to the data bus. This high impedance
reduces termination power and prevents loss of low state
noise margin when several loads share the bus.
The 100344 outputs are designed to drive a doubly termi-
nated 50
transmission line (25
load impedance). All
inputs have 50 k
pull-down resistors.
Features
s
Cut-off drivers
s
Drives 25
load
s
Low power operation
s
2000V ESD protection
s
Voltage compensated operating range
=
-
4.2V to
-
5.7V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
24-Pin DIP
28-Pin PLCC
Logic Symbol
Order Number
Package Number
Package Description
100344PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100344QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100344QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
-
40
C to
+
85
C)
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2
100344
Pin Descriptions
Truth Table
H
=
HIGH Voltage level
L
=
LOW Voltage level
Cutoff
=
lower-than-LOW state
X
=
Don't Care
Note 1: Retains data present before either LE or E go HIGH.
Logic Diagram
Pin Names
Description
D
0
D
7
Data Inputs
E
Enable Input
LE
Latch Enable Input
OEN
Output Enable Input
Q
0
Q
7
Data Outputs
Inputs
Outputs
D
n
E
LE
OEN
Q
n
L
L
L
L
L
H
L
L
L
H
X
H
X
L
Latched (Note 1)
X
X
H
L
Latched (Note 1)
X
X
X
H
Cutoff
3
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1
00344
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics
(Note 4)
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
0
C to
+
85
C
Note 4: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under "worst case" conditions.
AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND
Note 5: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Maximum Junction Temperature (T
J
)
+
150
C
V
EE
Pin Potential to Ground Pin
-
7.0V to
+
0.5V
Input Voltage (DC)
V
EE
to
+
0.5V
Output Current (DC Output HIGH)
-
100 mA
ESD (Note 3)
2000V
Case Temperature (T
C
)
Commercial
0
C to
+
85
C
Industrial
-
40
C to
+
85
Supply Voltage (V
EE
)
-
5.7V to
-
4.2V
Symbol
Parameter
Min
Typ
Max
Units
Conditions
V
OH
Output HIGH Voltage
-
1025
-
955
-
870
mV
V
IN
=
V
IH
(Max)
Loading with
V
OL
Output LOW Voltage
-
1830
-
1705
-
1620
mV
or V
IL
(Min)
25
to
-
2.0V
V
OHC
Output HIGH Voltage
-
1035
mV
V
IN
=
V
IH
(Min)
Loading with
V
OLC
Output LOW Voltage
-
1610
mV
or V
IL
(Max)
25
to
-
2.0V
V
OLZ
Cutoff LOW Voltage
-
1950
mV
V
IN
=
V
IH
(Min)
OEN
=
HIGH
or V
IL
(Max)
V
IH
Input HIGH Voltage
-
1165
-
870
mV
Guaranteed HIGH Signal for All Inputs
V
IL
Input LOW Voltage
-
1830
-
1475
mV
Guaranteed LOW Signal for All Inputs
I
IL
Input LOW Current
0.50
A
V
IN
=
V
IL
(Min)
I
IH
Input HIGH Current
240
A
V
IN
=
V
IH
(Max)
I
EE
Power Supply Current
Inputs Open
-
178
-
85
mA
V
EE
=
-
4.2V to
-
4.8V
-
185
-
85
V
EE
=
-
4.2V to
-
5.7V
Symbol
Parameter
T
C
=
0
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
0.90
2.10
0.90
2.10
1.00
2.30
ns
Figures 1, 2
t
PHL
D
n
to Output
(Note 5)
t
PLH
Propagation Delay
1.60
3.10
1.60
3.10
1.80
3.40
ns
Figures 1, 4
t
PHL
LE, E to Output
(Note 5)
t
PZH
Propagation Delay
1.60
4.20
1.60
4.20
1.60
4.20
ns
Figures 1, 2
t
PHZ
OEN to Output
1.00
2.70
1.00
2.70
1.00
2.70
(Note 5)
t
TLH
Transition Time
0.45
2.00
0.45
2.00
0.45
2.00
ns
Figures 1, 3
t
THL
20% to 80%, 80% to 20%
t
S
Setup Time
D
0
D
7
1.00
1.00
1.10
ns
Figures 1, 3
t
H
Hold Time
D
0
D
7
0.10
0.10
0.10
ns
Figures 1, 3
t
PW
(H)
Pulse Width HIGH
2.00
2.00
2.00
ns
Figures 1, 3
LE, E
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4
100344
Commercial Version
(Continued)
PLCC AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND
Note 6: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.
Note 7: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-
aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (t
OSHL
), or LOW-to-HIGH (t
OSLH
), or in opposite
directions both HL and LH (t
OST
). Parameters t
OST
and t
ps
guaranteed by design.
Symbol
Parameter
T
C
=
0
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
0.90
1.90
0.90
1.90
1.00
2.10
ns
Figures 1, 2
t
PHL
D
n
to Output
(Note 6)
t
PLH
Propagation Delay
1.60
2.90
1.60
2.90
1.80
3.20
ns
Figures 1, 4
t
PHL
LE, E to Output
(Note 6)
t
PZH
Propagation Delay
1.60
4.00
1.60
4.00
1.60
4.00
ns
Figures 1, 2
t
PHZ
OEN to Output
1.00
2.50
1.00
2.50
1.00
2.50
(Note 6)
t
TLH
Transition Time
0.45
1.90
0.45
1.90
0.45
1.90
ns
Figures 1, 3
t
THL
20% to 80%, 80% to 20%
t
S
Setup Time
D
0
D
7
0.90
0.90
1.00
ns
Figures 1, 3
t
H
Hold Time
D
0
D
7
0.00
0.00
0.00
ns
Figures 1, 3
t
PW
(H)
Pulse Width HIGH
2.00
2.00
2.00
ns
Figures 1, 3
LE, E
t
OSHL
Maximum Skew Common Edge
PLCC Only
Output-to-Output Variation
330
330
330
ps
(Note 7)
Data to Output Path
t
OSLH
Maximum Skew Common Edge
PLCC Only
Output-to-Output Variation
330
330
330
ps
(Note 7)
Data to Output Path
t
OST
Maximum Skew Opposite Edge
PLCC Only
Output-to-Output Variation
330
330
330
ps
(Note 7)
Data to Output Path
t
PS
Maximum Skew
PLCC Only
Pin (Signal) Transition Variation
230
230
230
ps
(Note 7)
Data to Output Path
5
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1
00344
Test Circuitry
Note:
V
CC
, V
CCA
=
+
2V, V
EE
=
-
2.5V
L1 and L2
=
equal length 50
impedance lines
R
T
=
50
terminator internal to scope
Decoupling 0.1
F from GND to V
CC
and V
EE
All unused outputs are loaded with 25
to GND
C
L
=
Fixture and stray capacitance
3 pF
FIGURE 1. AC Test Circuit
Switching Waveforms
FIGURE 2. Propagation Delay and Cutoff Times
FIGURE 3. Setup, Hold and Pulse Width Times
FIGURE 4. Propagation Delay LE, E to Q